Access method and device

Abstract

The invention provides an access method and device. The method is applied to the computer equipment, the computer equipment comprises a processor and a memory, the computer equipment further comprises at least one physical memory page and at least one temporary storage page, and each physical memory page is mapped to the memory. In the process of accessing the target virtual memory page based on the access instruction, if the target virtual memory page is not mapped to the physical memory page, the target temporary storage page is allocated to the target virtual memory page, and the access operation is executed on the cache space corresponding to the target temporary storage page, so that the influence of page missing abnormity on degree access is effectively reduced, and the access efficiency is improved.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of computer technologies, and in particular, to an access method and device. Background Art

[0002] When a central processing unit (CPU) executes a program, the addresses in the program are all virtual addresses. When an application accesses a virtual address, if a page fault exception is triggered, the execution context of the computer device switches from the user mode to the kernel mode. The operating system (OS) executes the page fault exception handling process, that is, the OS allocates a physical page for the virtual page and updates the page table. Subsequently, the execution context switches back from the kernel mode to the user mode, and the application re-executes the access operation. Summary of the Invention

[0003] The present application provides an access method and device. In this method, when a computer device has a page fault exception, by allocating a temporary page for the virtual memory page, the access efficiency can be effectively improved, and the interruption of the program access caused by the page fault exception can be avoided.

[0004] In a first aspect, the present application provides an access method. This method is applied to a computer device, which includes a processor and a memory. The computer device also includes at least one physical memory page and at least one temporary page. Each physical memory page is mapped to the memory. The method includes: The computer device obtains an access instruction, and the access instruction is used to indicate accessing a target virtual memory page. The computer device queries whether the target virtual memory page is mapped to a physical memory page in response to the access instruction. In the case where the target virtual memory page is not mapped to a physical memory page, the computer device allocates a target temporary page for the target virtual memory page. An access operation is performed on the cache space corresponding to the target temporary page. In this way, by mapping the virtual page to the temporary page, the computer device can avoid the interruption caused by the page fault exception during the program access process, improve the access efficiency, and reduce the impact of the page fault exception on the program access.

[0005] Exemplarily, the processor stores (or maintains, provides) at least one physical memory page and at least one temporary page.

[0006] Exemplarily, the temporary page is not mapped to the memory.

[0007] In a possible implementation, the processor stores the usage information of each scratch page and the physical memory page allocation information. The usage information is used to indicate whether the corresponding scratch page is available, and the physical memory page allocation information is used to indicate the physical memory page allocated for the corresponding scratch page. In this way, the computer device can allocate scratch pages for virtual memory based on the available state. Moreover, the computer device can execute a latency processing flow based on the physical memory page allocation information. By maintaining the state of the scratch pages in real time, flexible allocation and dynamic maintenance of the scratch pages can be achieved.

[0008] Exemplarily, the physical memory page allocation information may be the flush to PPN flag in the embodiments of the present application (the name is only for illustrative purposes and is not limited in the present application).

[0009] In a possible implementation, allocating a target scratch page for a target virtual memory page includes: the computer device selects a target scratch page from the scratch pages indicated by the usage information as available. The computer device allocates the target scratch page for the target virtual memory page. The computer device updates the usage information of the target scratch page to unavailable. In this way, by marking the usage status of the scratch page, the computer device can avoid the same scratch page being reused.

[0010] Exemplarily, the computer device can select the scratch pages in sequence or randomly select an available scratch page, which is not limited in the present application.

[0011] Exemplarily, the "unavailable" of the scratch page can also be understood as the scratch page being invalid or occupied, that is, the scratch page marked as unavailable cannot be allocated to other virtual memory pages anymore.

[0012] In a possible implementation, when the access instruction is a write instruction, performing a corresponding access operation on the cache space corresponding to the target scratch page includes: writing data into the cache space corresponding to the target scratch page. In this way, after allocating the scratch page in the present application, data can be directly written into the cache without executing the interrupt process of the page fault exception, which can effectively improve the access efficiency and shorten the duration occupied by the page fault exception handling. Especially for the program access on the user side, by shortening the processing duration, the user can be "unaware".

[0013] In a possible implementation, after performing a corresponding access operation on the cache space corresponding to the target temporary page, it further includes: when a preset condition is met, allocating a target physical memory page for the target temporary page. Updating the physical memory page allocation information of the target temporary page, and the updated physical memory page allocation information is used to indicate the target physical memory page allocated for the target temporary page. Updating the usage information of the target temporary page to available. In this way, after the access is executed, the related process of page fault exception is executed, avoiding program interruption and reducing the system processing pressure. Also, when the preset condition is met, the page fault exception handling process is executed, and the physical memory page is allocated by the OS, avoiding OS interruption during the reading of the application program and improving the efficiency.

[0014] Exemplarily, when the preset condition is met, the execution context is switched from the user mode to the kernel mode, and the OS allocates a target physical memory page for the target temporary page.

[0015] In a possible implementation, after performing a corresponding access operation on the cache space corresponding to the target temporary page, it further includes: detecting that the usage information of the target temporary page is updated to available, and based on the physical memory page allocation information of the target temporary page, writing the data in the cache space corresponding to the target temporary page into the memory corresponding to the target physical memory page. In this way, by the hardware's real-time monitoring of the status of the usage information of the temporary page, through the status switch of the usage information, the data in the cache can be written into the memory in a timely manner, thus releasing the cache resources in a timely manner. And writing the data back to the physical memory in a timely manner can ensure the security and stability of the data.

[0016] In a possible implementation, the preset condition includes at least one of the following: the load of the processor is less than the first threshold, the number of temporary pages whose usage information indicates unavailable exceeds the second threshold, and the timer timing ends.

[0017] In a possible implementation, the processor stores a reservation flag corresponding to each cache line, and the reservation flag is used to indicate whether to reserve the data in the corresponding cache line; after writing the data into the cache space corresponding to the target temporary page, it further includes: updating the reservation flag corresponding to each cache line of the cache space to reserved. In this way, by setting the reservation flag, the data corresponding to the temporary page can be avoided from being deleted, and the data can be reserved until the delayed processing flow stage (i.e., the data write-back stage).

[0018] In a possible implementation, the processor stores a page table, and the page table includes allocatable information for each virtual memory page. The allocatable information is used to indicate whether the corresponding virtual memory page can be allocated a scratch page. In this way, by recording the AAV (i.e., the allocatable information) of each virtual page, which virtual memory pages can be allocated scratch pages can be marked. When traversing the page table, it is possible to obtain whether the virtual page can be mapped to a physical memory page or a scratch page through the AAV, without waiting to find that the virtual page is unavailable during the page fault process, thus avoiding the overhead brought by this process.

[0019] In a possible implementation, allocating a target scratch page for a target virtual memory page includes: querying the allocatable information of the target virtual memory page; when it is queried that the allocatable information of the target virtual memory page indicates that the target virtual memory page can be allocated a scratch page, allocating a target scratch page for the target virtual memory page. In this way, the computer device can allocate a scratch page for the virtual memory based on the available state. Moreover, the computer device can execute a delay processing flow based on the physical memory page allocation information. By maintaining the state of the scratch page in real time, flexible allocation and dynamic maintenance of the scratch page can be achieved.

[0020] In a second aspect, the present application provides an access method. This method is applied to a computer device, and the method includes: the memory management unit MMU queries whether a first virtual memory page is mapped to a physical memory page in response to a first access indication obtained, and the first access instruction is used to indicate reading the first virtual memory page. When the first virtual memory page is not mapped to a physical memory page, the MMU allocates a target physical memory page for the first virtual memory page, and the target physical page includes specified data. In this way, in the data reading scenario, by allocating a specified physical page, the program interruption caused by a page fault exception can be avoided, effectively improving the program reading efficiency.

[0021] In a possible implementation, allocating a target physical memory page for the first virtual memory page includes: the MMU marks the first virtual memory page as a read-only page. In this way, by marking the virtual memory page as a read-only page, in a subsequent write scenario, a scratch page can be allocated for the virtual memory page based on this mark.

[0022] In a possible implementation, the computer device includes a processor and a memory. The processor maintains at least one physical memory page and at least one scratch page, and each physical memory page is mapped to the memory. The method further includes: the MMU queries whether a first virtual memory page is mapped to a physical memory page in response to a second access indication obtained; the second access indication is sent by the application program to the MMU in response to a second access instruction received, and the second access instruction is used to indicate writing to the first virtual memory page; when the first virtual memory page is already mapped to a target physical memory page and the first virtual memory page is a read-only page, the MMU allocates a target scratch page for the first virtual memory page.

[0023] In a possible implementation, the method further includes: The MMU queries whether the second virtual memory page is mapped to a physical memory page in response to the obtained third access indication, and the third access instruction is used to indicate reading the second virtual memory page; When the second virtual memory page is not mapped to a physical memory page, the MMU allocates a target physical memory page for the second virtual memory page, and the target physical page includes specified data.

[0024] In a possible implementation, the specified data is all-zero data.

[0025] In a third aspect, the present application provides an access device. The device is applied to a computer device, the computer device includes a processor and a memory, the computer device further includes at least one physical memory page and at least one scratch page, each physical memory page is mapped to the memory, and the device includes: an acquisition module, a query module, a first allocation module, and an execution module. The acquisition module is used to acquire an access instruction, and the access instruction is used to indicate accessing a target virtual memory page; The query module is used to query whether the target virtual memory page is mapped to a physical memory page in response to the access instruction; The first allocation module is used to allocate a target scratch page for the target virtual memory page when the target virtual memory page is not mapped to a physical memory page; The execution module is further used to perform an access operation on the cache space corresponding to the target scratch page.

[0026] In a possible implementation, the processor stores usage information of each scratch page and physical memory page allocation information, the usage information is used to indicate whether the corresponding scratch page is available, and the physical memory page allocation information is used to indicate the physical memory page allocated for the corresponding scratch page.

[0027] In a possible implementation, the allocation module is specifically used to: select a target scratch page from the scratch pages indicated by the usage information as available; allocate a target scratch page for the target virtual memory page; update the usage information of the target scratch page to unavailable.

[0028] In a possible implementation, the access instruction is a write instruction, and the execution module is specifically used to: write data into the cache space corresponding to the target scratch page.

[0029] In a possible implementation, the device further includes: a second allocation module, used to allocate a target physical memory page for the target scratch page when a preset condition is met; a first update module, used to update the physical memory page allocation information of the target scratch page, and the updated physical memory page allocation information is used to indicate the target physical memory page allocated for the target scratch page; a second update module, used to update the usage information of the target scratch page to available.

[0030] In a possible implementation, the apparatus further includes: a data processing module, configured to detect that the usage information of a target scratch page is updated to available, and write the data in the cache space corresponding to the target scratch page into the memory corresponding to the target physical memory page based on the physical memory page allocation information of the target scratch page.

[0031] In a possible implementation, the preset condition includes at least one of the following: the load of the processor is less than a first threshold, the number of scratch pages whose usage information indicates unavailable exceeds a second threshold, and the timer expires.

[0032] In a possible implementation, the processor stores a reservation flag corresponding to each cache line, and the reservation flag is used to indicate whether to reserve the data in the corresponding cache line; the apparatus further includes: a third update module, configured to update the reservation flag corresponding to each cache line in the cache space to reserved.

[0033] In a possible implementation, the processor stores a page table, and the page table includes allocatable information of each virtual memory page, and the allocatable information is used to indicate whether the corresponding virtual memory page can be allocated a scratch page.

[0034] In a possible implementation, the allocation module is specifically configured to: query the allocatable information of the target virtual memory page; and if it is queried that the allocatable information of the target virtual memory page indicates that the target virtual memory page can be allocated a scratch page, allocate a target scratch page for the target virtual memory page.

[0035] In a fourth aspect, an embodiment of the present application provides a computer device, including: a transceiver / transceiver pin and a processor. Optionally, a memory is further included. Wherein, the transceiver / transceiver pin, the processor, and the memory communicate with each other through an internal connection path; the processor is configured to execute instructions to control the transceiver / transceiver pin to send or receive signals; the memory is configured to store instructions. When the processor executes the instructions, the processor executes the method according to the first aspect or any possible implementation manner in the first aspect.

[0036] In a fifth aspect, an embodiment of the present application provides a computer-readable medium, configured to store a computer program, and the computer program includes instructions for executing the method according to the first aspect or any possible implementation manner in the first aspect.

[0037] In a sixth aspect, an embodiment of the present application provides a computer program, and the computer program includes instructions for executing the method according to the first aspect or any possible implementation manner in the first aspect.

[0038] In a seventh aspect, an embodiment of the present application provides a chip, which includes a processing circuit and transceiver pins. Wherein, the transceiver pins and the processing circuit communicate with each other through an internal connection path, and the processing circuit executes the method in the first aspect or any possible implementation manner of the first aspect to control the receiving pin to receive a signal and control the sending pin to send a signal.

[0039] In an eighth aspect, an embodiment of the present application provides a computer cluster, which includes at least one computer device, and the computer device is used to execute the method in the first aspect or any possible implementation manner of the first aspect. Description of the Drawings

[0040] Figure 1 Schematic diagram of the correspondence between virtual addresses and physical addresses shown for illustration purposes;

[0041] Figure 2 Schematic diagram of the TLB shown for illustration purposes;

[0042] Figure 3 Schematic diagram of the TLB query shown for illustration purposes;

[0043] Figure 4 Schematic diagram of the program access flow shown for illustration purposes;

[0044] Figure 5 Schematic diagram of the mapping relationship between virtual pages and physical pages shown for illustration purposes;

[0045] Figure 6 Schematic diagram of the memory allocation process shown for illustration purposes;

[0046] Figure 7 Schematic diagram of the memory allocation shown for illustration purposes;

[0047] Figure 8 Schematic diagram of the access flow shown for illustration purposes;

[0048] Figure 9 Schematic diagram of the memory page division shown for illustration purposes;

[0049] Figure 10 Schematic diagram of the write data process shown for illustration purposes;

[0050] Figure 11 Schematic diagram of the read data process shown for illustration purposes;

[0051] Figure 12 Schematic diagram of the delay processing process shown for illustration purposes;

[0052] Figure 13 Schematic diagram of the correspondence between scratch pages and caches shown for illustration purposes;

[0053] Figure 14 One of the structural schematic diagrams of the exemplary device;

[0054] Figure 15 One of the structural schematic diagrams of the exemplary device. Detailed implementation manners

[0055] Next, the technical solutions in the embodiments of the present application will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present application.

[0056] The term "and / or" in this article is merely a description of the association relationship of associated objects, indicating that there can be three relationships. For example, A and / or B can represent: A exists alone, A and B exist simultaneously, and B exists alone.

[0057] The terms "first" and "second" in the description and claims of the embodiments of the present application are used to distinguish different objects, rather than to describe a specific order of the objects. For example, the first target object and the second target object are used to distinguish different target objects, rather than to describe the specific order of the target objects.

[0058] In the embodiments of the present application, words such as "exemplary" or "for example" are used to represent examples, illustrations or explanations. Any embodiment or design solution described as "exemplary" or "for example" in the embodiments of the present application should not be construed as being more preferred or having more advantages than other embodiments or design solutions. Exactly speaking, using words such as "exemplary" or "for example" aims to present relevant concepts in a specific manner.

[0059] In the description of the embodiments of the present application, unless otherwise specified, the meaning of "a plurality of" refers to two or more. For example, a plurality of processing units refers to two or more processing units; a plurality of systems refers to two or more systems.

[0060] Before introducing the technical solutions in the embodiments of the present application, the background technology that the present application may involve will be briefly introduced first:

[0061] 1. Virtual address and physical address

[0062] During the execution of a program (which can also be referred to as an application program, and this application does not make any limitations), the addresses used by the program are all virtual addresses (VA). When the operating system loads a program into memory, it allocates an available physical address space for the program, that is, the physical memory space; the operating system maps the virtual addresses used in the program to specific physical addresses (PA), and this mapping is done in units of pages.

[0063] In a computer system, the memory management unit (MMU) realizes the mapping relationship between the virtual address and the physical address of the program through the paging mechanism. The virtual space in the operating system is divided in units of pages, which are virtual memory pages, also known as virtual pages. Correspondingly, the physical address space is also divided in units of pages, and the pages in the physical address space are called physical pages.

[0064] The pages corresponding to the virtual address and the physical address are numbered in sequence, which is called the page number. The so-called address mapping is to map a virtual page to a physical page. That is to say, replace the high-order bits of the virtual address with the high-order bits of the physical address.

[0065] In this mapping process, as Figure 1 shown, both the virtual address and the physical address are 64 bits, and correspondingly the space occupied by a page is 4KB; the lower 12 bits of the virtual address and the physical address (i.e., Addr[11:0]) remain unchanged, that is, the lower 12 bits of the virtual address and the lower 12 bits of the physical address are the same. This is because these 12 bits are used to represent the offset within a 4KB page. The high-order parts of the virtual address and the physical address, that is, the Addr[63:12] field, are called VPN (Virtual page number) in the virtual address, and PPN (Physical page number) in the physical address. The lower part of the address, that is, the Addr[11:0] field, is called the offset part. It can be seen that the offset part of the address remains unchanged during the mapping process.

[0066] 2. Page Table Cache and Page Table

[0067] TLB (Translation lookaside buffer), also known as the translation bypass cache or page table cache. During program execution, the operating system creates a complete mapping from virtual addresses to physical addresses for the program. This mapping is stored in a data structure called the "page table" (Page Table), where each entry in the page table contains the corresponding VPN information and PPN information. Address translation within the processor is typically performed by hardware, and the hardware that accomplishes this function is called TLB, which is the Translation Lookaside Buffer, and it can store a portion of the above-mentioned page table.

[0068] As Figure 2 shown is a general structure of the page table within the TLB, which contains 32 entries. The structure of each entry within the TLB is similar to that of each page table entry (Page table entry, PTE) within the page table (Page Table). The TLB can be regarded as a cache of the page table, storing a portion of the complete page table.

[0069] Among them, VPN is the high part of the virtual address. Taking a 64-bit address width (i.e., a 64-bit address) as an example, a virtual address can be represented as Vir_Addr[63:0]. When the page is set to 4KB, the VPN is Vir_Addr[63:12], that is, the VPN does not include the lower 12 bits of the address. PPN is the high part of the physical address. When the physical address is 64 bits wide, the physical address can be represented as Phy_Addr[63:0]. When the page is set to 4KB, the PPN is Phy_Addr[63:12]. It can be seen that the PPN also does not include the lower 12 bits of the address.

[0070] As Figure 3 shown, when the processor performs an address fetch operation or a memory access operation, the corresponding virtual address is sent to the TLB. The TLB extracts the VPN from this virtual address and then compares it with each entry within the TLB. If it is the same as the VPN within one of the entries, the PPN field within that entry is output, which is considered a TLB hit. If none of the entries have a VPN that is the same as the VPN to be translated, it is considered a TLB miss.

[0071] After a TLB Miss, it is necessary to search the page table for the PPN corresponding to the VPN, and then fill this VPN and PPN information into the TLB (usually overwriting an existing entry). This process is called a Page Table Walk. The Page Table Walk task can be automatically completed by hardware or by the operating system.

[0072] 3. Page Fault (PF)

[0073] Page Fault, also known as page fault, can also be called page fault exception, page error, etc., which is not limited in this application. As described above, during the address mapping process, the CPU first accesses the TLB. If there is a TLB Miss, the CPU further performs a page table walk (PTW) based on the virtual address, that is, searches the Page Table for the PPN corresponding to the virtual address. If none of the VPNs in the entries match the VPN to be translated, it is considered a Page Table Miss, and the MMU triggers a page fault exception, transferring control in the CPU to the page fault exception handler in the operating system kernel. The operating system (specifically the page fault exception handler in the operating system kernel, which will not be repeated hereinafter) executes the Page Fault process, allocates the corresponding physical memory for the virtual address, and updates the page table.

[0074] This approach can be called the lazy allocation mechanism, which is a physical memory allocation strategy. That is, physical memory pages are actually allocated only when accessed. By doing so, the OS allocates the corresponding physical memory only when it actually needs memory, that is, at the first use. Lazy allocation works because it is very rare for an application to immediately access all the pages it requests. Usually, the memory used by a program is much smaller than the memory space it applies for. Based on this characteristic of the program, the memory subsystem can allow multiple applications to execute concurrently, thereby improving the performance of the entire system without causing a memory shortage. Even though lazy allocation reduces the actual memory allocation for applications, it is still possible to allocate all the memory when many applications are running concurrently in the system. If the memory is exhausted, the swap mechanism is used to store the contents of some memory pages in a non-volatile storage device and reuse and reallocate them to other applications after the contents of these memory pages are cleared.

[0075] These two mechanisms (i.e., the deferred allocation mechanism and the swapping mechanism) are usually part of the PF exception handling. When memory is "allocated" (memory allocation is performed through mmap or malloc), in fact, the processor (specifically the OS) only creates a part of the VA space for the calling program. Physical memory pages are not paired with these virtual memory pages until they are accessed, that is, the mapping relationship is established. Memory accesses within this newly created region will trigger a PF by the MMU, and then the OS exception handler will check and confirm whether this access is legal and allocate a physical page.

[0076] The following combines Figure 4 the schematic diagram of the program access process shown to briefly describe the memory access process. Please refer to Figure 4 , specifically including:

[0077] The CPU Core executes the access instruction in the program. The access instruction is used to indicate accessing the virtual space (which can also be called the virtual memory space, and this application does not make any limitations). Exemplarily, the CPU Core inputs the virtual address (which can also be called the virtual memory address, and this application does not make any limitations) to the MMU. The MMU performs address translation on the virtual address to query its corresponding physical address.

[0078] Specifically, the TLB looks up the corresponding page table entry in the TLB page table based on the virtual address. In one example, if the TLB hits, the MMU performs address translation based on the PPN to obtain the corresponding physical address.

[0079] For example, as Figure 5 shown, assume that on the left are four virtual pages of VPN0 to VPN3, and on the right are physical pages of PPN0 to 7. The mapping relationship between the virtual page and the physical page is as shown by the arrows, that is, VPN1 is mapped to PPN1, VPN2 is mapped to PPN2, and the TLB includes the page table entries corresponding to the above two mapping relationships. If the program accesses VPN1, the TLB traverses to the page table entry corresponding to VPN1 cached in the TLB and can obtain the corresponding physical page, that is, PPN1, based on the mapping relationship.

[0080] In another example, if there is a TLB miss, the MMU traverses the page table based on this virtual address. If the page table is hit, the MMU obtains the corresponding physical address, and the MMU updates the TLB, that is, inserts the page table entry of the virtual page into the TLB. If the page table is not hit, the Page Fault process is executed. The MMU triggers a page fault exception. Specifically, the MMU outputs an interrupt signal to the OS, and the execution context switches from the user mode to the kernel mode. It can also be understood as transferring the control in the CPU to the operating system. The OS detects the validity of this virtual address. If the virtual address is valid, the OS allocates a physical page for this virtual page from the available and idle physical pages. The OS updates the page table entry in the page table. The execution context switches back from the kernel mode to the user mode, and the processor re-executes the access instruction. The TLB is hit, and the corresponding access operation can be performed on the physical page corresponding to the virtual page.

[0081] For example, still referring to Figure 5 , the program requests access to VPN0, and both the TLB and the page table miss. The OS has a page fault interrupt. The OS detects the validity of VPN0. If it is determined that VPN0 is valid, the OS allocates PPN5 for it. The OS updates the page table, and the TLB is optionally updated synchronously. The updated page table includes the page table entry corresponding to VPN0, and this entry corresponds to the mapping relationship between VPN0 and PPN5, that is, VPN0 is mapped to PPN5. After the PF exception handler completes its work, the system switches back from the kernel mode to the user mode, and the program re-executes the access instruction. This mode change (from user mode to kernel mode and then back to user mode) requires storing (or pushing) some "states" of the program (such as local variables, hardware registers, program counter, etc.) onto the stack. The last few operations of the PF processing flow are to pop this state from the stack and put it back in its original position so that the fault instruction can continue to execute. In addition to the overhead of pushing and popping the stack, the context switch also causes pollution of architectural resources such as caches, TLBs, and branch predictors.

[0082] Exemplarily, there are two types of page faults in the system: 1. Major Page Fault, also known as Hard Page Fault, which means that the memory to be accessed is not in the virtual memory space nor in the physical memory space, and needs to be loaded from a slow device. The slow device refers to a state-abnormal end device (host or storage) in a Storage Area Network (SAN). The state abnormality is manifested as the inability of the end device (host or storage) to respond quickly and normally. 2. Minor Page Fault, also known as Soft Page Fault, which means that the memory to be accessed is not in the virtual memory space but in the physical memory space, and only the MMU needs to establish the mapping relationship between the physical page and the virtual page.

[0083] The method in the embodiment of the present application can be applied to the Minor Page Fault scenario, effectively avoiding the service interruption caused by PF during the program access process, improving the processing efficiency of the program, especially the user-plane program, and enhancing the user experience.

[0084] The technical solution in the embodiment of the present application is described in three parts. The first part is memory allocation, the second part is program access, and the third part is delayed processing. Among them, memory allocation is the allocation of virtual memory space. The operating system can allocate corresponding virtual pages for the program based on the program's requirements (which can also be understood as virtual memory space, virtual address, virtual memory address, etc., and the present application does not make a limitation). During the program access process, the program accesses the virtual address. During this process, if a page fault occurs, a corresponding temporary page is allocated for the virtual page (the concept of the temporary page will be described in detail below). In the embodiment of the present application, program access can be understood as including commands in the program for indicating access to the virtual address, or as the CPU running the program and executing the access commands in the program. Delayed processing is optionally, after a page fault occurs during the program access process and a temporary page is allocated, and when a predetermined condition is met, a data write-back operation is performed on the data of the temporary page. The following will describe each part in detail with reference to the corresponding flowchart of each part:

[0085] I. Memory Allocation

[0086] Figure 6 For the schematic diagram of the memory allocation process shown exemplarily, please refer to Figure 6 , specifically including but not limited to the following steps:

[0087] S601, the OS determines whether the virtual memory space is available.

[0088] Exemplarily, the program sends an operating system request, which includes the required memory space size (e.g., 4K, which can be set according to actual requirements and is not limited in this application), to request the operating system to allocate a corresponding memory space for the program.

[0089] Based on the program's request, the operating system detects whether the virtual memory space of the operating system is available, that is, whether there is enough remaining virtual memory space to allocate a virtual memory space of the corresponding size for the program.

[0090] In one example, if the virtual memory space is available, then S602 is executed.

[0091] In another example, if the virtual memory space is not available (which can also be understood as insufficient virtual memory space), the program is instructed that the virtual memory space is not available. Optionally, the program can prompt the user that the current memory space is not available.

[0092] S602, the OS allocates a corresponding virtual memory space according to the request.

[0093] Exemplarily, the OS allocates a virtual memory space large enough for the program in the virtual memory space according to the program's requirements.

[0094] In the standard C library, functions such as malloc and mmap are provided. The operating system can call the corresponding functions to complete memory allocation. Figure 7 For the memory allocation schematic diagram shown exemplarily, please refer to Figure 7 , after the process calls A = malloc(4K), the operating system pushes the pointer 4K towards the higher address to complete the memory allocation. Among them, this memory allocation is only for the virtual memory space of the operating system, and there is no physical page corresponding to this virtual memory space, that is, this virtual page is not mapped to a physical page. When the process (or program) first reads or writes this virtual memory, a page fault interrupt, that is, PF, will occur. In the embodiments of this application, the operating system allocates a corresponding physical page or a temporary page for this virtual page, that is, establishes a mapping relationship between the virtual page and the temporary page (or physical page), and the specific implementation method will be described in detail in the second part.

[0095] S603, the OS traverses the page table, establishes a page table entry, and sets AAV to 1.

[0096] Exemplarily, after the OS allocates the virtual memory space, the OS updates the page table (including the Page Table, or a partial page table of the PageTable and the TLB cache) to establish a corresponding PTE for the virtual page.

[0097] In the embodiments of the present application, the PTE includes an Automatic Assignment Valid (AAV) flag bit (1 bit), which can also be referred to as assignable information, used to identify whether the corresponding virtual page can be assigned a staging page, as shown in Table 1:

[0098] Table 1

[0099]

[0100] Please refer to Table 1. The PTE is shown as the solid line part in Table 1. The dotted line part is the corresponding VPN. The MMU can use the VPN as an index to traverse the page table to find the corresponding PTE. The PPN is the page number of the physical page corresponding to the virtual page (the concept can be referred to Figure 1 ).

[0101] The PPN is used to identify the memory page mapped by the virtual page. In the embodiments of the present application, the memory page includes a staging page or a physical page, which will not be repeated hereinafter. Of course, in other embodiments, the memory page may also refer to a virtual page and a physical page, which is not limited in the present application. In this example, as described above, during the virtual memory space allocation process, the OS does not allocate the corresponding physical page for it. Correspondingly, the content corresponding to the PPN is empty or other meaningless data (which can be set according to actual needs and is not limited in the present application). After the first access to allocate the memory page for it, the PPN is updated accordingly.

[0102] Present (available) is used to identify whether the corresponding virtual page has been allocated a memory page (a staging page or a physical page). Similarly, since the memory page is not allocated currently, Present is empty or other values (which can be set according to actual needs and is not limited in the present application). In the embodiments of the present application, the unallocated memory page is marked as "0", and the allocated memory page is marked as "1". The values are only for illustrative purposes and are not limited in the present application.

[0103] Writable is used to identify whether the corresponding virtual page is writable. In the embodiments of the present application, the types of virtual pages include "writable" and "read-only" (which can also be understood as "not writable"). Among them, the "writable" type virtual page can be read and written, and the "read-only" type virtual page can only be read and cannot be written. In the embodiments of the present application, "writable" is marked as "1", and "read-only" is marked as "0". The values are only for illustrative purposes and are not limited in the present application. The Writable flag can be set according to user needs (the specific setting method can refer to the embodiments of the prior art and will not be elaborated in the present application), or it can be set to the default value. The default value in the embodiments of the present application is 1, that is, each virtual page is "writable" when initially created.

[0104] AAV is used to identify whether the corresponding virtual page can be allocated a scratch page. In the embodiments of the present application, the computer device may be configured with a scratch page allocation function option, and the user can select to enable or disable the function of automatically allocating scratch pages through this option. In one example, when the computer device determines to enable the automatic scratch page allocation function in response to the received user setting, the AAVs in the PTEs of the newly created virtual pages are all marked as "available", that is, scratch pages can be automatically allocated. In another example, when the computer device determines to disable the automatic scratch page allocation function in response to the received user setting, the AAVs in the PTEs of the newly created virtual pages are all marked as "unavailable", that is, scratch pages cannot be automatically allocated. After this function is disabled, the computer device allocates physical pages according to the existing process, and the specific process will be described below. In the embodiments of the present application, the scratch page that can be automatically allocated is marked as "1", and the scratch page that cannot be automatically allocated is marked as "0" or other values. The values are only for illustrative purposes and are not limited in the present application.

[0105] It should be noted that in the present application, the contents of each register are only represented in the form of a table, and this form is only for illustrative purposes and is not limited in the present application.

[0106] II. Program Access

[0107] Figure 8 For the schematic diagram of the access process shown by way of example, please refer to Figure 8 , which specifically includes but is not limited to the following steps:

[0108] S801, query whether the virtual page is mapped to a physical page.

[0109] Exemplarily, as Figure 4 shown, the MMU receives an access instruction sent by the program, and the access instruction is used to indicate accessing the corresponding virtual page. The access instruction includes a virtual address, and the virtual address includes but is not limited to: the page number and offset of the virtual page, etc.

[0110] Based on the virtual address, the MMU traverses the page table cached in the TLB. In one example, if the TLB hits, the MMU performs address conversion on the virtual address based on the PPN in the page table entry to obtain the corresponding physical address. The hardware (such as a cache controller or a memory controller) can access the memory corresponding to the physical address.

[0111] In another example, if the TLB misses, the MMU further performs PTW based on the virtual address, that is, traverses the page table. If the page table hits, the MMU performs address conversion on the virtual address based on the PPN in the page table entry to obtain the corresponding physical address, and the MMU updates the TLB. The hardware (such as a memory controller) can access the memory corresponding to the physical address. If the page table misses, then S802 is executed.

[0112] S802, allocate a scratch page for the virtual page.

[0113] Exemplarily, when the MMU determines that the virtual page is not mapped to a physical page, that is, when both the page table and the TLB miss, the MMU allocates a scratch page for the virtual page.

[0114] The scratch page in the embodiments of the present application will be described in detail below:

[0115] In the embodiments of the present application, the page size has been pre-configured in the processor architecture (configured by the operator before leaving the factory). Optionally, the size of the physical page is the same as that of the scratch page, for example, both are 4KB, which can be set according to actual needs and is not limited in the present application.

[0116] Figure 9 For the schematic diagram of the memory page division shown exemplarily, please refer to Figure 9 , the processor divides the physical space (a part of the physical space) into a normal space and a scratch space according to the page size. The sizes of the normal space and the scratch space are both configured by the operator before leaving the factory, and corresponding parameters are pre-configured in the processor architecture. Among them, the normal space includes physical memory. In the embodiments of the present application, the physical memory can be simply referred to as memory, and the memory is optionally a dynamic random access memory (DRAM). The processor divides the physical memory into multiple pages according to the pre-set page size, that is, physical pages.

[0117] Exemplarily, the processor divides the scratchpad space into multiple scratchpad pages, simply referred to as scratchpad pages. In the embodiments of the present application, the scratchpad pages are not mapped to the memory. It can be understood that physical pages are mapped to the memory, and the processor stores the mapping relationship between physical pages and the memory. Reading and writing of physical pages are the reading and writing of the corresponding physical memory of the physical pages. Optionally, in some instances, to accelerate the access speed, when a program reads and writes data of a physical page, usually, the cache allocates a corresponding cache space for the physical page. Taking data writing as an example, the cache allocates a corresponding cache space for the physical page, and the processor writes the data into the cache. Then, the hardware writes the data in the cache back to the physical memory corresponding to the physical page. There is a cache mechanism in the cache. If some data in the cache is not accessed within a certain period of time, the cache will clear this part of the data in the cache space. It can be understood that the corresponding relationship between the cache and the physical page is established temporarily. After the data is written back or after the data is not accessed for a certain period of time, the cache will clear the data, and the corresponding relationship no longer holds. The mapping relationship between the physical page and the physical memory is usually fixed. A unit or module (including hardware and software) can access the corresponding physical memory based on the mapping relationship between the physical page and the physical memory to read and write data. For the scratchpad pages, the scratchpad pages are not mapped to the physical memory, that is, the scratchpad pages do not have corresponding memory spaces, and the data of the scratchpad pages can only be stored in the corresponding cache.

[0118] In the embodiments of the present application, the processor configures a corresponding management register (TemporaryPage Management Register, TPMR) for each scratchpad page, as shown in Table 2:

[0119] Table 2

[0120]

[0121]

[0122] Please refer to Table 2. The Temporary PPN (Temporary Physical Page Number, simply referred to as scratchpad page number) is the page number of the scratchpad page. Its definition is similar to that of the physical page number, that is, the scratchpad pages corresponding to the scratchpad addresses (which can also be called scratchpad addresses) are numbered in sequence, called scratchpad page numbers.

[0123] Details are not described here again. The Temporary PPN can be used as the index of the TPMR of each scratchpad page, and a unit or module can find the corresponding register based on the Temporary PPN.

[0124] Exemplarily, the ASID (Address Space ID) is the virtual address, which can also be called the virtual address ID.

[0125] VPN stands for virtual page number, which is used to indicate the virtual page corresponding to the staging page.

[0126] Used can be referred to as usage information, which is used to indicate whether the staging page is available, or it can be understood as whether the staging page can be allocated. In the embodiments of the present application, the allocable flag is "0", and the non-allocable flag is "1", which can be set according to actual needs, and the present application does not make any limitations.

[0127] Flush to PPN (Flush Physical Page Number) can be referred to as physical memory page allocation information, which is used to indicate the physical page allocated for the staging page. In the latency processing stage of the third part, the system writes back (or writes) the data in the cache space corresponding to the staging page to the memory corresponding to the physical page identified by Flush to PPN.

[0128] In a possible implementation, if it is a multi-core CPU, the TPMR of the staging page needs to be uniformly managed across all CPUs to avoid the VPN of the same process being allocated to different staging pages.

[0129] In another possible implementation, other modules or units (such as the OS) can access the TPMR, and the access includes reading or modifying.

[0130] In yet another possible implementation, the information not filled in the register can be empty or a meaningless value, which can be set according to actual needs, and the present application does not make any limitations. In the embodiments of the present application, it is taken as an example that the data filled in is empty. For example, as shown in Table 2, in the current scenario, the ASID, VPN, and Flush to PPN of each staging page are all empty, and the Used is all 0.

[0131] In the embodiments of the present application, the MMU can traverse the TPMR corresponding to each staging page, and select a staging page from the available (i.e., the Used flag is "0") staging pages and allocate it to the virtual page. The traversal order of the MMU can be set according to actual needs, and the present application does not make any limitations. Correspondingly, the MMU updates the TPMR of the staging page, and updates the PTE (including the page table and TLB) corresponding to the virtual page. The specific update method will be illustrated by examples below.

[0132] S803, perform a corresponding access operation on the cache space corresponding to the staging page.

[0133] Exemplarily, the CPU re-executes the access instruction. The MMU responds to the access instruction and traverses the TLB based on the virtual address. Since in S802, the MMU has allocated a corresponding staging page for the virtual page and updated the page table, correspondingly, the MMU can find the corresponding staging page in the TLB based on the virtual address.

[0134] The MMU can perform address translation on the virtual address to obtain a temporary address. The hardware can access the cache space corresponding to the temporary address. Exemplarily, the correspondence between the virtual address and the temporary address is similar to the mapping relationship between the virtual address and the physical address (i.e., the physical address corresponding to the physical page), and reference can be made to the relevant content in Figure 1 above, which will not be elaborated here. The processor can access the cache space corresponding to the temporary physical page.

[0135] Specifically, the cache space corresponding to the temporary page is allocated by the cache (such as the cache controller) for the temporary page. The cache will allocate the corresponding cache space for the temporary page. Taking data writing as an example, the cache allocates the corresponding cache space for the temporary page, and the cache controller writes the data into the cache.

[0136] In the embodiments of the present application, the cache can allocate the corresponding cache space for the temporary page, that is, the Cache Line. Optionally, a 4KB temporary page can correspond to 64 Cache Lines. Correspondingly, the hardware can find the corresponding Cache Line based on the temporary address.

[0137] In a possible implementation manner, if the amount of data written does not fill the entire temporary page, when writing to the cache, only the number of Cache Lines corresponding to the amount of data is occupied. For example, assume that the written data can occupy 4 CacheLines, then the cache space only includes the first 4 Cache Lines, and the addresses corresponding to the pages without written data do not occupy the cache space. In the embodiments of the present application, what is in the cache is called Cache Line, and what is not in the cache is called XX address. For specific descriptions, reference can be made to Figure 13 .

[0138] As described above, the cache sets a cache mechanism, and data that has not been accessed for a certain period of time will be cleared. In the embodiments of the present application, to ensure that the data in the cache corresponding to the temporary page is not cleared before data write-back (i.e., written back from the cache to the memory corresponding to the physical page), the processor in the embodiments of the present application sets a Do Not Evict (DNE) flag for each Cache Line, which can also be called a retention flag, to identify that the data in the Cache line cannot be removed. That is to say, if the DNE flag is "retained", after the data in the Cache line reaches a certain duration, the CPU will still retain the cache data based on this flag. In the embodiments of the present application, the DNE flag of "1" indicates "retained", and the DNE flag of "0" indicates "not retained", which can be set according to actual needs, and the present application does not make any limitations. Table 3 shows the exemplary structure of the Cache Line:

[0139] Table 3

[0140]

[0141]

[0142] Please refer to Table 3, with the Tag as the index. In the embodiments of the present application, the index can be a temporary address or a physical address. The cache controller can find the corresponding Cache Line based on the index. If multiple Cache Lines can be found for an index address, these multiple Cache Lines form a Set.

[0143] The Data part is used to store data and can also be referred to as cached data.

[0144] The Valid flag (which can also be simply referred to as V) is used to indicate whether the data in the Cache Line is valid data. In the embodiments of the present application, a Valid flag of "1" indicates valid data, and a Valid flag of "0" indicates invalid data. Optionally, if the Valid flag is "0", that is, the data is invalid, the cache controller can recycle the Cache Line, that is, clear the data in the Cache Line or overwrite it with new data. In the embodiments of the present application, if the DNE flag is "1", that is, it is marked as reserved, and the Valid flag is "0", that is, the data is invalid, the cache controller also recycles the Cache Line. That is to say, after the hardware writes the data in the Cache Line corresponding to the temporary page back to the memory, the operating system updates the Valid of the Cache Line to "0", and the DNE of the Cache Line can remain "1" or be updated to "0" (i.e., not reserved), and the cache controller will recycle the Cache Line in both cases.

[0145] Exemplarily, program access can include but is not limited to: writing a page (or writing data) and reading a page (or reading data), etc. The scenarios of writing data and reading data are described below respectively:

[0146] 1) Writing scenario

[0147] Figure 10 For the schematic diagram of the data writing process shown exemplarily, please refer to 10, which specifically includes but is not limited to the following steps:

[0148] S1001, query the TLB.

[0149] Exemplarily, the processor executes a write instruction of the program, and the write instruction is used to indicate the execution of a write operation. The write instruction includes but is not limited to: a virtual address and data.

[0150] Exemplarily, based on the virtual address, the MMU traverses the page table cached in the TLB.

[0151] In one example, if there is a TLB hit, that is, the page table in the TLB includes the page table entry for this virtual address, S1011 is executed.

[0152] In another example, if there is a TLB miss, that is, the page table in the TLB does not include the page table entry for this virtual address, S1002 is executed.

[0153] S1002, traverse the page table.

[0154] Exemplarily, the MMU further traverses the page table based on this virtual address to query the page table entry corresponding to this virtual address.

[0155] S1003, query PTE Present.

[0156] In the embodiments of the present application, each virtual page allocated by the OS corresponds to an AAV. Optionally, if the queried virtual address is not in the page table, that is, the corresponding AAV is not queried, the MMU can determine that the virtual address accessed by the program is an "invalid" (which can also be called non-compliant) virtual address, and the MMU feeds back a virtual address exception indication to the program.

[0157] As described above, in the prior art embodiments, the MMU will execute the Page Fault process when there is a page table miss (including the cases where the virtual address does not exist or the physical page is not allocated). The program is interrupted, and the execution context is switched from the user mode to the kernel mode. When the OS executes the Page Fault process, it performs compliance (or invalidity) detection on the virtual page to determine whether the virtual address is invalid. In the embodiments of the present application, based on the AAV in the register corresponding to the page table, the MMU can determine whether the corresponding virtual address is invalid, without the OS executing a page fault exception interrupt, which can reduce the system processing complexity and feedback the exception in a timely manner.

[0158] When the MMU determines that the virtual address is valid, the MMU queries the Present of the PTE, which can refer to Table 1.

[0159] In one example, if Present is "0" (or empty, or other meaningless value), which is used to indicate that the virtual page is not mapped to a physical page and no corresponding scratch page is allocated (in the embodiments of the present application, Present will be updated to 1 after the scratch page is allocated, and the specific implementation can be referred to below), S1004 is executed. Optionally, in the embodiments of the present application, "mapping" means having a stable mapping relationship, such as between a virtual page and a physical page, or between a physical page and memory. "Corresponding" in the embodiments of the present application means having a certain corresponding relationship, but this corresponding relationship is not stable and will be released when needed. For example, the corresponding relationship between a virtual page and a scratch page, and the corresponding relationship between a scratch page and a cache. The corresponding relationship between the virtual page and the scratch page is optionally released after the OS allocates a physical page for the virtual page, and the corresponding relationship between the scratch page and the cache is optionally released after the hardware writes back the data in the cache to memory, which will not be repeated below.

[0160] In another example, if Present is "1", which is used to indicate that the virtual page has been mapped to a physical page or a corresponding scratch page has been allocated, that is, the page table is hit, the MMU performs address translation on the virtual page to obtain the corresponding physical address or scratch address, and S1015 is executed.

[0161] S1004, query whether it is writable.

[0162] Exemplarily, the MMU determines whether the virtual page is writable based on Writable in the page table entry.

[0163] In one example, if Writable is "0", which is used to indicate that the virtual page is not writable (or can be understood as read-only), S1021 is executed.

[0164] In another example, if Writable is "1", which is used to indicate that the virtual page is writable, S1005 is executed.

[0165] S1005, query AAV.

[0166] Exemplarily, the MMU determines whether a scratch page can be allocated for the virtual page based on the AAV of the page table entry.

[0167] In one example, if AAV is "1", which is used to indicate that a scratch page can be allocated for the virtual page, S1006 is executed.

[0168] In another example, if AAV is "0" (or empty, or other meaningless value), which is used to indicate that a scratch page cannot be allocated for the virtual page, S1021 is executed.

[0169] S1006, determine whether there is an available scratch page.

[0170] Exemplarily, when the MMU determines that a scratch page can be allocated for a virtual page, it detects whether the scratch page is available. As described above, in the computer device, there is a TPMR corresponding to each scratch page, and the TPMR includes a Used flag for indicating whether the scratch page is available. The MMU can traverse the TPMRs of each scratch page to determine whether there is a scratch page with a Used flag of "0". Here, a Used flag of "0" indicates that the scratch page is available.

[0171] In one example, if there is no available scratch page, for example, all existing scratch pages have been allocated to the corresponding virtual pages, that is, the Used flags of all scratch pages are "1", then S1021 is executed.

[0172] In another example, if there is an available scratch page, S1007 is executed.

[0173] S1007, allocate a scratch page.

[0174] Exemplarily, when the MMU determines that there is an available scratch page, it selects a scratch page from the available scratch pages and allocates it to the virtual page. Optionally, the selection of the scratch page can be random or the first scratch page with a Used flag of "0" can be selected in the traversal order, which can be set according to actual requirements and is not limited in this application.

[0175] Exemplarily, after the MMU allocates a scratch page for the virtual page, it updates the TPMR corresponding to the scratch page. As shown in Table 2, the MMU updates the ASID, VPN, and Used of the TPMR of this scratch page (i.e., the scratch page allocated to the virtual page). Among them, the ASID and VPN are updated according to the virtual address, and the Used is updated to "1" to indicate that this scratch page is unavailable (it can also be understood as occupied, invalid, etc., which is not limited in this application). The specific update method will be illustrated in the following embodiments.

[0176] S1008, update the PPN in the PTE, clear the AAV, and set the Writable to "1".

[0177] Exemplarily, after the MMU allocates a scratch page for a virtual page, it updates the PTE corresponding to the virtual page in the page table. Specifically, referring to Table 1, the MMU updates the PPN in the PTE of the virtual page to the PPN of the scratch page (which can be referred to as the scratch page number in the embodiments of the present application). The MMU updates Present to "1" to indicate that a memory page has been allocated for the virtual page, and in this example, the allocated memory page is the scratch page. Also, the MMU sets Writable to "1" to indicate that the virtual page is a writable page. Among them, the value of Writable may originally be "1", and in this example, there is no need to update Writable. And, the MMU clears the value in AAV. Optionally, the MMU can also set AAV to "0" to indicate that the virtual page cannot be allocated a scratch page. That is to say, after a virtual page has been allocated a scratch page, no more scratch pages will be allocated for this virtual page.

[0178] S1009, Insert into TLB.

[0179] Exemplarily, the MMU inserts the new PTE into the TLB. The memory page indicated by the PPN in the new PTE can be a physical page or a scratch page. For example, after executing S1022, S1009 is executed, and the page indicated by the PPN in the page table entry inserted into the TLB is a physical page. After executing S1008, S1009 is executed, and the page indicated by the PPN in the page table entry inserted into the TLB is a scratch page.

[0180] S1010, The processor re-executes the write instruction.

[0181] In this example, Figure 10 the process in advances to S1001. Since the MMU has allocated a scratch page for the virtual page, the MMU queries the TLB and determines that the TLB hits. The MMU performs address translation on the virtual address based on the PPN in the TLB (which may be the page number of the scratch page or the page number of the physical page) to obtain the physical address, and continues to execute S1011. It should be noted that for the MMU, the converted address is considered to be a physical address, and in fact, it can be the physical address corresponding to the physical page or the scratch address corresponding to the scratch page.

[0182] S1011, Query whether it is writable.

[0183] In the case of TLB hit, the MMU queries whether the virtual page is writable based on the page table entry. This process can refer to the relevant description of S1004 and will not be elaborated here.

[0184] In one example, if the virtual page is writable, then S1012 is executed.

[0185] In another example, if the virtual page is not writable, S1016 is executed.

[0186] S1012, Whether the PPN is a temporary page.

[0187] In the embodiments of the present application, the processor can configure a physical page list and a temporary page list (which can also be in other forms, not limited in the present application). The temporary page list is used to record information such as the page number and temporary address of the temporary page. If the temporary page is removed, the temporary page in the list can be deleted. Similarly for the physical page list, details are not elaborated here.

[0188] In a possible implementation, if the processor in the computer device is a single-core processor, the cache controller can access the temporary page list to determine whether the memory page corresponding to the virtual page is a temporary page.

[0189] In another possible implementation, if the processor of the computer device is a multi-core processor, multiple processors correspond to multiple caches. The computer device includes a cache proxy. The cache proxy accesses the temporary page list maintained (or stored) by the processor to determine whether the page indicated by the physical address after MMU conversion is a temporary page.

[0190] In one example, if the page is a temporary page, execute S1013.

[0191] In another example, if the page is a physical page, execute S1014.

[0192] S1013, Write the data into the cache corresponding to the temporary page, and the DNE flag of the Cache Line is 1.

[0193] Exemplarily, the cache controller allocates a corresponding cache space for the temporary page and writes the data into the cache space. Specifically, the cache controller allocates a corresponding CacheLine based on the temporary address (i.e., the physical address after MMU conversion as described above), and writes the data into the Data part of the Cache Line. The Cache Line structure can refer to Table 3.

[0194] Optionally, as described above, a 4K temporary page can correspond to 64 Cache Lines. Only the Cache Lines with data written are stored in the cache, and those without data written are called XX addresses, which can be called the nth 64B in the embodiments of the present application.

[0195] Exemplarily, the cache proxy described above can also be used to maintain (or store) the correspondence between physical pages or staging pages and the cache. For example, the cache proxy is provided with a cache correspondence table (taking a list as an example only, it can be in other forms, which is not limited in this application). The correspondence table includes the correspondence between each Cache Line in the cache and the physical address (including the physical address of the physical page and the staging address of the staging page), and is used to record the cache to which the Cache Line belongs. The cache controller can retrieve the cache correspondence table based on the physical address, for querying whether there is a corresponding Cache Line for this physical address and which cache the corresponding Cache Line belongs to.

[0196] In the embodiment of this application, after the cache controller allocates a cache for the staging page, the cache proxy updates the cache correspondence table to save the correspondence between the staging address and the Cache Line.

[0197] S1014, Write data to the cache or memory.

[0198] Exemplarily, if the page to be written is a physical page, the hardware writes the data to the cache or the memory corresponding to the physical page. Optionally, as described above, if the data is written to the cache, under certain conditions (the condition settings of the hardware, which can be set according to actual needs), the hardware writes the data to the memory corresponding to the physical page. It should be noted that although the data of the physical page can be written to the cache first and then to the memory, different from the staging page, the physical page will cause an OS interruption during the PageFaulte process. After the interruption, that is, after the physical page is allocated, the data can be written to the cache allocated by the cache for the physical page.

[0199] Similarly, in a multi-core scenario, if the data is written to the cache, the cache proxy updates the cache correspondence table to save the correspondence between the physical address and the Cache Line.

[0200] S1015, Query whether it is writable.

[0201] Exemplarily, in the case of a page table hit, the MMU queries whether the virtual page is writable. The specific implementation method can refer to the relevant content of S1004, which will not be elaborated here.

[0202] In one example, if the virtual page is writable, then execute S1009.

[0203] In another example, if the virtual page is not writable, execute S1016.

[0204] S1016, Query AAV.

[0205] Exemplarily, in the case where a virtual page corresponds to a memory page and the virtual page is non-pageable (i.e., read-only page), in the embodiments of the present application, a writable scratch page will be allocated for the virtual page to write data into the cache space corresponding to the scratch page, without causing an OS interruption (OS interruption to cause the OS to allocate a physical page for the virtual page).

[0206] The implementation manner of this step can refer to S1005, which will not be elaborated here.

[0207] In one example, if the AAV flag is "1", then S1021 is executed.

[0208] In another example, if the AAV flag is "0", then S1017 is executed.

[0209] S1017, determine whether there is an available scratch page.

[0210] The specific implementation manner can refer to the relevant content of S1006, which will not be elaborated here.

[0211] S1018, allocate a scratch page.

[0212] The specific implementation manner can refer to the relevant content of S1007, which will not be elaborated here.

[0213] S1019, flush the TLB.

[0214] Exemplarily, in this example, there is a page table entry of the virtual page in the TLB. After the MMU reallocates a memory page (i.e., a scratch page) for the virtual page, the MMU removes the page table entry corresponding to the virtual page in the TLB. When S1009 is executed, a new page table entry will be reinserted.

[0215] S1020, copy the non-zero data of the old page.

[0216] In some examples, there may be non-zero data in the memory page (which may be a physical page or a scratch page) corresponding to the virtual page before. The non-zero data of the physical page may be in the cache or in the memory. The non-zero data of the scratch page is in the cache. Correspondingly, the cache controller can copy the non-zero data from the cache, or the memory controller can copy the non-zero data from the memory. It can be understood that this step is to copy the non-zero data in the old memory page to migrate the data to the cache space corresponding to the new scratch page.

[0217] S1021, normal Page Fault.

[0218] Exemplarily, in the embodiments of the present application, if a virtual page has no allocated memory page and the virtual page is non-writable; or, the virtual page has no allocated memory page, the virtual page is writable but does not allow the allocation of a scratch page (i.e., the AAV flag is "0"); or, the virtual page has already been allocated a memory page, the virtual page is non-writable and does not allow the allocation of a scratch page (i.e., the AAV is 0); or, a scratch page needs to be allocated for the virtual page but the scratch space is insufficient (i.e., all scratch pages are unavailable), in any of the above cases, the normal Page Fault process is executed, that is, the MMU outputs an interrupt instruction to the OS. The execution context is switched from the user mode to the kernel mode, and the OS allocates a physical page for the virtual page. The relevant process can refer to Figure 4 the description in, which will not be elaborated here.

[0219] S1022, update the PTE.

[0220] Exemplarily, the OS updates the PTE based on the physical page allocated for the virtual page. Specifically, the OS updates the PPN of the virtual page to the PPN of this physical page.

[0221] 2) Read data

[0222] Figure 11 For the schematic diagram of the read data process shown exemplarily, please refer to 11, which specifically includes but is not limited to the following steps:

[0223] S1101, query the TLB.

[0224] Exemplarily, the processor executes the read instruction of the program, and the read instruction is used to indicate the execution of a read operation. The read instruction includes but is not limited to: a virtual address.

[0225] Exemplarily, the MMU traverses the page table cached in the TLB based on the virtual address.

[0226] In one example, if the TLB hits, that is, the page table in the TLB includes the page table entry of this virtual address, execute S1111.

[0227] In another example, if the TLB misses, that is, the page table in the TLB does not include the page table entry of this virtual address, execute S1102.

[0228] S1102, traverse the page table.

[0229] Exemplarily, the MMU further traverses the page table based on this virtual address to query the page table entry corresponding to this virtual address.

[0230] S1103, query PTE Present.

[0231] In the embodiments of the present application, each virtual page allocated by the OS corresponds to an AAV. Optionally, if the queried virtual address is not in the page table, that is, the corresponding AAV is not queried, the MMU can determine that the virtual address accessed by the program is an "invalid" (also referred to as non-compliant) virtual address, and the MMU feeds back a virtual address exception indication to the program.

[0232] As described above, in the prior art embodiments, the MMU executes the Page Fault process when the page table misses (including the cases where the virtual address does not exist or the physical page is not allocated). The program is interrupted, and the execution context is switched from the user mode to the kernel mode. When the OS executes the Page Fault process, it performs compliance (or invalidity) detection on the virtual page to determine whether the virtual address is invalid. In the embodiments of the present application, based on the AAV in the register corresponding to the page table, the MMU can determine whether the corresponding virtual address is invalid, without the OS executing a page fault exception interrupt, which can reduce the system processing complexity and feedback the exception in a timely manner.

[0233] When the MMU determines that the virtual address is valid, the MMU queries the Present of the PTE, and Table 1 can be referred to.

[0234] In one example, if the Present is "0" (or empty, or other meaningless values), which is used to indicate that the virtual page is not mapped to the physical page and the corresponding scratch page is not allocated (in the embodiments of the present application, the Present will be updated to 1 after the scratch page is allocated, and the specific implementation can be referred to below), S1104 is executed.

[0235] In another example, if the Present is "1", which is used to indicate that the virtual page is mapped to the physical page or the corresponding scratch page is allocated, that is, the page table hits, the MMU performs address conversion on the virtual page to obtain the corresponding physical address or scratch address, and S1105 is executed.

[0236] S1104, query the AAV.

[0237] Exemplarily, in this example, the AAV can also be used to indicate whether a specified physical page can be allocated. In the embodiments of the present application, the specified physical page is the zero page, that is, the physical page with all data being 0. In other embodiments, it can also be other specified physical pages, such as the page with all data being "1", which is not limited in the present application.

[0238] The MMU determines whether the virtual page can allocate the specified physical page based on the AAV of the page table entry.

[0239] In one example, if the AAV is "1", which is used to indicate that the virtual page can allocate the specified physical page, S1106 is executed.

[0240] In another example, if the AAV is "0" (or empty, or other meaningless value) to indicate that the virtual page cannot be assigned a specified physical page, S1107 is executed.

[0241] S1105, insert the TLB.

[0242] Exemplarily, the MMU inserts the new PTE into the TLB. The memory page indicated by the PPN in the new PTE can be a physical page or a scratch page. For example, after executing S1107, S1105 is executed, and the page indicated by the PPN in the page table entry inserted into the TLB is a physical page. After executing S1108, S1105 is executed, and the page indicated by the PPN in the page table entry inserted into the TLB is a scratch page. After executing S1103 and then S1105, the page indicated by the PPN in the page table entry inserted into the TLB may be a scratch page or a physical page.

[0243] S1106, query whether it is writable.

[0244] Exemplarily, the MMU determines whether the virtual page is writable based on the Writable in the page table entry.

[0245] In one example, if the Writable is "0" to indicate that the virtual page is not writable (or can be understood as read-only), S1109 is executed.

[0246] In another example, if the Writable is "1" to indicate that the virtual page is writable, S1108 is executed.

[0247] S1107, normal Page Fault.

[0248] The normal Page Fault process can refer to Figure 4 , which will not be elaborated here. After the Page Fault process is executed, that is, after the OS assigns the corresponding physical page to the virtual page, the OS updates the page table and executes S1105, that is, inserts the new PTE into the TLB.

[0249] S1108, allocate a zero page, update the PTE, and set the Writable to "0".

[0250] The processor is pre-configured with a zero page, which is a physical page and the data in the page is all 0.

[0251] In the embodiments of the present application, in the read scenario, if a memory page needs to be assigned to the virtual page, the memory page assigned by the MMU to the virtual page is the specified page. In the embodiments of the present application, the specified page is taken as the zero page, that is, the data in the page is all 0 as an example for illustration. In other embodiments, it can also be other specified pages. For example, the data in the page can be all "1", which is not limited in the present application.

[0252] In the embodiments of the present application, if there is another program executing Figure 11 the read process in, when the MMU executes S1008, it will allocate a zero page for it.

[0253] S1109, clear the AAV.

[0254] Exemplarily, the MMU clears the AAV corresponding to the virtual page, for example, sets the AAV to "0" or clears it, to indicate that the virtual page cannot allocate a scratch page or specify a physical page. That is to say, if the virtual address is accessed again, the AAV of the virtual address is marked as "0".

[0255] S1110, the processor re-executes the read instruction.

[0256] In this example, Figure 11 the process in advances to S1101. Since the MMU has allocated a zero page for the virtual page, the MMU queries the TLB and determines that the TLB hits. The MMU performs address translation on the virtual address to obtain a physical address or a scratch address, and executes S1111.

[0257] S1111, determine whether the PPN is a scratch page.

[0258] Exemplarily, for the specific description, reference can be made to the relevant description of S1012, which will not be elaborated here.

[0259] S1112, obtain data from the cache or memory.

[0260] Exemplarily, in the scenario of a single-core processor, the cache controller parses the physical address to find the corresponding Cache Line. For example, the cache controller takes the middle 8 bits of the physical address (for example, bits [5, 12]) to find which Cache Line group the physical address belongs to. Optionally, the cache can include 256 groups. After the group is determined, the cache controller compares the bits [13, 31] in the physical address with the 256 Cache Lines in the group. If the bits [13, 31] are the same as the Tag field in the Cache Line, and the Valid field of the Cache Line is marked as "1", indicating that the Cache Line is valid, then it is determined that the cache hits. The cache controller reads data from the hit Cache Line. If the cache misses, the memory controller can obtain the corresponding data in the memory based on the physical page address.

[0261] In another example, in a multi-core processor scenario, the cache agent can traverse the cache correspondence table based on the physical address to determine whether the physical address corresponds to a Cache Line and which cache the Cache Line belongs to. If it is found that the physical address corresponds to a Cache Line and the corresponding cache is located, the cache controller can search for the corresponding Cache Line from the corresponding cache based on the physical address and obtain the data. The search method can refer to the single-core scenario and will not be elaborated here. If it is found that the physical address does not correspond to a Cache Line, the memory controller can obtain the corresponding data from the memory based on the physical page address.

[0262] S1113, Query the cache.

[0263] In one example, in a single-core processor scenario, the cache controller resolves the physical address to search for the corresponding Cache Line. For example, the cache controller takes the middle 8 bits of the physical address (e.g., bits [5, 12]) to search for which Cache Line group the physical address belongs to. Optionally, the cache can include 256 groups. After the group is determined, the cache controller compares the bits [13, 31] in the physical address with the 256 Cache Lines in the group. If the bits [13, 31] are the same as the Tag field in the Cache Line and the Valid field of the Cache Line is marked as "1" to indicate that the Cache Line is valid, it is determined that the cache hit occurs and S1115 is executed. If the cache miss occurs, S1114 is executed.

[0264] In another example, in a multi-core processor scenario, the cache agent can traverse the cache correspondence table based on the physical address to determine whether the physical address corresponds to a Cache Line and which cache the Cache Line belongs to. If it is found that the physical address corresponds to a Cache Line and the corresponding cache is located, then S1115 is executed. The search method can refer to the single-core scenario and will not be elaborated here. If it is found that the physical address does not correspond to a Cache Line, then S1114 is executed.

[0265] For the case where the cache may miss, as described above, only the Cache Lines with non-zero data will be cached in the cache. Correspondingly, in some instances, if the data in the Cache Line corresponding to the staging page is all 0, there will be no Cache Line data corresponding to the staging page in the cache.

[0266] S1114, Feedback all-zero data.

[0267] Exemplarily, if there is no data corresponding to the staging page in the cache, the cache controller feeds back all-zero data.

[0268] S1115, Obtain data from the cache.

[0269] Exemplarily, as Figure 10 shown in the process, the data of the staging page will be written into one or more Cache Lines corresponding to the staging page. The cache controller can obtain data from the corresponding Cache Line based on the staging address. The specific obtaining method can refer to the description in S1112 and will not be elaborated here.

[0270] III. Delayed Processing

[0271] Figure 12 For the schematic diagram of the delayed processing flow shown exemplarily, please refer to Figure 12 , which specifically includes but is not limited to the following steps:

[0272] S1201, Detect that the preset condition is satisfied.

[0273] Exemplarily, the processor sets a preset condition, and the preset condition is used to indicate the execution of the delayed processing flow. In the embodiments of the present application, the preset condition includes but is not limited to at least one of the following: the CPU load is less than the first threshold (which can also be understood as the CPU is idle), the number of available staging pages is less than the second threshold, and the timer timing ends (which can also be understood as there is an execution period set).

[0274] When the processor detects that the preset condition is satisfied, it executes the delayed processing flow. In the embodiments of the present application, through the preset condition, the computer device can execute the OS interrupt when the preset condition is satisfied to execute the delayed processing flow. In this way, during program access, the program can be not interrupted, but when conditions such as the CPU is idle, the page fault exceptions of one or more virtual pages can be uniformly processed, that is, physical page allocation and data writing are performed according to the PF processing logic in the existing embodiments.

[0275] S1202, Search for the used staging pages.

[0276] Exemplarily, when the processor detects that the preset condition is satisfied, it sends an interrupt to the OS, and all programs currently running on the processor (which may be background programs, or of course, there may be no programs running) are interrupted. The OS traverses the TPMR of each staging page to search for the used staging pages, that is, the staging pages with Used being "0".

[0277] S1203, Allocate physical pages.

[0278] Exemplarily, the OS allocates physical pages for the used staging pages. The specific allocation method is similar to the Page Fault process and will not be elaborated here.

[0279] Flush to PPN in the TPMR of the OS update scratch page, and update this parameter to the PPN of the physical page.

[0280] Optionally, as described above, the processor maintains (or stores) a list of scratch pages, and the processor may also maintain (or store) a list of physical pages. The list may include tracking information for indicating the usage of physical pages. If a physical page is frequently used, the count value in the tracking information is large, and the physical page is counted each time it is used. If the count value in the tracking information is less than a preset threshold (which can be set according to actual requirements and is not limited in this application), that is, the physical page is accessed less frequently, the memory controller may migrate the data in the memory of this physical page to an auxiliary storage such as a hard disk.

[0281] S1204, write the data in the cache to the memory of the physical page.

[0282] Exemplarily, the OS updates the Used in the TPMR of the scratch page that has been allocated a physical page to "0" to indicate that the scratch page is available.

[0283] When the processor detects that the Used flag of any scratch page changes from "1" to "0", the CPU controls the cache controller to extract the data in the cache space corresponding to this scratch page, and the memory controller can write the data to the memory of the corresponding physical page based on the Flush to PPN in the TPMR of the scratch page. In the embodiment of this application, there is a certain time delay between the OS updating the Used to "0" and the data being migrated to the memory of the physical page. During this time period, since the current execution context is the kernel mode, in the case of kernel mode execution, all programs are in an interrupted state and will not execute new user-mode access instructions, and thus will not execute the behavior of allocating scratch pages. Therefore, the situation where the data of the scratch page with Used updated to "0" has not been successfully written back and is allocated to other virtual pages will not occur.

[0284] S1205, update the PTE.

[0285] Exemplarily, the OS updates the page table, or the PTE of the virtual page in the page table and TLB. Update the PPN in the PTE of the scratch page corresponding to the scratch page that has been written back to the PPN of the physical page allocated in S1203.

[0286] The following uses a specific example to Figure 10 、 Figure 11 and Figure 12 in the solution are described in detail.

[0287] Scenario 1:

[0288] In this scenario, take the example of a program writing to a virtual page and then reading it. Take the ASDI of the program as 0x2. In this scenario, the program requires 2KB of memory space. The OS allocates a virtual page with a base address (i.e., VPN) of 0x1000 for it according to the process in Figure 8 The OS configures the PTE of this virtual page as shown in Table 4:

[0289] Table 4

[0290]

[0291] Please refer to Table 4. Among them, the Present flag of the virtual address 0x1000 is "0" (in hexadecimal in the table, which will not be repeated in the following text), indicating that the virtual page has no allocated memory page. The Writable flag is "1", indicating that the virtual page is writable. The AAV flag is "1", indicating that a scratch page can be allocated.

[0292] Please refer to Figure 10 , and the processor executes the write instruction of the program to perform a write operation on the virtual page. The write instruction includes, but is not limited to, the virtual address 0x1000 (xxx) and data. Among them, the content in the parentheses is the offset.

[0293] The process advances to S1001, and the MMU queries the TLB based on the VPN (0x1000). In this example, the MMU does not find the corresponding page table entry, that is, TLB Miss.

[0294] The process advances to S1002, and the MMU further queries the page table based on the VPN and reads the corresponding PTE, such as Table 4.

[0295] The process advances to S1003, and the MMU queries the Present flag. In this example, the MMU queries that the Present flag is "0", indicating that the virtual page has no allocated memory page.

[0296] The process advances to S1004, and the MMU queries whether the virtual page is writable. In this example, the MMU queries that the Writable flag in the PTE is "1", indicating that the virtual page is writable.

[0297] The process advances to S1005, and the MMU queries the AAV. In this example, the MMU queries that the AAV flag is "1", indicating that the virtual page can be allocated a scratch page.

[0298] The process advances to S1006, and the MMU queries whether there is an available scratch page, as shown in Table 5:

[0299] Table 5

[0300]

[0301] Please refer to Table 5. The MMU traverses each TPMR, queries for the scratch pages with the Used flag being "0", and determines that there are available scratch pages.

[0302] The process proceeds to S1007, where the MMU allocates a scratch page. In this example, the MMU allocates the scratch page 0x8000 to the virtual page 0x1000. The MMU updates the TPMR of the scratch page 0x8000 as shown in Table 6:

[0303] Table 6

[0304]

[0305] Please refer to Table 6. The MMU updates the TPMR of the scratch page 0x8000, sets the ASID to "0x2", and sets the VPN to "0x1000" to indicate that the scratch page 0x8000 is allocated to 0x1000. The MMU sets the Used flag to "1" to indicate that the scratch page 0x8000 is unavailable.

[0306] The process proceeds to S1008, where the MMU updates the PPN in the PTE, clears the AAV, and sets the Writable flag to 1. In this example, the updated PTE is shown in Table 7:

[0307] Table 7

[0308]

[0309] Please refer to Table 7. The MMU updates the PPN to the page number corresponding to the scratch page, which is 0x8000. The MMU updates the Present flag to "1" to indicate that the corresponding memory page has been allocated for the virtual page 0x1000. The MMU updates the AAV flag to "0" to indicate that the virtual page cannot be allocated a scratch page. Among them, the Writable flag being "1" does not need to be updated.

[0310] The process proceeds to S1009, where the MMU inserts the PTE into the TLB. In this example, the MMU inserts the PTE in Table 6 into the TLB.

[0311] The process proceeds to S1010, and the processor re-executes the write instruction.

[0312] The process proceeds to S1001, where the MMU queries the TLB. In this example, the MMU traverses the TLB based on the VPN of the virtual page: 0x1000. As shown in Table 7, the MMU queries the corresponding page table entry. The MMU performs address translation on the virtual address 0x1000(xxx) based on the PPN to obtain the corresponding scratch address 0x8000(xxx). The conversion method can be referred to Figure 3 , which will not be elaborated here.

[0313] The process proceeds to S1011, where the MMU queries whether the virtual page is writable. As shown in Table 7, in this example, the MMU queries that the Writable flag in the PTE is "1", indicating that the virtual page is writable.

[0314] The process proceeds to S1012, where the cache controller module queries whether the PPN is a scratch page. Exemplarily, as described above, the processor is configured with a scratch page list that includes information such as the VPNs of all scratch pages. Taking a single-core CPU as an example, the cache controller can traverse the scratch page list based on the PPN (0x8000) in the PTE to query whether the memory page is a scratch page. In this example, the cache proxy module determines that the memory page indicated by the PPN is a scratch page.

[0315] The process proceeds to S1013, where the cache controller writes the data to the cache space corresponding to the scratch page. Specifically, the cache controller allocates a Cache Line for the scratch page based on the scratch address after MMU translation. The cache controller writes non-zero data into the corresponding Cache Line. For example, as Figure 13 shown, each scratch address corresponds to a 64B space, and scratch page 0x8000 corresponds to n 64B spaces. Among them, the data written to scratch page 0x8000 occupies the 1st 64B to the 3rd 64B, that is, it occupies Cache Line 1 to Cache Line 3 (Cache Lines can be continuous or discontinuous, which is not limited in this application). Correspondingly, Cache Line 1 to Cache Line 3 are in the cache, and other scratch addresses (such as the 4th 64B to the 64th 64B) are not in the cache. The Cache Lines are shown in Table 8:

[0316] Table 8

[0317]

[0318] Please refer to Table 7. The cache controller sets the Valid flag to "1" to indicate that the data in this Cache Line is valid data. The cache controller sets the DNE flag to "1" to indicate retaining the data in the Cache Line. For example, when the cache controller queries that the data in multiple Cache Lines (including the Cache Lines in Table 7) has not been accessed for a long time, the cache controller clears the Cache Lines with the DNE flag set to "0" and / or the Valid flag set to "0" (to indicate that the Cache Line is invalid). The Cache Lines with the DNE flag set to "1" and the Valid flag set to "1" are retained.

[0319] In this example, it is assumed that the processor executes a read instruction of a program to perform a read operation on a virtual page. The read instruction includes, but is not limited to, a virtual address.

[0320] Please refer to Figure 11 , the process advances to S1101, and the MMU queries the TLB. In this example, in the write scenario, the TLB has been updated. Correspondingly, based on the virtual address 0x1000(xxx), the MMU traverses the TLB (as shown in Table 7) and finds the corresponding page table entry. The MMU performs address translation based on the PPN (0x8000) in the PTE to obtain a temporary address (for the MMU, it considers this to be a physical address).

[0321] The process advances to S1111, and the cache controller determines whether the PPN is a temporary page. In this example, taking a single-core CPU as an example, the cache controller can determine that the page of the physical address 0x8000(xxx) is a temporary page based on the temporary page list.

[0322] The process advances to S1113, and the cache controller queries the cache based on the temporary address. In the above embodiment, data is written into the corresponding part of the Cache Line of the temporary page. Correspondingly, in this step, taking a single-core CPU as an example, the cache controller can search for the corresponding Cache Line in the cache based on the temporary address.

[0323] The process advances to S1115, and the cache controller obtains data from at least one Cache Line corresponding to the temporary page (0x8000).

[0324] Based on the scenario in the above embodiment, an example of the Figure 12 delay processing flow will be given below. Please refer to Figure 12 , the process advances to S1201. In this scenario, the processor detects that a preset condition is met, for example, the CPU load is less than the first threshold. The processor sends an interrupt to the OS to indicate that the OS executes the delay processing flow. All programs running on the processor (which can include user programs or background programs (i.e., programs that the user is not aware of)) are interrupted, and the execution context switches from the user mode to the kernel mode.

[0325] The process advances to S1202, and the OS searches for used temporary pages. Specifically, the OS traverses the TPMR of each temporary page to find a temporary page with the Used flag marked as "0". As shown in Table 6, by traversing the TPMR, the OS finds that the Used of temporary page N, temporary page N + 1, temporary page N + 2, and temporary page 0x8000 are all marked as "0".

[0326] The process proceeds to S1203, where the OS allocates physical pages. Specifically, the OS allocates physical pages for the used scratch pages. In one possible implementation, the OS can traverse all TPMRs, find all the used scratch pages, and allocate physical pages for each used scratch page. Then, it proceeds to execute S1204. In another possible implementation, the OS can also find a used scratch page, execute S1203 and S1204, and repeat the execution of S1202 - S1204 until the traversal is complete (i.e., all TPMRs have been traversed). For example, in this instance, when the OS traverses the scratch page 0x8000 and the Used flag is "0", it determines that the scratch page 0x8000 has been used and no physical page has been allocated (i.e., Flush to PPN is empty). The OS selects a physical page from the available physical pages (the selection method can refer to the existing embodiments, which will not be elaborated in this application), for example, physical page 0x2000. The OS allocates physical page 0x2000 to scratch page 0x8000.

[0327] Exemplarily, the OS updates the TPMR of scratch page 0x8000 as shown in Table 9:

[0328] Table 9

[0329]

[0330] Please refer to Table 9. Based on Table 6, the OS updates the Flush to PPN in the TPMR of 0x8000 to the PPN of the physical page, which is 0x2000. Also, the OS updates the Used flag to "0" to indicate that the scratch page is available.

[0331] The process proceeds to S1204, where the hardware writes the data in the cache to the memory of the physical page. Specifically, when the processor detects that the Used flag of scratch page 0x8000 is updated from "1" to "0", it instructs the cache controller to extract the data in the Cache Line corresponding to scratch page 0x8000. For example, the Data part of the Cache Line in Table 8. The cache controller updates the Valid of the Cache Line and sets the Valid flag to "0" to indicate that the data in the Cache Line is invalid data. Optionally, the cache controller updates the DNE flag to "0" to indicate that the data in the Cache Line is not retained, as shown in Table 10:

[0332] Table 10

[0333]

[0334] The cache controller can, according to the preset rules of the cache controller, under certain conditions, clear the Cache Lines with the Valid flag set to "0".

[0335] After the cache controller extracts the data, the memory controller writes the data to the memory corresponding to 0x2000 based on the Flush to PPN of the TPMR at 0x8000.

[0336] The process advances to S1205, and the OS updates the PTE. Specifically, based on Table 7, the OS updates the PTE of virtual page 0x1000, and the updated PTE is shown in Table 11:

[0337] Table 11

[0338]

[0339] Please refer to Table 11. The OS updates the PPN to the PPN of the physical page, which is 0x2000, to indicate that virtual page 0x1000 is mapped to physical page 0x2000. The Present flag is not updated and remains "1", indicating that the memory page has been allocated. The Writable flag is not updated and remains "1", indicating that virtual page 0x1000 is a writable page. The OS updates the AAV flag to "1" to indicate that a scratch page can be allocated for the virtual page.

[0340] Scenario 2:

[0341] In this scenario, an example is given where the program reads a virtual page and then writes to it. Take the ASDI of the program as 0x3. In this scenario, the program requires 1KB of memory space. The OS allocates a virtual page with a base address (i.e., VPN) of 0x2000 for it according to the Figure 8 process in. The OS configures the PTE of this virtual page as shown in Table 12:

[0342] Table 12

[0343]

[0344] Please refer to Table 12. Among them, the Present flag of virtual address 0x2000 is "0", indicating that the virtual page has no allocated memory page. The Writable flag is "1", indicating that the virtual page is writable. The AAV flag is "1", indicating that a scratch page can be allocated.

[0345] Please refer to Figure 11 , and the processor executes the read instruction of the program to perform a write operation on the virtual page. The write instruction includes, but is not limited to, virtual address 0x1000(xxx) and data. The content in the parentheses is the offset.

[0346] The process advances to S1101, and the MMU queries the TLB. The MMU queries the TLB based on the VPN (0x2000). In this example, the MMU does not find the corresponding page table entry, that is, TLB Miss.

[0347] The process proceeds to S1102, where the MMU further queries the page table based on the VPN, reads the corresponding PTE, such as Table 12.

[0348] The process proceeds to S1103, where the MMU queries the Present flag. In this example, the MMU queries that the Present flag is "0", indicating that the virtual page does not have an allocated memory page.

[0349] The process proceeds to S1104, where the MMU queries the AAV. In this example, the MMU queries that the AAV flag is "1", indicating that the virtual page can be allocated a scratch page or a specified physical page. In this instance, the specified physical page is the zero page, i.e., the physical page with all data being 0.

[0350] The process proceeds to S1105, where the MMU queries whether the virtual page is writable. In this example, the MMU queries that the Writable flag in the PTE is "1", indicating that the virtual page is writable.

[0351] The process proceeds to S1106, where the MMU allocates the zero page and updates the PTE, setting the Writable flag to "0". Specifically, the MMU allocates the zero page for virtual page 0x2000 and updates the PTE. The updated PTE is shown in Table 13:

[0352] Table 13

[0353]

[0354] Please refer to Table 13. The MMU updates the PPN to the PPN of the zero page, which is 0x0. The MMU updates the Present flag to "1", indicating that a memory page has been allocated. The MMU sets the Writable flag to "0", indicating that virtual page 0x2000 is not writable, i.e., it is a read-only page. Among them, the AAV flag remains "1", indicating that a scratch page can be allocated.

[0355] The process proceeds to S1105, where the MMU inserts the TLB. In this example, the MMU inserts the PTE in Table 13 into the TLB.

[0356] The process proceeds to S1110, where the processor re-executes the read instruction.

[0357] The process proceeds to S1101, where the MMU queries the TLB. In this example, the MMU traverses the TLB based on the VPN of the virtual page: 0x2000. As shown in Table 13, the MMU queries the corresponding page table entry. The MMU performs address translation on the virtual address 0x2000(xxx) based on the PPN to obtain the corresponding physical address 0x000(xxx). The conversion method can be referred to Figure 3 , which will not be elaborated here.

[0358] The process proceeds to S1111, and the cache controller determines whether the PPN is a scratch page. In this example, the cache controller can determine, based on the scratch page list, that the page at physical address 0x000(xxx) is not a scratch page.

[0359] The process proceeds to S1112, and the memory controller retrieves data from memory. Specifically, the memory controller can find the corresponding data (i.e., all-zero data) in memory based on the physical page address (0x0000(xxx)) and read the data.

[0360] In this example, it is assumed that the processor executes a write instruction of a program to perform a write operation on the virtual page (0x2000). The read instruction includes, but is not limited to, the virtual address and data.

[0361] Please refer to Figure 10 , the process proceeds to S1001, and the MMU queries the TLB. In this example, in the write scenario, the TLB has been updated. Correspondingly, the MMU traverses the TLB (as shown in Table 13) based on the virtual address 0x2000(xxx) and finds the corresponding page table entry. The MMU performs address translation based on the PPN (0x0000) in the PTE to obtain the physical address.

[0362] The process proceeds to S1011, and the MMU queries whether the virtual page is writable. As shown in Table 13, in this example, the MMU queries that the Writable flag in the PTE is "0", indicating that the virtual page is not writable, i.e., it is a read-only page.

[0363] The process proceeds to S1016, and the MMU queries the AAV. In this example, the MMU queries that the AAV flag is "1", indicating that the virtual page can be allocated a scratch page.

[0364] The process proceeds to S1017, and the MMU queries whether there is an available scratch page, as shown in Table 14:

[0365] Table 14

[0366]

[0367]

[0368] Please refer to Table 14. The MMU traverses each TPMR and finds a scratch page with the Used flag being "0", determining that there is an available scratch page.

[0369] The process proceeds to S1018, and the MMU allocates a scratch page. In this example, the MMU allocates the scratch page 0x9000 to the virtual page 0x2000. The MMU updates the TPMR of the scratch page 0x9000, as shown in Table 15:

[0370] Table 15

[0371]

[0372] Please refer to Table 15. The MMU updates the TPMR of the scratch page 0x9000, sets the ASID to "0x3", and sets the VPN to "0x2000" to indicate that the scratch page 0x9000 is allocated to 0x2000. The MMU sets Used to "1" to indicate that the scratch page 0x9000 is unavailable.

[0373] The process advances to S1019, and the MMU flushes the TLB. In this example, there is a page table entry for the virtual page (0x2000) in the TLB. After the MMU reallocates a memory page (i.e., a scratch page) for the virtual page (0x2000), the MMU removes the page table entry corresponding to this virtual page (0x2000) from the TLB.

[0374] The process advances to S1020. In this example, since the previously allocated physical page is a zero page and its data is all zero, correspondingly, in this step, the cache controller does not need to copy the data of the old page, and S1013 does not need to be executed either.

[0375] The process advances to S1008. The MMU updates the PPN in the PTE, clears the AAV, and sets Writable to 1. In this example, the updated PTE is shown in Table 16:

[0376] Table 16

[0377]

[0378] Please refer to Table 16. The MMU updates the PPN to the page number corresponding to the scratch page, which is 0x9000. The Present flag remains "1" to indicate that a corresponding memory page has been allocated for the virtual page 0x2000. The MMU updates the AAV flag to "0" to indicate that the virtual page cannot be allocated a scratch page. The MMU sets the Wtritable flag to "1" to indicate that the virtual page 0x2000 is a writable page.

[0379] The process advances to S1009, and the MMU inserts into the TLB. In this example, the MMU inserts the PTE in Table 16 into the TLB.

[0380] The process advances to S1010, and the processor re-executes the write instruction.

[0381] The process advances to S1001, where the MMU queries the TLB. In this example, the MMU traverses the TLB based on the VPN of the virtual page: 0x2000. As shown in Table 16, the MMU finds the corresponding page table entry. The MMU performs address translation on the virtual address 0x2000(xxx) based on the PPN, obtaining the corresponding cached address 0x9000(xxx). The conversion method can be referred to Figure 3 , which will not be elaborated here.

[0382] The process advances to S1011, where the MMU queries whether the virtual page is writable. As shown in Table 16, in this example, the MMU finds that the Writable flag in the PTE is "1", indicating that the virtual page is writable.

[0383] The process advances to S1012, where the cache controller queries whether the PPN is a cached page. The description can be referred to the above, which will not be elaborated here.

[0384] The process advances to S1013, where the cache controller writes data to the cache space corresponding to the cached page. Specifically, the cache controller allocates a Cache Line for the cached page based on the cached address after MMU conversion. The cache controller writes non-zero data into the corresponding Cache Line and sets the DNE of the Cache Line to 1. The description can be referred to the above, which will not be elaborated here.

[0385] The delay processing flow in this scenario can be referred to Scenario 1, and will not be repeated here.

[0386] The above mainly introduces the solution provided by the embodiments of the present application from the perspective of the interaction between each network element. It can be understood that in order to implement the above functions, the access device includes the corresponding hardware structure and / or software module for executing each function. Those skilled in the art should easily realize that, combining the units and algorithm steps of each example described in the embodiments disclosed in this article, the embodiments of the present application can be implemented in the form of hardware or a combination of hardware and computer software. Whether a certain function is executed in the way of hardware or computer software driving hardware depends on the specific application and design constraints of the technical solution. Professional technicians can use different methods to implement the described functions for each specific application, but such implementation should not be considered to exceed the scope of the present application.

[0387] The embodiments of the present application can divide the access device into functional modules according to the above method examples. For example, each functional module can be divided corresponding to each function, or two or more functions can be integrated into one processing module. The above integrated module can be implemented in the form of hardware or in the form of a software functional module. It should be noted that the division of modules in the embodiments of the present application is illustrative, only a logical function division, and there can be other division methods in actual implementation.

[0388] In the case of dividing each functional module corresponding to each function, in the case of dividing each functional module corresponding to each function, Figure 14 FIG. shows a possible structural schematic diagram of the access device 1400 involved in the above embodiment, as Figure 14 shown, the access device may include: an acquisition module 1401, a query module 1402, a first allocation module 1403, and an execution module 1404. The acquisition module 1401 is used to acquire an access instruction, and the access instruction is used to indicate accessing a target virtual memory page; the query module 1402 is used to query whether the target virtual memory page is mapped to a physical memory page in response to the access instruction; the first allocation module 1403 is used to allocate a target temporary page for the target virtual memory page when the target virtual memory page is not mapped to a physical memory page; the execution module 1404 is used to perform an access operation on the cache space corresponding to the target temporary page.

[0389] In a possible implementation manner, the processor stores usage information and physical memory page allocation information of each temporary page. The usage information is used to indicate whether the corresponding temporary page is available, and the physical memory page allocation information is used to indicate the physical memory page allocated for the corresponding temporary page.

[0390] In a possible implementation manner, the first allocation module 1403 is specifically used to: select a target temporary page from the temporary pages indicated by the usage information as available; allocate a target temporary page for the target virtual memory page; and update the usage information of the target temporary page to unavailable.

[0391] In a possible implementation manner, the access instruction is a write instruction, and the execution module 1404 is specifically used to: write data into the cache space corresponding to the target temporary page.

[0392] In a possible implementation manner, the device further includes: a second allocation module 1405, which is used to allocate a target physical memory page for the target temporary page when a preset condition is met; a first update module 1406, which is used to update the physical memory page allocation information of the target temporary page, and the updated physical memory page allocation information is used to indicate the target physical memory page allocated for the target temporary page; a second update module 1407, which is used to update the usage information of the target temporary page to available.

[0393] In a possible implementation, the apparatus further includes a data processing module 1408, configured to, upon detecting that the usage information of a target scratch page is updated to available, write the data in the cache space corresponding to the target scratch page into the memory corresponding to the target physical memory page based on the physical memory page allocation information of the target scratch page.

[0394] In a possible implementation, the preset condition includes at least one of the following: the load of the processor is less than a first threshold, the number of scratch pages whose usage information indicates unavailable exceeds a second threshold, and the timer timing ends.

[0395] In a possible implementation, the processor stores a retention flag corresponding to each cache line, and the retention flag is used to indicate whether to retain the data in the corresponding cache line; the apparatus further includes a third update module 1409, configured to update the retention flag corresponding to each cache line of the cache space to retained.

[0396] In a possible implementation, the processor stores a page table, and the page table includes allocable information of each virtual memory page, and the allocable information is used to indicate whether the corresponding virtual memory page can be allocated a scratch page.

[0397] In a possible implementation, the first allocation module 1402 is specifically configured to: query the allocable information of the target virtual memory page; when it is queried that the allocable information of the target virtual memory page indicates that the target virtual memory page can be allocated a scratch page, allocate a target scratch page for the target virtual memory page.

[0398] In another example, Figure 15 FIG. shows a schematic block diagram of an access apparatus 1500 according to an embodiment of the present application. The access apparatus may include a processor 1501 and a transceiver / transceiver pin 1502. Optionally, it further includes a memory 1503. The processor 1501 may be configured to execute the steps performed by the access apparatus in the various methods of the foregoing embodiments, and control the receive pin to receive a signal and control the transmit pin to transmit a signal.

[0399] The various components of the access apparatus 1500 are coupled together through a bus 1504. The bus system 1504 includes, in addition to a data bus, a power bus, a control bus, and a status signal bus. However, for clarity of illustration, all the buses are labeled as the bus system 1504 in the figure.

[0400] Optionally, the memory 1503 may be used to store instructions in the foregoing method embodiments.

[0401] It should be understood that the access device 1500 according to the embodiments of the present application may correspond to the computer device in each of the methods of the foregoing embodiments, and the above and other management operations and / or functions of each element in the access device 1500 respectively implement the corresponding steps of the foregoing respective methods. For the sake of brevity, they will not be elaborated herein.

[0402] Among them, all relevant contents of the steps involved in the above method embodiments can be cited in the function descriptions of the corresponding function modules, and will not be elaborated herein.

[0403] Based on the same technical concept, the embodiments of the present application further provide a computer-readable storage medium. The computer-readable storage medium stores a computer program, and the computer program includes at least one segment of code. The at least one segment of code can be executed by a computer device to control the computer device to implement the above method embodiments.

[0404] Based on the same technical concept, the embodiments of the present application further provide a computer program. When the computer program is executed by a computer device, it is used to implement the above method embodiments.

[0405] The program can be stored in whole or in part on a storage medium packaged together with the processor, or can be stored in whole or in part on a memory not packaged together with the processor.

[0406] Based on the same technical concept, the embodiments of the present application further provide a processor, and the processor is used to implement the above method embodiments. The above processor can be a chip.

[0407] The steps of the method or algorithm described in combination with the disclosed content of the embodiments of the present application can be implemented in a hardware manner, or can be implemented by a processor executing software instructions. The software instructions can be composed of corresponding software modules. The software modules can be stored in a random access memory (Random Access Memory, RAM), flash memory, read-only memory (Read Only Memory, ROM), erasable programmable read-only memory (Erasable Programmable ROM, EPROM), electrically erasable programmable read-only memory (Electrically EPROM, EEPROM), register, hard disk, removable hard disk, compact disc read-only memory (CD-ROM) or any other form of storage medium well known in the art. An exemplary storage medium is coupled to the processor so that the processor can read information from the storage medium and write information to the storage medium. Of course, the storage medium can also be a component of the processor. The processor and the storage medium can be located in an ASIC.

[0408] Those skilled in the art should be able to realize that in one or more of the above examples, the functions described in the embodiments of the present application can be implemented by hardware, software, firmware, or any combination thereof. When implemented using software, these functions can be stored in a computer-readable medium or transmitted as one or more instructions or codes on a computer-readable medium. The computer-readable medium includes computer storage media and communication media, where the communication media includes any medium that facilitates the transfer of a computer program from one place to another. The storage media can be any available medium accessible by a general-purpose or special-purpose computer.

[0409] The embodiments of the present application have been described above in conjunction with the accompanying drawings. However, the present application is not limited to the above specific embodiments. The above specific embodiments are merely illustrative and not restrictive. Under the inspiration of the present application, those of ordinary skill in the art can also make many forms without departing from the purpose of the present application and the scope protected by the claims, and all of them fall within the protection scope of the present application.

Claims

1. An access method, characterized in that, Applied to a computer device, the computer device includes a processor and a memory, and the computer device further includes at least one physical memory page and at least one scratch page. Each of the physical memory pages is mapped to the memory. The method includes: Obtain an access instruction, where the access instruction is used to indicate accessing a target virtual memory page; In response to the access instruction, query whether the target virtual memory page is mapped to a physical memory page; In the case where the target virtual memory page is not mapped to a physical memory page, allocate a target scratch page for the target virtual memory page; Perform an access operation on the cache space corresponding to the target scratch page.

2. The method according to claim 1, wherein The processor stores usage information of each of the scratch pages and physical memory page allocation information. The usage information is used to indicate whether the corresponding scratch page is available, and the physical memory page allocation information is used to indicate the physical memory page allocated for the corresponding scratch page.

3. The method according to claim 2, wherein The allocating a target scratch page for the target virtual memory page includes: Select the target scratch page from the scratch pages indicated as available by the usage information; Allocate the target scratch page for the target virtual memory page; Update the usage information of the target scratch page to unavailable.

4. The method according to claim 3, characterized in that The access instruction is a write instruction. The performing a corresponding access operation on the cache space corresponding to the target scratch page includes: Write data into the cache space corresponding to the target scratch page.

5. The method according to claim 4, wherein After performing the corresponding access operation on the cache space corresponding to the target scratch page, it further includes: Under a preset condition, allocate a target physical memory page for the target scratch page; Update the physical memory page allocation information of the target scratch page. The updated physical memory page allocation information is used to indicate the target physical memory page allocated for the target scratch page; Update the usage information of the target scratch page to available.

6. The method according to claim 5, characterized in that, After performing the corresponding access operation on the cache space corresponding to the target scratch page, it further includes: Detect that the usage information of the target scratch page is updated to available. Based on the physical memory page allocation information of the target scratch page, write the data in the cache space corresponding to the target scratch page into the memory corresponding to the target physical memory page.

7. The method according to claim 5, wherein The preset condition includes at least one of the following: The load of the processor is less than a first threshold, the number of scratch pages indicated as unavailable by the usage information exceeds a second threshold, and the timer timing ends.

8. The method according to claim 4, characterized in that, The processor stores a reservation flag corresponding to each cache line. The reservation flag is used to indicate whether to reserve the data in the corresponding cache line. After writing the data into the cache space corresponding to the target scratch page, it further includes: Update the reservation flag corresponding to each cache line of the cache space to reserved.

9. The method according to any one of claims 1 to 8, characterized in that, The processor stores a page table, and the page table includes allocatable information of each virtual memory page. The allocatable information is used to indicate whether the corresponding virtual memory page can be allocated a scratch page.

10. The method according to claim 9, wherein The allocating a target scratch page for the target virtual memory page includes: Query the allocatable information of the target virtual memory page; When it is queried that the allocable information of the target virtual memory page indicates that the target virtual memory page can allocate a scratch page, allocate the target scratch page for the target virtual memory page.

11. An access device, characterized in that, Applied to a computer device, the computer device includes a processor and a memory, and the computer device further includes at least one physical memory page and at least one scratch page. Each physical memory page is mapped to the memory. The device includes: An acquisition module, configured to acquire an access instruction, where the access instruction is used to indicate accessing a target virtual memory page; A query module, configured to query whether the target virtual memory page is mapped to a physical memory page in response to the access instruction; A first allocation module, configured to allocate a target scratch page for the target virtual memory page when the target virtual memory page is not mapped to a physical memory page; An execution module, configured to perform an access operation on a cache space corresponding to the target scratch page.

12. The device according to claim 11, characterized in that, The processor stores usage information of each scratch page and physical memory page allocation information. The usage information is used to indicate whether the corresponding scratch page is available, and the physical memory page allocation information is used to indicate the physical memory page allocated for the corresponding scratch page.

13. The device according to claim 12, characterized in that, The first allocation module is specifically configured to: Select the target scratch page from the scratch pages indicated as available by the usage information; Allocate the target scratch page for the target virtual memory page; Update the usage information of the target scratch page to unavailable.

14. The device according to claim 13, characterized in that When the access instruction is a write instruction, the execution module is specifically configured to: Write data into a cache space corresponding to the target scratch page.

15. The device according to claim 14, characterized in that, The device further includes: A second allocation module, configured to allocate a target physical memory page for the target scratch page when a preset condition is satisfied; A first update module, configured to update the physical memory page allocation information of the target scratch page, and the updated physical memory page allocation information is used to indicate that the target physical memory page allocated for the target scratch page; A second update module, configured to update the usage information of the target scratch page to available.

16. The device according to claim 15, characterized in that, The device further includes: A data processing module, configured to detect that the usage information of the target scratch page is updated to available, and based on the physical memory page allocation information of the target scratch page, write data in a cache space corresponding to the target scratch page into a memory corresponding to the target physical memory page.

17. The device according to claim 15, characterized in that, The preset condition includes at least one of the following: The load of the processor is less than a first threshold, the number of scratch pages indicated as unavailable by the usage information exceeds a second threshold, and the timer timing ends.

18. The device according to claim 14, wherein The processor stores a reservation flag corresponding to each cache line, and the reservation flag is used to indicate whether to reserve data in the corresponding cache line; the device further includes: A third update module, configured to update the reservation flag corresponding to each cache line of the cache space to reserved.

19. The device according to any one of claims 11 to 18, characterized in that, The processor stores a page table, and the page table includes allocable information of each virtual memory page, and the allocable information is used to indicate whether the corresponding virtual memory page can allocate a scratch page.

20. The device according to claim 19, characterized in that, The first allocation module is specifically configured to: Query the allocable information of the target virtual memory page; The allocatable information of the target virtual memory page is queried to indicate that the target virtual memory page can allocate a scratch page, and the target scratch page is allocated for the target virtual memory page.

21. A computer cluster, characterized in that, The computer cluster includes at least one computer device, and the computer device is configured to execute the method according to any one of claims 1 to 10.

22. A computer storage medium, characterized in that, It includes computer instructions that, when the computer instructions run on a computer device, cause the computer device to execute the method according to any one of claims 1-10.

23. A computer program product, characterized in that, When the computer program product runs on a computer device, it causes the computer device to execute the method according to any one of claims 1-10.

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