Chip power consumption measuring system and method

Abstract

The invention provides a chip power consumption measurement system and method.The chip power consumption measurement system comprises a test board, a power consumption collection module and a control module, the control module sends task instructions to a chip to be tested, and the task instructions comprise any one or more of a voltage instruction, a frequency instruction and an operation core instruction; when the chip to be tested executes a task instruction, the power consumption acquisition module acquires voltage information of each test resistor and transmits the voltage information to the control module; the control module determines the test power consumption of the to-be-tested chip according to the voltage information. According to the technical scheme, the task instruction can be sent to the to-be-tested chip, any one or more of the working frequency, the working voltage and the number of the running cores of the to-be-tested chip can be changed, different use scenes can be simulated, power consumption measurement of the to-be-tested chip can be completed in different scenes, and the test power consumption of the to-be-tested chip can be accurately and rapidly obtained.

Description

Technical Field

[0001] The present invention relates to the field of chips, and in particular, to a chip power consumption measurement system and method. Background Art

[0002] During the backend testing of chips and the process of delivering them to customers, it is necessary to measure the overall power consumption of the chips and the corresponding circuits, and it is also necessary to comprehensively evaluate the heat dissipation solutions / chip configurations, etc.

[0003] Currently, the main method for measuring chip power consumption is mainly through a power consumption acquisition instrument. By measuring the voltage and current at the current detection resistor end and feeding back the corresponding power consumption, and then manually adjusting the chip configuration to achieve the load and power consumption verification of different chip configurations on the test board and the evaluation of the corresponding solutions.

[0004] For chip factories with a large customer base and diverse requirements, it is necessary to consider the measurement and evaluation of different chip configurations and the corresponding power consumption of each path. It is necessary to manually replace the chips with corresponding configurations and set the frequency and voltage before collecting power consumption, which is relatively labor-intensive and time-consuming. Summary of the Invention

[0005] The purpose of the present invention is to provide a chip power consumption measurement system and method to improve the above problems.

[0006] To achieve the above purpose, the technical solutions adopted in the embodiments of the present invention are as follows: In a first aspect, an embodiment of the present invention provides a chip power consumption measurement system. The chip power consumption measurement system includes a test board, a power consumption acquisition module, and a control module. The test board is deployed with a communication unit and N test links, and each test link includes a test resistor and a test load; One end of the i-th test link is used to connect to the i-th power supply rail of the chip under test, and the other end of the i-th test link is grounded, where 1 ≤ i ≤ N; The (2i - 1)-th detection end of the power consumption acquisition module is connected to one end of the test resistor of the i-th test link, and the 2i-th detection end of the power consumption acquisition module is connected to the other end of the test resistor of the i-th test link; The control module is connected to the communication unit and the power consumption acquisition module, and the communication unit is also connected to the chip under test; The control module is used to send task instructions to the chip under test. The task instructions include any one or more of a voltage instruction, a frequency instruction, and a running core instruction. The voltage instruction includes the target voltage corresponding to each power supply rail. The frequency instruction includes the target operating frequency of the cores in the chip under test. The running core instruction includes the number of running cores; The power consumption acquisition module is used to collect the voltage information of each test resistor when the chip under test executes the task instruction, and transmit the voltage information to the control module; The control module is used to determine the test power consumption of the chip under test according to the voltage information.

[0007] Optionally, the chip under test is equipped with a power management unit and a startup unit; The startup unit is used to execute the running core instruction and start the cores in the chip under test according to the number of running cores; The power management unit is used to execute the voltage instruction to adjust the supply voltage of each power rail to the corresponding target voltage; The power management unit is also used to execute the frequency instruction to make the cores in the chip under test run at the target operating frequency.

[0008] Optionally, the communication unit includes a first UART communication interface, a second UART communication interface, and an interface selector; One end of the first UART communication interface is connected to the power management unit, and the other end of the first UART communication interface is connected to the first downlink port of the interface selector; One end of the second UART communication interface is connected to the startup unit, and the other end of the second UART communication interface is connected to the second downlink port of the interface selector; The uplink port of the interface selector is connected to the control module; The interface selector is used to switch the conduction relationship between its internal downlink port and uplink port according to an instruction or a preset rule.

[0009] Optionally, the chip under test is also equipped with a temperature detection unit, and the temperature detection unit is connected to one or more temperature sensors deployed on the chip under test; The communication unit also includes a third UART communication interface. One end of the third UART communication interface is connected to the temperature detection unit, and the other end of the third UART communication interface is connected to the third downlink port of the interface selector; The temperature detection unit is used to collect the temperature data monitored by each temperature sensor and transmit the temperature data to the control module.

[0010] Optionally, the control module includes a first control unit and a second control unit, and the second control unit includes a first MCU; The first MCU is respectively connected to the power consumption acquisition module and the first control unit; The first MCU is configured to forward the voltage information of each test resistor transmitted by the power consumption acquisition module to the first control unit; The first control unit is configured to determine the test power consumption of the chip under test according to the voltage information.

[0011] Optionally, the second control unit further includes a second MCU; The second MCU is respectively connected to the upstream port of the interface selector and the first control unit; The second MCU is configured to perform protocol conversion on the task instruction issued by the first control unit and transmit the converted instruction to the interface selector; The second MCU is further configured to perform protocol conversion on the temperature data uploaded by the interface selector and transmit the converted temperature data to the first control unit; The first control unit is configured to evaluate the heat dissipation state in combination with the temperature data.

[0012] Optionally, the test load is an adjustable load, and the first control unit is further connected to the adjustable load; The first control unit is configured to send a load adjustment instruction to the test load to change the equivalent resistance of the test load.

[0013] Optionally, the first control unit is configured to determine the test power consumption of the chip under test according to the voltage information and the resistance value of the test resistor.

[0014] Optionally, the power consumption acquisition module includes one or more power consumption acquisition chips.

[0015] In a second aspect, an embodiment of the present invention provides a method for measuring chip power consumption, which is applied to the above chip power consumption measurement system. The method includes: The control module sends a task instruction to the chip under test. The task instruction includes any one or more of a voltage instruction, a frequency instruction, and a running core instruction. The voltage instruction includes the target voltage corresponding to each power supply rail. The frequency instruction includes the target operating frequency of the core in the chip under test. The running core instruction includes the number of running cores; When the chip under test executes the task instruction, the power consumption acquisition module acquires the voltage information of each test resistor and transmits the voltage information to the control module; The control module determines the test power consumption of the chip under test according to the voltage information.

[0016] Compared with the prior art, a chip power consumption measurement system and method provided by an embodiment of the present invention. The chip power consumption measurement system includes a test board, a power consumption acquisition module, and a control module. The control module sends task instructions to the chip under test. The task instructions include any one or more of a voltage instruction, a frequency instruction, and a running core instruction. The voltage instruction includes the target voltage corresponding to each power supply rail. The frequency instruction includes the target operating frequency of the core in the chip under test. The running core instruction includes the number of running cores. When the chip under test executes the task instructions, the power consumption acquisition module collects the voltage information of each test resistor and transmits the voltage information to the control module. The control module determines the test power consumption of the chip under test according to the voltage information. By sending task instructions to the chip under test, any one or more of the operating frequency, operating voltage, and number of running cores of the chip under test can be changed, so as to simulate different usage scenarios. Under different scenarios, the power consumption measurement of the chip under test is completed, and the test power consumption of the chip under test can be accurately and quickly obtained.

[0017] In order to make the above objects, features, and advantages of the present invention more obvious and understandable, the following specifically enumerates preferred embodiments and, in conjunction with the accompanying drawings, makes a detailed description as follows. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following will briefly introduce the drawings required for the embodiments. It should be understood that the following drawings only show some embodiments of the present invention, and therefore should not be regarded as limiting the scope. For those of ordinary skill in the art, without creative efforts, other related drawings can also be obtained based on these drawings.

[0019] Figure 1 It is a schematic structural diagram of the chip power consumption measurement system provided by an embodiment of the present invention.

[0020] Figure 2 It is a schematic structural diagram of the chip under test provided by an embodiment of the present invention.

[0021] Figure 3 It is a schematic structural diagram of the control module provided by an embodiment of the present invention.

[0022] In the figure: 11 - test link; 12 - communication unit; 121 - first UART communication interface; 122 - second UART communication interface; 123 - third UART communication interface; 124 - interface selector; 13 - power consumption acquisition module; 14 - control module; 141 - first control unit; 142 - second control unit; 1421 - first MCU; 1422 - second MCU; 20 - chip under test; 201 - power management unit; 202 - startup unit; 203 - temperature detection unit. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0023] To make the objectives, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are some but not all of the embodiments of the present invention. Components of the embodiments of the present invention generally described and illustrated in the figures herein can be arranged and designed in a variety of different configurations.

[0024] Therefore, the detailed description of the embodiments of the present invention provided in the drawings below is not intended to limit the scope of the claimed invention, but merely represents selected embodiments of the present invention. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts fall within the scope of the present invention.

[0025] It should be noted that like reference numerals and letters denote like items in the following figures, and thus, once an item is defined in one figure, further definition and explanation thereof is not required in subsequent figures. At the same time, in the description of the present invention, terms such as "first", "second", etc. are only used for descriptive distinction and should not be construed as indicating or implying relative importance.

[0026] It should be noted that, in this document, relational terms such as "first" and "second" are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the terms "comprising", "including" or any other variation thereof are intended to cover non-exclusive inclusion, such that a process, method, article or device comprising a series of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article or device. Without further limitation, an element defined by the phrase "comprising a..." does not exclude the presence of additional identical elements in the process, method, article or device comprising the element.

[0027] In the description of the present invention, it should be noted that the orientation or positional relationship indicated by terms such as "upper", "lower", "inner", "outer", etc. is based on the orientation or positional relationship shown in the drawings or the orientation or positional relationship in which the inventive product is customarily placed during use. It is only for the convenience of describing the present invention and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus should not be construed as a limitation of the present invention.

[0028] In the description of the present invention, it should also be noted that unless otherwise clearly specified and defined, the terms "arrangement" and "connection" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be directly connected or indirectly connected through an intermediate medium, and it can be the communication inside two components. For those of ordinary skill in the art, the specific meanings of the above terms in the present invention can be understood according to specific situations.

[0029] The following will describe in detail some embodiments of the present invention with reference to the accompanying drawings. Without conflict, the following embodiments and the features in the embodiments can be combined with each other.

[0030] In order to quickly and accurately complete power consumption measurement, an embodiment of the present invention provides a chip power consumption measurement system, which can establish a communication mechanism with the chip to be measured, can control the power consumption measurement and feedback of the corresponding circuit, and can communicate with the chip power supply system control unit through the UART serial port to control the setting of chip configuration (voltage / frequency / degradation), so that the voltage and frequency adjustment can achieve the expected power consumption evaluation purpose. It can also collect power consumption data in different temperature environments in the incubator environment based on the remote control logic.

[0031] Specifically, please refer to Figure 1 , Figure 1 is a schematic structural diagram of the chip power consumption measurement system provided by an embodiment of the present invention. The chip power consumption measurement system includes a test board, a power consumption acquisition module 13, and a control module 14. The test board is deployed with a communication unit 12 and N test links 11. The test link 11 includes a test resistor Rt and a test load St; One end of the i-th test link 11 is used to connect to the i-th power supply rail of the chip to be measured 20, and the other end of the i-th test link 11 is grounded, where 1 ≤ i ≤ N.

[0032] The power supply rail of the chip to be measured 20 is used to supply power to the cores in the chip to be measured 20.

[0033] The (2i - 1)-th detection end of the power consumption acquisition module 13 is connected to one end of the test resistor Rt of the i-th test link 11, and the 2i-th detection end of the power consumption acquisition module 13 is connected to the other end of the test resistor Rt of the i-th test link 11.

[0034] The control module 14 is connected to the communication unit 12 and the power consumption acquisition module 13, and the communication unit 12 is also connected to the chip to be measured 20.

[0035] The control module 14 is used to send task instructions to the chip under test 20, and the task instructions include any one or more of a voltage instruction, a frequency instruction, and a running core instruction. The voltage instruction includes the target voltage corresponding to each power rail, the frequency instruction includes the target operating frequency of the cores in the chip under test 20, and the running core instruction includes the number of running cores.

[0036] The power consumption acquisition module 13 is used to collect the voltage information of each test resistor Rt when the chip under test 20 executes the task instruction, and transmit the voltage information to the control module 14.

[0037] The control module 14 is used to determine the test power consumption of the chip under test 20 according to the voltage information.

[0038] Optionally, it is used to determine the test power consumption of the chip under test 20 according to the voltage information and the resistance value of the deployed test resistor.

[0039] In the chip power consumption measurement system provided by the embodiments of the present invention, by sending task instructions to the chip under test, any one or more of the operating frequency, operating voltage, and number of running cores of the chip under test can be changed, so as to simulate different usage scenarios. Under different scenarios, the power consumption measurement of the chip under test is completed, and the test power consumption of the chip under test can be accurately and quickly obtained.

[0040] In an optional implementation manner, the test board and the chip under test 20 are placed in an incubator, and the control module 14 is connected to the incubator, and can control the incubator to adjust to the target temperature, so as to change the test environment temperature of the chip under test 20 and simulate more working scenarios.

[0041] In Figure 1 On the basis of, regarding the structure of the chip under test, the embodiments of the present invention further provide an optional implementation manner. Please refer to Figure 2 , Figure 2 is the structural schematic diagram of the chip under test provided by the embodiments of the present invention. The chip under test 20 is deployed with a power management unit 201 and a startup unit 202.

[0042] The startup unit 202 is used to execute the running core instruction and start the cores in the chip under test 20 according to the number of running cores.

[0043] The power management unit 201 is used to execute the voltage instruction to adjust the supply voltage of each power rail to the corresponding target voltage.

[0044] The power management unit 201 is further used to execute the frequency instruction to make the cores in the chip under test 20 run at the target operating frequency.

[0045] Please continue to refer to Figure 2 , the communication unit 12 includes a first UART communication interface 121, a second UART communication interface 122, and an interface selector 124.

[0046] One end of the first UART communication interface 121 is connected to the power management unit 201, and the other end of the first UART communication interface 121 is connected to the first downstream port of the interface selector 124.

[0047] One end of the second UART communication interface 122 is connected to the startup unit 202, and the other end of the second UART communication interface 122 is connected to the second downstream port of the interface selector 124.

[0048] The upstream port of the interface selector 124 is connected to the control module 14.

[0049] The interface selector 124 is used to switch the conduction relationship between its internal downstream port and upstream port according to an instruction or a preset rule.

[0050] The first UART communication interface 121 and the second UART communication interface 122 are used to realize the communication interaction between the chip under test 20 and the control module 14. It should be understood that in the chip power consumption measurement system provided by the embodiment of the present invention, only one upstream port of the interface selector 124 needs to be connected to the control module 14, that is, the power management unit 201 and the startup unit 202 share an interface of the control module 14 to realize the reasonable application of the pins of the control module 14.

[0051] Please continue to refer to Figure 2 , in an optional implementation manner, the chip under test 20 is further provided with a temperature detection unit 203, and the temperature detection unit 203 is connected to one or more temperature sensors (not shown in the figure) deployed on the chip under test 20.

[0052] The communication unit 12 further includes a third UART communication interface 123. One end of the third UART communication interface 123 is connected to the temperature detection unit 203, and the other end of the third UART communication interface 123 is connected to the third downstream port of the interface selector 124.

[0053] The temperature detection unit 203 is used to collect the temperature data monitored by each temperature sensor and transmit the temperature data to the control module 14.

[0054] The control module 14 can generate a temperature rise curve and a temperature average value of each temperature monitoring position in the chip under test 20 according to the temperature data uploaded by the temperature detection unit 203, and then evaluate the heat dissipation state in the corresponding power consumption scenario according to the temperature rise curve and the temperature average value.

[0055] In an optional implementation manner, when evaluating the heat dissipation state, the rotation speed information of the heat dissipation fan in the chip under test 20 can also be combined.

[0056] Based on the foregoing, regarding the structure of the control module, an alternative embodiment is further provided in the embodiments of the present invention. Please refer to Figure 3 , Figure 3 which is a schematic structural diagram of the control module provided in the embodiments of the present invention.

[0057] The control module 14 includes a first control unit 141 and a second control unit 142, and the second control unit 142 includes a first MCU 1421.

[0058] The first MCU 1421 is respectively connected to the power consumption acquisition module 13 and the first control unit 141.

[0059] I2C can be used for communication between the first MCU 1421 and the power consumption acquisition module 13.

[0060] The first MCU 1421 is configured to forward the voltage information of each test resistor Rt transmitted by the power consumption acquisition module 13 to the first control unit 141.

[0061] The first control unit 141 is configured to determine the test power consumption of the chip under test 20 according to the voltage information.

[0062] Please continue to refer to Figure 3 , and the second control unit 142 further includes a second MCU 1422.

[0063] The second MCU 1422 is respectively connected to the upstream port of the interface selector 124 and the first control unit 141.

[0064] The second MCU 1422 is configured to perform protocol conversion on the task instructions issued by the first control unit 141 and transmit the converted instructions to the interface selector 124.

[0065] The second MCU 1422 is further configured to perform protocol conversion on the temperature data uploaded by the interface selector 124 and transmit the converted temperature data to the first control unit 141.

[0066] The first control unit 141 is configured to perform heat dissipation state evaluation in combination with the temperature data.

[0067] The second MCU 1422 and the chip under test 20 communicate using a UART communication interface.

[0068] In the chip power consumption measurement system provided in the embodiments of the present invention, the expected evaluation power consumption is achieved by dynamically adjusting the voltage frequency and the number of switching cores for each path, and the rising curve and average value of the temperature at different positions in the corresponding chip after the feedback load is applied, as well as the utilization rate of the corresponding cores, are fed back. Combining the platform fan speed and power efficiency, a comprehensive evaluation scheme is given for customers' design reference and subsequent chip iteration.

[0069] In an alternative embodiment, the test load St is an adjustable load, and the first control unit 141 is also connected to the adjustable load.

[0070] The first control unit 141 is configured to send a load adjustment instruction to the test load St to change the equivalent resistance of the test load St, thereby enabling conversion of more test scenarios.

[0071] In an alternative embodiment, the first control unit 141 is configured to determine the test power consumption of the chip under test 20 based on the voltage information and the resistance value of the test resistor Rt.

[0072] Optionally, P = Vsense × Vsense ÷ R, where P represents the test power consumption of the i-th power rail, Vsense represents the voltage across the test resistor of the i-th test link, and R represents the resistance value of the test resistor of the i-th test link. After determining the test power consumption of all power rails, the test power consumption of the chip under test 20 can be further determined, and the test power consumption of the chip under test 20 is the sum of the test power consumptions of all power rails.

[0073] In an alternative embodiment, the power consumption acquisition module 13 includes one or more power consumption acquisition chips (which may but are not limited to PAC1954).

[0074] An embodiment of the present invention also provides a method for measuring chip power consumption, which is applied to the above chip power consumption measurement system. The method for measuring chip power consumption includes: S101, S102, and S103, which are specifically described as follows.

[0075] S101, the control module sends a task instruction to the chip under test.

[0076] The task instruction includes any one or more of a voltage instruction, a frequency instruction, and a running core instruction. The voltage instruction includes the target voltage corresponding to each power rail, the frequency instruction includes the target operating frequency of the core in the chip under test, and the running core instruction includes the number of running cores.

[0077] S102, when the chip under test executes the task instruction, the power consumption acquisition module acquires the voltage information of each test resistor and transmits the voltage information to the control module.

[0078] S103, the control module determines the test power consumption of the chip under test based on the voltage information.

[0079] In summary, a chip power consumption measurement system and method provided by an embodiment of the present invention. The chip power consumption measurement system includes a test board, a power consumption acquisition module, and a control module. The control module sends task instructions to the chip under test. The task instructions include any one or more of a voltage instruction, a frequency instruction, and a running core instruction. The voltage instruction includes the target voltage corresponding to each power rail. The frequency instruction includes the target operating frequency of the core in the chip under test. The running core instruction includes the number of running cores. When the chip under test executes the task instructions, the power consumption acquisition module acquires the voltage information of each test resistor and transmits the voltage information to the control module. The control module determines the test power consumption of the chip under test according to the voltage information. By sending task instructions to the chip under test, any one or more of the operating frequency, operating voltage, and number of running cores of the chip under test can be changed, so as to simulate different usage scenarios. Under different scenarios, the power consumption measurement of the chip under test is completed, and the test power consumption of the chip under test can be accurately and quickly obtained.

[0080] The foregoing is only a preferred embodiment of the present invention and is not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and changes. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

[0081] For those skilled in the art, it is obvious that the present invention is not limited to the details of the above-described exemplary embodiments, and without departing from the spirit or basic characteristics of the present invention, the present invention can be implemented in other specific forms. Therefore, from any point of view, the embodiments should be regarded as exemplary and non-limiting. The scope of the present invention is defined by the appended claims rather than the above description. Therefore, it is intended to embrace all changes falling within the meaning and scope of the equivalent elements of the claims in the present invention. Any reference signs in the claims should not be regarded as limiting the claimed claim.

Claims

1. A chip power consumption measurement system, characterized in that, The chip power consumption measurement system includes a test board, a power consumption acquisition module, and a control module. The test board is deployed with a communication unit and N test links, and each test link includes a test resistor and a test load; One end of the i-th test link is used to connect to the i-th power rail of the chip under test, and the other end of the i-th test link is grounded, where 1 ≤ i ≤ N; The (2i - 1)-th detection end of the power consumption acquisition module is connected to one end of the test resistor of the i-th test link, and the 2i-th detection end of the power consumption acquisition module is connected to the other end of the test resistor of the i-th test link; The control module is connected to the communication unit and the power consumption acquisition module, and the communication unit is also connected to the chip under test; The control module is used to send task instructions to the chip under test. The task instructions include any one or more of a voltage instruction, a frequency instruction, and a running core instruction. The voltage instruction includes the target voltage corresponding to each power rail. The frequency instruction includes the target operating frequency of the core in the chip under test. The running core instruction includes the number of running cores; The power consumption acquisition module is used to collect the voltage information of each test resistor when the chip under test executes the task instructions, and transmit the voltage information to the control module; The control module is used to determine the test power consumption of the chip under test according to the voltage information.

2. The chip power consumption measurement system according to claim 1, wherein The chip under test is deployed with a power management unit and a startup unit; The startup unit is used to execute the running core instruction and start the cores in the chip under test according to the number of running cores; The power management unit is used to execute the voltage instruction to adjust the supply voltage of each power rail to the corresponding target voltage; The power management unit is also used to execute the frequency instruction to make the cores in the chip under test operate at the target operating frequency.

3. The chip power consumption measurement system according to claim 2, wherein The communication unit includes a first UART communication interface, a second UART communication interface, and an interface selector; One end of the first UART communication interface is connected to the power management unit, and the other end of the first UART communication interface is connected to the first downstream port of the interface selector; One end of the second UART communication interface is connected to the startup unit, and the other end of the second UART communication interface is connected to the second downstream port of the interface selector; The upstream port of the interface selector is connected to the control module; The interface selector is used to switch the conduction relationship between its internal downstream port and upstream port according to an instruction or a preset rule.

4. The chip power consumption measurement system according to claim 3, wherein The chip under test is also deployed with a temperature detection unit, and the temperature detection unit is connected to one or more temperature sensors deployed on the chip under test; The communication unit further includes a third UART communication interface. One end of the third UART communication interface is connected to the temperature detection unit, and the other end of the third UART communication interface is connected to the third downstream port of the interface selector; The temperature detection unit is used to collect the temperature data monitored by each temperature sensor and transmit the temperature data to the control module.

5. The chip power consumption measurement system according to claim 4, wherein, The control module includes a first control unit and a second control unit, and the second control unit includes a first MCU; The first MCU is respectively connected to the power consumption acquisition module and the first control unit; The first MCU is configured to forward the voltage information of each test resistor transmitted by the power consumption acquisition module to the first control unit; The first control unit is configured to determine the test power consumption of the chip under test according to the voltage information.

6. The chip power consumption measurement system according to claim 5, characterized in that The second control unit further includes a second MCU; The second MCU is respectively connected to the upstream port of the interface selector and the first control unit; The second MCU is configured to perform protocol conversion on the task instruction issued by the first control unit and transmit the converted instruction to the interface selector; The second MCU is further configured to perform protocol conversion on the temperature data uploaded by the interface selector and transmit the converted temperature data to the first control unit; The first control unit is configured to evaluate the heat dissipation state in combination with the temperature data.

7. The chip power consumption measurement system according to claim 5, characterized in that The test load is an adjustable load, and the first control unit is further connected to the adjustable load; The first control unit is configured to send a load adjustment instruction to the test load to change the equivalent resistance of the test load.

8. The chip power consumption measurement system according to claim 5, characterized in that, The first control unit is configured to determine the test power consumption of the chip under test according to the voltage information and the resistance value of the test resistor.

9. The chip power consumption measurement system according to claim 5, characterized in that, The power consumption acquisition module includes one or more power consumption acquisition chips.

10. A method for measuring the power consumption of a chip, characterized in that, Applied to the chip power consumption measurement system according to any one of claims 1-9, the method includes: The control module sends a task instruction to the chip under test, and the task instruction includes any one or more of a voltage instruction, a frequency instruction, and a running core instruction. The voltage instruction includes the target voltage corresponding to each power supply rail, the frequency instruction includes the target operating frequency of the core in the chip under test, and the running core instruction includes the number of running cores; When the chip under test executes the task instruction, the power consumption acquisition module acquires the voltage information of each test resistor and transmits the voltage information to the control module; The control module determines the test power consumption of the chip under test according to the voltage information.

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