Central processing unit power supply efficiency test method and device, electronic equipment and medium

Abstract

The invention discloses a central processing unit power supply efficiency test method and device, electronic equipment and a medium, and relates to the technical field of server hardware testing, and the method comprises the steps: generating a plurality of test loads and a plurality of temperature test scenes if a data synchronous collection signal is detected, and carrying out the testing of the power supply efficiency of a central processing unit based on a preset traversal strategy; all power supply states of the central processing unit are traversed according to various test loads and various temperature test scenes, load change data, power supply data and temperature data of the central processing unit in the traversing process are collected, the data are packaged, and power supply efficiency test data can be obtained. And obtaining a central processing unit power supply efficiency test result according to the power supply efficiency test data. Therefore, by automatically adjusting the test load and the temperature test scene, the real business scene is simulated, the problem that the prior art depends on a fixed load mode and cannot reflect the dynamic frequency / voltage regulation characteristic of the CPU in the real scene is solved, and the technical effects of high test efficiency and high accuracy are achieved.

Description

Technical Field

[0001] This application relates to the technical field of server hardware testing, and particularly to a method, device, electronic device, and medium for testing the power efficiency of a central processing unit. Background Art

[0002] The power efficiency of a CPU (Central Processing Unit) refers to the measure of the energy efficiency ratio when the central processing unit is performing computing tasks, that is, the amount of work that can be completed per watt of electrical energy. High power efficiency means that the CPU can provide high performance output while consuming less power, which is particularly important for extending the battery life of mobile devices, reducing energy consumption in data centers, and lowering overall operating costs. Power efficiency is a core competitive indicator for CPU manufacturers. By measuring power efficiency, manufacturers can optimize the power consumption strategy of the CPU under different loads (such as dynamic frequency adjustment), and balance performance and battery life. Measuring the power efficiency of the CPU is not only the basis for technical optimization, but also the core means to achieve economic benefits, environmental responsibility, and improved user experience.

[0003] In related technologies, CPU efficiency testing usually adopts the method of using an electronic load to draw current, that is, using an electronic load device to simulate the load situation of the CPU in actual work, and by adjusting the electronic load, recording the current draw data of the CPU under different load conditions, and then analyzing the relationship between current consumption and CPU performance to evaluate its efficiency. However, in this method, the electronic load usually can only provide a fixed load mode and cannot fully simulate the dynamic frequency / voltage adjustment characteristics of the CPU in the real scenario, which urgently needs to be solved. Summary of the Invention

[0004] The present invention provides a method, device, electronic device, and medium for testing the power efficiency of a central processing unit, so as to at least solve the problem that the prior art mostly relies on a fixed load mode and cannot reflect the dynamic frequency / voltage adjustment characteristics of the CPU in the real scenario, and achieve the technical effects of high test efficiency and high accuracy.

[0005] The present invention provides a method for testing the power efficiency of a central processing unit, including the following steps: Determine whether a data synchronization acquisition signal is detected; If the data synchronization acquisition signal is detected, generate multiple test loads and multiple temperature test scenarios, and based on a preset traversal strategy, traverse all power states of the central processing unit according to the multiple test loads and the multiple temperature test scenarios, and collect the central processing unit load change data, power supply data, and temperature data during the traversal process; Package the central processing unit (CPU) load change data, the power supply data, and the temperature data to obtain power efficiency test data, and obtain the CPU power efficiency test result according to the power efficiency test data.

[0006] The present invention provides a CPU power efficiency test device, including: A judgment module, configured to judge whether a data synchronization acquisition signal is detected; A traversal module, configured to generate a variety of test loads and a variety of temperature test scenarios when the data synchronization acquisition signal is detected, and based on a preset traversal strategy, traverse all power states of the CPU according to the variety of test loads and the variety of temperature test scenarios, and collect the CPU load change data, the power supply data, and the temperature data during the traversal process; An acquisition module, configured to package the CPU load change data, the power supply data, and the temperature data to obtain power efficiency test data, and obtain the CPU power efficiency test result according to the power efficiency test data.

[0007] The present invention also provides an electronic device, including: a memory, configured to store a computer program; a processor, configured to implement the steps of any one of the above CPU power efficiency test methods when executing the computer program.

[0008] The present invention also provides a computer-readable storage medium, in which a computer program is stored, and when the computer program is executed by a processor, the steps of any one of the above CPU power efficiency test methods are implemented.

[0009] The present invention also provides a computer program product, including a computer program, and when the computer program is executed by a processor, the steps of any one of the above CPU power efficiency test methods are implemented.

[0010] Through the present invention, when a data synchronization acquisition signal is detected, a variety of test loads and a variety of temperature test scenarios can be generated, and based on a preset traversal strategy, all power states of the CPU are traversed according to the variety of test loads and the variety of temperature test scenarios, and the CPU load change data, the power supply data, and the temperature data during the traversal process are collected; package the CPU load change data, the power supply data, and the temperature data to obtain power efficiency test data, and obtain the CPU power efficiency test result according to the power efficiency test data. Thus, by automatically adjusting the test load and the temperature test scenario to simulate various situations that may occur in actual use, the power efficiency of the CPU can be evaluated more accurately, solving the problem that the prior art mostly relies on a fixed load mode and cannot reflect the dynamic frequency / voltage regulation characteristics of the CPU in a real scenario, and achieving the technical effects of high test efficiency and high accuracy. Brief Description of the Drawings

[0011] To more clearly illustrate the embodiments of the present invention, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on these drawings.

[0012] Figure 1 It is a flowchart of a method for testing the power efficiency of a central processing unit provided by an embodiment of the present invention; Figure 2 It is a schematic diagram of the multi-voltage domain power supply and power management cooperation architecture of a central processing unit in the related art; Figure 3 It is a flowchart of another method for testing the power efficiency of a central processing unit provided by an embodiment of the present invention; Figure 4 It is a block diagram of a device for testing the power efficiency of a central processing unit provided by an embodiment of the present invention; Figure 5 It is a schematic diagram of the structure of an electronic device provided by an embodiment of the present invention. Detailed Embodiments

[0013] Next, the technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, rather than all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts belong to the protection scope of the present invention.

[0014] It should be noted that in the description of the present invention, the terms "include", "comprise" or any other variation thereof are intended to cover a non-exclusive inclusion, so that a process, method, article or device including a series of elements not only includes those elements, but also includes other elements not expressly listed, or further includes elements inherent to such process, method, article or device. The terms "first", "second", etc. in the present invention are used to distinguish similar objects, rather than to describe a specific order or sequence.

[0015] To enable those skilled in the art of the present technology to better understand the solution of the present invention, the present invention will be further described in detail below in conjunction with the drawings and specific embodiments.

[0016] The embodiments of the present invention provide a method for testing the power efficiency of a central processing unit. In combination with the execution process of the method for testing the power efficiency of the central processing unit, the method will be described in detail.

[0017] Figure 1 It is a flowchart of the central processing unit power efficiency test method according to an embodiment of the present invention.

[0018] Before introducing the central processing unit power efficiency test method proposed by the embodiments of the present invention, the relevant technical background will be introduced first.

[0019] As Figure 2 shown, the CPU includes multiple different voltage domains, and each voltage domain has its specific requirements. To meet these requirements, the power chips that supply power to the CPU voltage domain are mainly divided into three categories: VRM (Voltage Regulator Module), POL (Point of Load), and EFUSE (Electronic Fuse). Among them, the VRM communicates with the CPU through SVID (Serial Voltage Identification), enabling the CPU to directly read the voltage and current information provided by the VRM. However, there is no communication between the POL, EFUSE and the CPU, and their voltage and current information cannot be directly obtained by the CPU. To obtain the voltage and current information of the POL and EFUSE, it is necessary to collect them with the help of a power sampling circuit. Since the CPU and the power sampling circuit cannot synchronously collect data, there may be a certain deviation in the obtained efficiency value. In addition, the traditional CPU efficiency test method usually uses the method of pulling current with an electronic load, and this method cannot truly simulate the performance of the CPU in the actual working state.

[0020] Based on the above problems, the embodiments of the present invention propose a central processing unit power efficiency test method, which can simulate various working states of the CPU and the switching boundaries of each working state, realize the synchronous collection of CPU and power data, and at the same time consider the influence of temperature on efficiency to improve the accuracy of the test.

[0021] Exemplarily, as Figure 1 shown, the central processing unit power efficiency test method includes the following steps: In step S101, it is judged whether a data synchronous collection signal is detected.

[0022] It can be understood that traditional power measurement methods often rely on software polling or interrupt synchronization mechanisms to obtain data, which can lead to a time stamp deviation of microseconds between the electrical power sampling and the Performance Monitoring Counter (PMC). This tiny time deviation may not have a significant impact in a static environment, but in the application scenario of Dynamic Voltage and Frequency Scaling (DVFS), this deviation will have a greater negative impact on the accuracy of the energy efficiency model.

[0023] To avoid the above problems, the embodiments of the present invention can generate a data synchronization acquisition signal through the GPIO (General Purpose Input / Output) pins of a Complex Programmable Logic Device (CPLD). This signal can be sent to the CPU core, high-precision data acquisition, and temperature sensors simultaneously in the form of a hardware-level trigger to form a globally synchronized acquisition starting point and achieve a synchronization accuracy of nanoseconds.

[0024] In step S102, if a data synchronization acquisition signal is detected, a variety of test loads and a variety of temperature test scenarios are generated, and based on a preset traversal strategy, all power states of the central processing unit are traversed according to the variety of test loads and the variety of temperature test scenarios, and the CPU load change data, power supply data, and temperature data during the traversal process are collected.

[0025] Specifically, in the case of detecting a data synchronization acquisition signal, a series of differentiated CPU load patterns (i.e., a variety of test loads) can be generated to cover different working states, and a variety of temperature test scenarios can be generated to evaluate the performance of the CPU under different temperature working conditions. Further, based on a preset traversal strategy, all power states of the CPU can be traversed according to the variety of test loads and the variety of temperature test scenarios. During the traversal process, the CPU load change data can be continuously collected, and these data reflect the workload of the CPU under different test scenarios. At the same time, the power supply data can also be recorded to monitor the change of the power supply state. In addition, the acquisition of temperature data is also essential, which records the temperature change of the CPU under different test scenarios. Through the comprehensive analysis of these data, the performance and stability of the CPU under various working conditions can be comprehensively evaluated.

[0026] It should be noted that a single data synchronization acquisition signal can cause the BMC (Baseboard Management Controller) to perform up to 1000 polling operations to ensure the integrity and accuracy of power data. In addition, after the BMC completes the polling, the current data synchronization acquisition signal can be pulled low to control the server platform to enter the normal working mode.

[0027] The following details how to synchronously acquire the central processing unit load change data, power supply data, and temperature data.

[0028] When the rising edge of the synchronization pulse (i.e., the data synchronization acquisition signal, the instant from low level to high level) is triggered, all relevant devices (such as CPU, power meter, temperature sensor) start to acquire data simultaneously and record all the acquired data in the form of timestamp marking. That is, the CPU can immediately freeze its internal performance monitoring unit (such as PEBS (Processor Event-Based Sampling) of Intel), stop the current monitoring task, and record the current key performance indicators, including the current instruction cycle (the number of instructions executed by the CPU), cache hit rate (the proportion of data required found in the CPU cache), and other key indicators, which reflect the performance of the CPU in the current state. The high-precision power meter (a device for measuring the power consumption of the CPU) can synchronously capture the transient current and voltage data, with a sampling rate of up to more than 10MS / s, capable of completely capturing the surge current and voltage drop during DVFS switching, thus providing more accurate power data. The temperature sensor can obtain the chip surface heat distribution data with a response speed at the microsecond level. The timestamps of all devices (CPU, power meter, temperature sensor) start from the rising edge of the synchronization pulse, and a highly stable constant temperature crystal oscillator is used as the clock source to uniformly calibrate the timestamps of all devices. Since there will be delays when the signal is transmitted on the PCB (Printed Circuit Board Routing) traces, and the response times of different sensors may also be different, it is necessary to dynamically compensate for these physical delays. Through compensation, the synchronization of data acquisition can be further improved, and finally, the nanosecond-level alignment of power, performance, and temperature data can be achieved.

[0029] Among them, the power supply data includes voltage, current, power consumption, etc.; the temperature data is the temperature data of the CPU chip surface collected by the temperature sensor.

[0030] Optionally, in some embodiments, the central processing unit load change data includes at least one of the residence time in the energy-saving state, frequency change in the performance state, number of state switches, and delay time.

[0031] It can be understood that the residence time in the energy-saving state is the residence time of the CPU in different C-States; the frequency change in the performance state is the frequency change of the CPU in different P-States; the number of state switches is the number of switches of the CPU between different states; and the delay time is the delay time of the state switch.

[0032] Specifically, the embodiments of the present invention can use an integrated system tool to monitor in real time the residence time in the energy-saving state, the frequency change in the performance state, the number of state switches, and the delay time. When the system detects a specific state, for example, when the C0 state has not completely exited, corresponding measures can be taken, that is, to dynamically increase the pressure on I / O (Input / Output) (command line parameter "--io 4") or memory (command line parameter "--hdd 1") through command line parameters, so as to force the CPU to exit its deep sleep state, thereby ensuring that the system performance and response speed are optimized.

[0033] Thus, by monitoring the state changes of the CPU in real time and dynamically adjusting the test load according to the current state, it can be ensured that the test covers the behavior of the CPU in all possible working states, thereby improving the comprehensiveness and accuracy of the test.

[0034] Optionally, in some embodiments, the time stamps between the central processing unit load change data, the power supply data, and the temperature data are less than a preset time stamp.

[0035] Through the hardware-triggered data synchronization acquisition signal and the highly stable constant temperature crystal oscillator clock source, it is ensured that the time stamps of all devices are aligned, that is, the time stamp error between the central processing unit load change data, the power supply data, and the temperature data can be less than the preset time stamp (20 nanoseconds), thereby ensuring a high degree of temporal consistency of the data and achieving nanosecond-level alignment of the power, performance, and temperature data.

[0036] Next, how to generate multiple test loads will be described in detail.

[0037] As a possible implementation manner, in some embodiments, generating multiple test loads includes: determining the load scenario to be simulated; generating multiple test loads based on the preset Stress-NG strategy according to the load scenario to be simulated.

[0038] It can be understood that Stress-NG (Stress Next Generation) is a tool for stress testing systems. It can simulate various different load conditions, which cover multiple aspects such as CPU, memory, disk I / O, and network. Through these simulation tests, users can comprehensively evaluate the performance of the system. In the embodiment of the present invention, a preset Stress-NG strategy is proposed. This strategy can generate dynamic load instructions based on the Stress-NG tool, dynamically adjust the load intensity according to the real-time frequency of the CPU, and thus generate a differentiated CPU load pattern (i.e., test load) according to the load scenario to be simulated. These load patterns can cover the switching situations of C-State and P-State under different load conditions, thereby providing a more accurate test method for in-depth analysis of system performance.

[0039] Among them, C-State and P-State are two working states of the processor. C-State represents the idle state of the processor. Different C-State levels (such as C0, C1, C2... Cn, etc.) correspond to different energy-saving degrees, and the higher the value, the more energy-saving; P-State represents the performance state of the processor. Different P-State levels (such as P0, P1, P2... Pn, etc.) correspond to different frequency and voltage combinations. The lower the P-State, the higher the frequency, the better the performance, but the higher the power consumption.

[0040] Thus, by generating multiple test loads based on the load scenario to be simulated and using the preset Stress-NG strategy, the full-state switching of C-State and P-State can be covered, the comprehensive simulation of the real business scenario can be realized, and it is helpful to test the efficiency under different power management states.

[0041] Optionally, in some embodiments, the load scenario to be simulated includes a first load scenario, a second load scenario, and a third load scenario. Among them, the first load scenario is determined by a first load interval; the second load scenario is determined by a second load interval, and the minimum load value of the second load interval is greater than the maximum load value of the first load interval; the third load scenario is determined by a third load interval, and the minimum load value of the third load interval is greater than the maximum load value of the second load interval.

[0042] Specifically, by using the command-line parameter "--cpu-load", the CPU occupancy rate can be dynamically adjusted (e.g., from 10% to 100%) to simulate the working states of light load (low load, i.e., the first load scenario), medium load (medium load, i.e., the second load scenario), and heavy load (high load, i.e., the third load scenario). Such adjustment can effectively trigger the frequency adjustment mechanism of the P-State, enabling the CPU to switch between different working modes, such as from the energy-saving mode (running at a low frequency) to the high-performance mode (running at a high frequency), thereby testing and evaluating the performance and energy efficiency of the CPU under different workloads.

[0043] It can be understood that different load scenarios to be simulated can be determined by corresponding load intervals. That is, the first load scenario can be set according to the first load interval, within which specific load parameters are defined to simulate the performance of the system under a certain load. Then, the second load scenario can be determined based on the second load interval, and the minimum load value of this interval is set to be higher than the maximum load value of the first load interval, thus ensuring the incrementality and continuity between the load scenarios to be simulated. Similarly, the third load scenario can be set according to the third load interval, and the minimum load value of the third load interval is set to be higher than the maximum load value of the second load interval, which can further ensure that the test covers a wider load range, thereby more comprehensively evaluating the performance and stability of the system.

[0044] In addition, the "--taskset" parameter can be used to bind specific stress test tasks to specific cores of the CPU, and further combined with the "--cpu 0" (all cores) parameter to generate a load spanning multiple cores. This cross-core load can trigger the collaborative switching of the C-State (core state) between multi-core processors, thereby testing the performance and energy efficiency management of the CPU when multi-core processors work collaboratively.

[0045] The following details how to traverse all power states of the central processing unit based on a preset traversal strategy according to multiple test loads and multiple temperature test scenarios.

[0046] As a possible implementation, in some embodiments, traversing all power states of the central processing unit based on a preset traversal strategy according to multiple test loads and multiple temperature test scenarios includes: determining the combined test order of the performance state and the energy-saving state based on the preset traversal strategy; traversing all power states of the central processing unit according to the combined test order and / or the preset periodic load mutation trigger state switching boundary conditions based on multiple temperature test scenarios.

[0047] Specifically, the preset traversal strategy is to traverse the combinations of C0 - Cn and P0 - Pn in sequence, where C0 - Cn are different levels of the C - State (energy - saving state), and P0 - Pn are different levels of the P - State (performance state). By traversing all possible combinations of the energy - saving state and the performance state in sequence based on the preset traversal strategy, it can ensure that the test covers the behavior of the processing chip in various working states, that is, covers all power states of the CPU.

[0048] Based on multiple temperature test scenarios, the "--ignite - cpu" option can be used to simulate the working state of the CPU in a high - temperature scenario of the temperature test scenario by increasing the CPU load. In the high - temperature scenario, verify the down - clocking behavior of the P - State under thermal constraints. During this process, it can be detailedly recorded how the C - State of the CPU gradually degrades due to temperature triggering when the temperature rises, so as to ensure the stable operation of the system under high - temperature conditions. In addition, the working state of the CPU in the normal - temperature scenario of the temperature test scenario can also be simulated to evaluate the behavior of the CPU under typical working conditions.

[0049] In addition to triggering the state - switching boundary conditions according to the combined test sequence, the load intensity can be periodically changed (for example, from high load to idle suddenly) according to the preset periodic load mutation to trigger the switching between different C - States and P - States of the processing chip, dynamically adjusting the load intensity to ensure that the test covers the behavior of the CPU under different loads. It should be noted that the above two strategies for triggering state - switching boundary conditions can also be applied simultaneously to further ensure the comprehensiveness of the test.

[0050] Thus, through the preset traversal strategy, multiple temperature test scenarios, combined with periodic load mutation, comprehensively cover and verify the behavior of the CPU under different working states, which not only improves the comprehensiveness and accuracy of the test, but also provides reliable data support for the power - efficiency optimization of the CPU.

[0051] In step S103, the load - change data, power - supply data, and temperature data of the central processing unit are encapsulated to obtain power - efficiency test data, and the power - efficiency test result of the central processing unit is obtained according to the power - efficiency test data.

[0052] Specifically, after collecting the data on the changes in the central processor load, power supply data, and temperature data, the BMC can communicate with each collection device (such as the CPU, high-precision power meter, temperature sensor, etc.) through a low-latency bus, encapsulate all the data collected by the devices (i.e., the data on the changes in the central processor load, power supply data, and temperature data) into a data frame, and assign a unified time tag to each data frame. This time tag ensures that all the data is synchronized in time, thereby obtaining the power efficiency test data. These data reflect the power consumption and power conversion efficiency of the CPU during actual operation. Subsequently, an efficiency calculation engine can be used to integrate these power efficiency test data, and through a temperature compensation algorithm, further analyze and calculate the power efficiency test results of the CPU, so as to evaluate the energy efficiency performance of the CPU under different working conditions.

[0053] It can be understood that temperature has a significant impact on the performance and power consumption of the CPU. Especially in a high-temperature environment, the CPU may automatically throttle to prevent overheating. The temperature compensation algorithm can ensure that the calculated efficiency value reflects the real situation by correcting the influence of temperature on the electric power and performance data.

[0054] In addition, by using the BMC to integrate multi-source data and encapsulate it into a data frame with a unified time tag, the synchronization, integrity, and reliability of the data are significantly improved, facilitating subsequent data analysis and processing, enhancing the accuracy and reliability of the test, and optimizing the power consumption management strategy of the CPU.

[0055] Optionally, in some embodiments, after obtaining the central processor power efficiency test results based on the power efficiency test data, it further includes: optimizing the energy efficiency of the data center based on the central processor power efficiency test results.

[0056] It can be understood that in a data center, a large number of servers and computing devices consume a large amount of electricity. Through the CPU power efficiency test, the power efficiency test results (detailed power consumption and performance data) of the CPU under different working conditions can be obtained, and based on this test result, it can be used to optimize the overall energy efficiency of the data center, reduce the operating cost, and improve the performance and reliability of the system at the same time.

[0057] Optionally, in some embodiments, after obtaining the central processor power efficiency test results based on the power efficiency test data, it further includes: analyzing the energy consumption of mobile devices based on the central processor power efficiency test results.

[0058] It is understandable that the battery life of mobile devices (such as smartphones and tablets) is one of the key factors in the user experience. Through CPU power efficiency testing, it is possible to gain an in-depth understanding of the power consumption of mobile devices in different usage scenarios, thereby optimizing the device's energy consumption management strategy and extending the battery life.

[0059] Optionally, in some embodiments, after obtaining the central processing unit power efficiency test result based on the power efficiency test data, it further includes: researching the power management of the RISC-V architecture based on the central processing unit power efficiency test result.

[0060] It is understandable that RISC-V (Reduced Instruction Set Computing - Five Architecture) is an open-source instruction set architecture. Through CPU power efficiency testing, it is possible to research and optimize the power management strategy of the RISC-V architecture, such as DVFS and power-saving state management, to improve its energy efficiency ratio in different application scenarios.

[0061] Furthermore, in some embodiments, after traversing all the power states of the central processing unit according to a preset traversal strategy based on multiple test loads and multiple temperature test scenarios, it further includes: determining whether the test result meets the preset coverage requirement; if the test result does not meet the preset coverage requirement, identifying the untriggered state combinations, and dynamically adjusting the load parameters of the untriggered state combinations based on a preset load parameter adjustment strategy, and performing tests according to the adjusted state combinations.

[0062] Specifically, the utilization rate of the CPU under different loads during the stress test and the number of context switches of the system under different loads can be output through the "--metrics-brief" option, and the output performance metrics are compared with the state transition log (which records the state transition situation of the processing chip under different loads) to verify whether the coverage of the test covers all expected state combinations (that is, determining whether the test result meets the preset coverage requirement). In the case where the test result does not meet the preset coverage requirement, by analyzing the state transition log, the untriggered state combinations can be identified (for example, some C-States are not exited). According to the identification result, a preset load parameter adjustment strategy can be used to automatically adjust the load parameters to complete the test scenario, for example, increasing the "--vm-bytes" memory pressure to force the processing chip to enter the untriggered state combination to ensure that the test covers all possible working states and state transition conditions.

[0063] Thus, by dynamically adjusting the test load parameters, it is ensured that the test covers all expected state combinations, improving the comprehensiveness of the test; by completing the test scenarios, it is ensured that the test results can accurately reflect the power efficiency of the CPU chip under all possible working states.

[0064] As a possible implementation manner, in some other embodiments, after determining whether a data synchronization acquisition signal is detected, it further includes: if the data synchronization acquisition signal is not detected, maintaining the server platform in a preset working mode.

[0065] That is to say, when the data synchronization acquisition signal is not detected, the server platform can be maintained in the preset working mode. Among them, the preset working mode refers to the state of the server platform during normal operation. For example, running a specific application program or being in a standby state.

[0066] Thus, through this mechanism, the synchronization and accuracy of the test can be ensured, improving the reliability and test efficiency of the test.

[0067] Furthermore, in some embodiments, before determining whether a data synchronization acquisition signal is detected, it further includes: determining whether there is a central processing unit power efficiency test requirement; if there is a central processing unit power efficiency test requirement, controlling the server platform to enter the preset working mode and performing a reset operation on the server platform.

[0068] That is to say, at the initial stage of the CPU power efficiency test process, it can first be determined whether there is a central processing unit power efficiency test requirement. If there is a test requirement, then the system can control the server platform to enter the preset working mode and perform a reset operation on the server platform to ensure that the server is in a consistent initial state at the start of the test. This design can improve the reliability and accuracy of the test and ensure the validity of the test results.

[0069] To facilitate those skilled in the art to further understand the central processing unit power efficiency test method proposed by the embodiments of the present invention, the following will be further elaborated in conjunction with Figure 3 for further elaboration.

[0070] As Figure 3 shown, the central processing unit power efficiency test method may further include the following steps: Step S301, enter the preparation work for the central processing unit power efficiency test.

[0071] Step S302, control the server platform reset signal to be low.

[0072] Step S303, determine whether a data synchronization acquisition signal is issued. If so, execute step S304, otherwise, execute S308.

[0073] Step S304, dynamic load generation, traverse the power states of all central processing units.

[0074] Step S305, read the data related to the central processing unit (load change data), power supply data, and temperature data.

[0075] Step S306, use the baseboard management controller to encapsulate the data related to the central processing unit (load change data), power supply data, and temperature data into a data frame, and assign a unified time tag to each data frame to obtain power efficiency test data.

[0076] Step S307, end the power efficiency test process of the central processing unit.

[0077] Step S308, control the server platform to execute normal services.

[0078] According to the central processing unit power efficiency test method proposed by the embodiments of the present invention, when a data synchronization acquisition signal is detected, various test loads and various temperature test scenarios can be generated, and based on a preset traversal strategy, all power states of the central processing unit are traversed according to various test loads and various temperature test scenarios, and the load change data, power supply data, and temperature data of the central processing unit during the traversal process are collected; encapsulate the load change data, power supply data, and temperature data of the central processing unit to obtain power efficiency test data, and obtain the power efficiency test result of the central processing unit according to the power efficiency test data. Thus, by automatically adjusting the test load and temperature test scenarios to simulate various situations that may occur in actual use, the power efficiency of the central processing unit can be more accurately evaluated, solving the problem that the prior art mostly relies on a fixed load mode and cannot reflect the dynamic frequency / voltage regulation characteristics of the CPU in the real scenario, and achieving the technical effects of high test efficiency and high accuracy.

[0079] Through the description of the above embodiments, those skilled in the art can clearly understand that the system according to the above embodiments can be implemented by means of software plus a necessary general hardware platform. Of course, it can also be implemented by hardware, but in many cases, the former is a better implementation method.

[0080] The embodiments of the present invention also provide a central processing unit power efficiency test device.

[0081] Figure 4 It is a block diagram of a central processing unit power efficiency test device according to an embodiment of the present invention.

[0082] As Figure 4 shown, the central processing unit power efficiency test device 10 includes: a judgment module 100, a traversal module 200, and an acquisition module 300.

[0083] Among them, a judgment module 100 is configured to judge whether a data synchronization acquisition signal is detected; A traversal module 200 is configured to, when a data synchronization acquisition signal is detected, generate a variety of test loads and a variety of temperature test scenarios, and based on a preset traversal strategy, traverse all power states of a central processing unit according to the variety of test loads and the variety of temperature test scenarios, and collect the central processing unit load change data, power supply data, and temperature data during the traversal process; An acquisition module 300 is configured to encapsulate the central processing unit load change data, power supply data, and temperature data to obtain power efficiency test data, and obtain a central processing unit power efficiency test result according to the power efficiency test data.

[0084] Optionally, in some embodiments, the traversal module 200 is specifically configured to: Determine a combined test order of a performance state and an energy-saving state based on a preset traversal strategy; Based on the variety of temperature test scenarios, traverse all power states of the central processing unit according to the combined test order and / or a preset periodic load mutation trigger state switching boundary condition.

[0085] Optionally, in some embodiments, after traversing all power states of the central processing unit according to the variety of test loads and the variety of temperature test scenarios based on a preset traversal strategy, Optionally, in some embodiments, after traversing all power states of the central processing unit according to the variety of test loads and the variety of temperature test scenarios based on a preset traversal strategy, the traversal module 200 is further configured to: Judge whether a test result meets a preset coverage requirement; If the test result does not meet the preset coverage requirement, identify an untriggered state combination, dynamically adjust the load parameters of the untriggered state combination based on a preset load parameter adjustment strategy, and perform a test according to the adjusted state combination.

[0086] Optionally, in some embodiments, the traversal module 200 is specifically configured to: Determine a load scenario to be simulated; Generate a variety of test loads according to the load scenario to be simulated based on a preset Stress-NG strategy.

[0087] Optionally, in some embodiments, the load scenario to be simulated includes a first load scenario, a second load scenario, and a third load scenario, where The first load scenario is determined by a first load range; The second load scenario is determined by a second load range, and the minimum load of the second load range is greater than the maximum load of the first load range; The third load scenario is determined by a third load range, and the minimum load of the third load range is greater than the maximum load of the second load range.

[0088] Optionally, in some embodiments, the time stamps among the central processing unit load change data, the power supply data, and the temperature data are less than a preset time stamp.

[0089] Optionally, in some embodiments, the central processing unit load change data includes at least one of the residence time in the energy-saving state, the frequency change in the performance state, the number of state switches, and the delay time.

[0090] Optionally, in some embodiments, after determining whether a data synchronization acquisition signal is detected, the determination module 100 is further configured to: When the data synchronization acquisition signal is not detected, maintain the server platform in a preset working mode.

[0091] Optionally, in some embodiments, before determining whether a data synchronization acquisition signal is detected, the determination module 100 is further configured to: Determine whether there is a need for central processing unit power efficiency testing; If there is a need for central processing unit power efficiency testing, control the server platform to enter a preset working mode and perform a reset operation on the server platform.

[0092] Optionally, in some embodiments, after obtaining the central processing unit power efficiency test result based on the power efficiency test data, the obtaining module 300 is further configured to: Optimize the energy efficiency of the data center based on the central processing unit power efficiency test result.

[0093] Optionally, in some embodiments, after obtaining the central processing unit power efficiency test result based on the power efficiency test data, the obtaining module 300 is further configured to: Analyze the energy consumption of the mobile device based on the central processing unit power efficiency test result.

[0094] Optionally, in some embodiments, after obtaining the central processing unit power efficiency test result based on the power efficiency test data, the obtaining module 300 is further configured to: Research the power management of the RISC-V architecture based on the central processing unit power efficiency test result.

[0095] For the description of the features in the embodiments corresponding to the central processing unit power efficiency test device, reference may be made to the relevant descriptions in the embodiments corresponding to the central processing unit power efficiency test method, which will not be elaborated here one by one.

[0096] According to the central processing unit power efficiency testing device proposed by the embodiments of the present invention, when a data synchronization acquisition signal is detected, a variety of test loads and a variety of temperature test scenarios can be generated, and based on a preset traversal strategy, all power states of the central processing unit are traversed according to the variety of test loads and the variety of temperature test scenarios, and the central processing unit load change data, power supply data, and temperature data during the traversal process are collected; the central processing unit load change data, power supply data, and temperature data are encapsulated to obtain power efficiency test data, and the central processing unit power efficiency test result is obtained according to the power efficiency test data. Thus, by automatically adjusting the test load and temperature test scenarios to simulate various situations that may occur in actual use, the power efficiency of the central processing unit can be more accurately evaluated, solving the problem in the prior art that mostly relies on a fixed load mode and cannot reflect the dynamic frequency / voltage regulation characteristics of the CPU in a real scenario, and achieving the technical effects of high test efficiency and high accuracy.

[0097] Figure 5 The structural schematic diagram of the electronic device provided by the embodiments of the present invention. The electronic device may include: A memory 501, a processor 502, and a computer program stored on the memory 501 and executable on the processor 502.

[0098] When the processor 502 executes the program, it implements the steps in any of the above embodiments of the central processing unit power efficiency testing method.

[0099] Further, the electronic device further includes: A communication interface 503, used for communication between the memory 501 and the processor 502.

[0100] The memory 501, used for storing a computer program executable on the processor 502.

[0101] The memory 501 may include a high-speed RAM (Random Access Memory) memory, and may also include a non-volatile memory, such as at least one disk memory.

[0102] If the memory 501, the processor 502, and the communication interface 503 are implemented independently, the communication interface 503, the memory 501, and the processor 502 can be interconnected through a bus and communicate with each other. The bus can be an ISA (Industry Standard Architecture) bus, a PCI (Peripheral Component Interconnect) bus, an EISA (Extended Industry Standard Architecture) bus, or the like. The bus can be divided into an address bus, a data bus, a control bus, etc. For ease of representation, Figure 5 it is represented by only a thick line in Figure 5 , but this does not mean that there is only one bus or one type of bus.

[0103] Optionally, in a specific implementation, if the memory 501, the processor 502, and the communication interface 503 are integrated on a single chip, the memory 501, the processor 502, and the communication interface 503 can communicate with each other through an internal interface.

[0104] The processor 502 may be a CPU (Central Processing Unit), or an ASIC (Application Specific Integrated Circuit), or one or more integrated circuits configured to implement the embodiments of the present invention.

[0105] Embodiments of the present invention also provide a computer-readable storage medium storing a computer program, where the computer program is configured to execute the steps in any of the above embodiments of the central processor power efficiency test method when running.

[0106] In an exemplary embodiment, the above computer-readable storage medium may include, but is not limited to: various media such as a USB flash drive, a read-only memory (ROM), a random access memory, a mobile hard disk, a magnetic disk, or an optical disc that can store a computer program.

[0107] Embodiments of the present invention also provide a computer program product including a computer program that, when executed by a processor, implements the steps in any of the above embodiments of the central processor power efficiency test method.

[0108] An embodiment of the present invention further provides another computer program product, including a non-volatile computer-readable storage medium storing a computer program, and when the computer program is executed by a processor, the steps in any of the above-described embodiments of the central processor power efficiency test method are implemented.

[0109] Those skilled in the art can further realize that the units and algorithm steps of each example described in combination with the embodiments disclosed herein can be implemented by electronic hardware, computer software, or a combination of the two. To clearly illustrate the interchangeability of hardware and software, the composition and steps of each example have been generally described according to functions in the above description. Whether these functions are executed in a hardware or software manner depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered to exceed the scope of the present invention.

[0110] The above has introduced in detail a central processor power efficiency test method provided by the present invention. Specific examples are used herein to elaborate on the principle and implementation manner of the present invention. The description of the above embodiments is only used to help understand the method and its core idea of the present invention. It should be noted that for those of ordinary skill in the art in the technical field, without departing from the principle of the present invention, several improvements and modifications can be made to the present invention, and these improvements and modifications also fall within the protection scope of the claims of the present invention.

Claims

1. A method for testing the power efficiency of a central processing unit, characterized in that, including the following steps: judging whether a data synchronization acquisition signal is detected; if the data synchronization acquisition signal is detected, generating multiple test loads and multiple temperature test scenarios, and traversing all power states of the central processing unit based on a preset traversal strategy according to the multiple test loads and the multiple temperature test scenarios, and collecting the central processing unit load change data, power supply data, and temperature data during the traversal process; encapsulating the central processing unit load change data, the power supply data, and the temperature data to obtain power efficiency test data, and obtaining a central processing unit power efficiency test result according to the power efficiency test data.

2. The central processor power efficiency test method according to claim 1, wherein, The traversing all power states of the central processing unit based on a preset traversal strategy according to the multiple test loads and the multiple temperature test scenarios includes: determining a combined test order of performance states and power-saving states based on the preset traversal strategy; traversing all power states of the central processing unit based on the multiple temperature test scenarios according to the combined test order and / or preset periodic load mutation trigger state switching boundary conditions.

3. The central processor power efficiency testing method according to claim 1 or 2, wherein After traversing all power states of the central processing unit based on a preset traversal strategy according to the multiple test loads and the multiple temperature test scenarios, it further includes: judging whether the test result meets a preset coverage requirement; if the test result does not meet the preset coverage requirement, identifying untriggered state combinations, dynamically adjusting the load parameters of the untriggered state combinations based on a preset load parameter adjustment strategy, and performing tests according to the adjusted state combinations.

4. The central processor power efficiency testing method according to claim 1, wherein The generating multiple test loads includes: determining a load scenario to be simulated; generating the multiple test loads based on a preset Stress-NG strategy according to the load scenario to be simulated.

5. The central processor power efficiency test method according to claim 4, wherein The load scenario to be simulated includes a first load scenario, a second load scenario, and a third load scenario, where the first load scenario is determined by a first load range; the second load scenario is determined by a second load range, and the minimum load of the second load range is greater than the maximum load of the first load range; the third load scenario is determined by a third load range, and the minimum load of the third load range is greater than the maximum load of the second load range.

6. The central processor power efficiency test method according to claim 1, characterized in that The time stamps among the central processing unit load change data, the power supply data, and the temperature data are less than a preset time stamp.

7. The central processor power efficiency test method according to claim 6, wherein The central processing unit load change data includes at least one of the residence time in the power-saving state, the frequency change in the performance state, the number of state switches, and the delay time.

8. The central processor power efficiency testing method according to claim 1, wherein After judging whether the data synchronization acquisition signal is detected, it further includes: if the data synchronization acquisition signal is not detected, maintaining the server platform in a preset working mode.

9. The central processor power efficiency testing method according to claim 1, wherein Before judging whether the data synchronization acquisition signal is detected, it further includes: judging whether there is a central processing unit power efficiency test requirement; if there is the central processing unit power efficiency test requirement, controlling the server platform to enter a preset working mode and performing a reset operation on the server platform.

10. The central processor power efficiency testing method according to claim 1, wherein After obtaining the central processing unit (CPU) power efficiency test result based on the power efficiency test data, it further includes: Optimizing the energy efficiency of the data center based on the CPU power efficiency test result.

11. The central processor power efficiency testing method according to claim 1, wherein After obtaining the CPU power efficiency test result based on the power efficiency test data, it further includes: Analyzing the energy consumption of the mobile device based on the CPU power efficiency test result.

12. The central processor power efficiency testing method according to claim 1, wherein After obtaining the CPU power efficiency test result based on the power efficiency test data, it further includes: Researching the power management of the RISC-V architecture based on the CPU power efficiency test result.

13. An electronic device, characterized in that, It includes: A memory for storing a computer program; A processor for implementing the steps of the CPU power efficiency test method according to any one of claims 1 to 12 when executing the computer program.

14. A computer-readable storage medium, characterized in that, A computer program is stored in the computer-readable storage medium, wherein the computer program implements the steps of the CPU power efficiency test method according to any one of claims 1 to 12 when executed by a processor.

15. A computer program product, comprising a computer program, characterized in that, The computer program implements the steps of the CPU power efficiency test method according to any one of claims 1 to 12 when executed by a processor.

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