Semiconductor packaging structure and manufacturing method thereof
By adopting a double ball grid array design in the semiconductor package, the adhesion of the second ball planting ball planting in the first ball planting gap is used to form a redistributed conductive line, which solves the problems of ball grid array cracks and line detours, and improves the quality and life of the package.
Patent Information
- Application Number
- CN202410080169.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-01-19
- Publication Date
- 2025-07-22
- Estimated Expiration
- Not applicable · inactive patent
AI Technical Summary
The ball grid arrays in semiconductor packages are prone to cracks during thermal cycle testing or production, resulting in the short life cycle of the chip product. At the same time, the line detour problem in the connecting line redistribution layer affects signal delay.
A double ball grid array design is adopted, wherein the first ball grid array is used for signal connection, and the implanted balls of the second ball grid array are arranged in the transverse gap between the first ball grid and adhered by a reflow step to form a redistributed conductive circuit to enhance the cured adhesion range of the ball grid and reduce the circuit bend.
It effectively improves the problem of ball planting cracks, extends the number of thermal cycle tests and product life cycle of semiconductor packaging, and reduces the signal delay of connecting lines to betrayed.