Data processing method and device

Abstract

The embodiment of the invention provides a data processing method. The method can be applied to a first communication device. A first communication device may acquire a first FEC codeword transmitted by a second communication device. The first communication device does not decode the first FEC codeword according to a traditional FEC decoding mode, but decodes the first FEC codeword according to a first distribution relation. Wherein the first distribution relation is used for indicating the distribution relation between the first error correction capability and the first error detection capability for processing the first FEC code word. The first error correction capability indicates that the maximum error symbol number in the cyclic code codeword can be corrected, and the first error detection capability indicates that the maximum error symbol number in the cyclic code codeword can be detected. In other words, in the embodiment of the invention, the error correction capability and the error detection capability for decoding the cyclic code word can be flexibly allocated, so that the performance provided by the FEC technology can meet requirements.

Description

Technical Field

[0001] This application relates to the field of communications, and in particular, to a data processing method and apparatus. Background Art

[0002] With the development of information technologies such as cloud computing, big data, artificial intelligence, and the Internet of Things, more and more data is transmitted in Ethernet. Due to some non-ideal characteristics of the transmission channel, such as transmission loss, crosstalk, and noise, the signal is distorted after passing through the channel, resulting in bit errors. Especially for high-speed links, the signal is severely distorted after being transmitted through the channel, resulting in a high bit error rate.

[0003] Forward error correction (FEC) is an important technology for ensuring the correct transmission of information and improving the bit error performance of the communication link. FEC refers to the process of pre-encoding a signal according to a certain algorithm before it is sent into the transmission channel, adding a certain number of redundant bits with the characteristics of the signal itself, and decoding the received signal according to the corresponding algorithm at the receiving end, so as to realize the error control technology of error detection and correction of data.

[0004] The performance of the current FEC technology cannot meet the requirements. Therefore, there is an urgent need for a solution to solve the above problems. Summary of the Invention

[0005] The embodiments of this application provide a data processing method, which can improve the performance provided by FEC.

[0006] In a first aspect, the embodiments of this application provide a data processing method, which can be applied to a first communication device. The first communication device can obtain a first FEC codeword sent by a second communication device. Instead of decoding the first FEC codeword in the traditional FEC decoding manner, the first communication device decodes the first FEC codeword according to a first allocation relationship. The first allocation relationship is used to indicate the allocation relationship between the first error correction ability and the first error detection ability for processing the first FEC codeword. The first error correction ability indicates the maximum number of error symbols that can be corrected in the cyclic codeword, and the first error detection ability indicates the maximum number of error symbols that can be detected in the cyclic codeword. In other words, in the embodiments of this application, the error correction ability and the error detection ability for decoding the cyclic codeword can be flexibly allocated, so that the performance provided by the FEC technology can meet the requirements.

[0007] In one possible implementation, in order to ensure the error detection performance of the communication device, the first error correction capability may be less than the first error detection capability. In this case, the first communication device can detect a maximum number of erroneous symbols, thereby improving the error detection performance of the first communication device. Accordingly, the Ethernet standard requirements for MTTFPA can be more easily met.

[0008] In a possible implementation, considering that in some scenarios, the traditional FEC decoding method is used, its error correction performance is redundant, but the error detection performance cannot meet the Ethernet standard for the mean time to false packet acceptance (MTTFPA) requirement. Therefore, in order to make the error detection performance provided by FEC meet the Ethernet standard for MTTFPA requirements as much as possible, the redundant error correction capability can be reduced on the basis of the traditional FEC decoding method to improve the error detection capability. Therefore, in one example, the first error correction capability can be less than the first error detection capability.

[0009] In a possible implementation, the first allocation relationship may be determined according to the link quality between the first communication device and the second communication device. That is, the first communication device may dynamically adjust the allocation relationship between the error correction capability and the error detection capability for processing a specific type of cyclic code codeword according to the link quality, thereby obtaining the first allocation relationship, so that when decoding the aforementioned specific type of cyclic code codeword based on the first allocation relationship, the obtained link quality meets the link quality requirement.

[0010] In a possible implementation, considering that the link bit error rate and the number of data frame retransmissions can reflect the quality of the link, the link quality may include the link bit error rate and / or the number of data frame retransmissions. Accordingly, the link quality satisfies the link quality requirement, which may be that the link bit error rate satisfies the bit error rate requirement and / or the number of data frame retransmissions satisfies the number of retransmissions requirement.

[0011] In a possible implementation, if the first allocation relationship meets the link quality requirement, that is, when decoding the cyclic code word of the foregoing specific type based on the first allocation relationship, the link quality between the first communication device and the second communication device meets the link quality requirement. Then, in order to further improve the error correction performance and make the error detection performance provided by the FEC meet the requirements of the Ethernet standard for MTTFPA as much as possible, the first error correction capability in the first allocation relationship can be further reduced to increase the first error detection capability in the first allocation relationship, thereby obtaining a second allocation relationship for subsequent decoding of the cyclic code word of the foregoing specific type based on the second allocation relationship. Since the first error correction capability is reduced, when processing the cyclic code word of the foregoing specific type based on the second allocation relationship, the link quality between the first communication device and the second communication device will decrease. In the embodiments of the present application, the first error correction capability is not reduced without limit, but it can be controlled that after reducing the first error correction capability, the second allocation relationship can still meet the link quality requirement.

[0012] In a possible implementation, when the first communication device decodes the first FEC code word according to the first allocation relationship, in specific implementation, the first FEC code word can be first error-corrected according to the first error correction capability to obtain a second FEC code word; then, the second FEC code word is error-detected according to the second error detection capability, and the second error detection capability is equal to the difference between the maximum error correction capability and the first error correction capability.

[0013] In a possible implementation, let P represent the second error detection capability, that is, the second error detection capability is P. Then, when "error-detecting the second FEC code word according to the second error detection capability" is specifically implemented, 2*P syndromes can be calculated according to the second FEC code word. Further, based on the 2*P syndromes, it is determined whether there is an error in the second FEC code word. Specifically, if the 2*P syndromes are all 0, it can be determined that the second FEC code word does not include an error code word; if the 2*P syndromes are not all 0, it can be determined that the second FEC code word includes an error code word.

[0014] In a possible implementation, considering that the current Reed-Solomon (RS) code is a commonly used coding method in FEC, the first FEC code word can be an RS code.

[0015] In a possible implementation, the sum of the first error correction capability and the first error detection capability is equal to dmin - 1, where dmin is the minimum Hamming distance between RS codes. In other words, the sum of the error correction capability and the error detection capability provided by the RS code is a fixed value. Therefore, if the error correction capability is reduced, the error detection capability can be correspondingly improved.

[0016] In a possible implementation, if the first FEC codeword is RS(128, 120), the minimum Hamming distance of RS(128, 120) is 9. Therefore, the sum of the first error correction capability and the first error detection capability is 8. Thus: In one example, the first error correction capability may be 1 and the first error detection capability may be 7; in another example, the first error correction capability may be 2 and the first error detection capability may be 6; in yet another example, the first error correction capability may be 3 and the first error detection capability may be 5; in another example, both the first error correction capability and the first error detection capability may be 4.

[0017] In a second aspect, an embodiment of the present application provides a data processing apparatus, which is applied to a first communication apparatus. The first communication apparatus includes a receiving unit and a processing unit; the receiving unit is configured to obtain a first forward error correction (FEC) codeword sent by a second communication apparatus; the processing unit is configured to decode the first FEC codeword according to a first allocation relationship, where the first allocation relationship indicates an allocation relationship between a first error correction capability and a first error detection capability for processing the first FEC codeword, the first error correction capability indicates the maximum number of error symbols that can be corrected in a cyclic codeword, and the first error detection capability indicates the maximum number of error symbols that can be detected in a cyclic codeword.

[0018] In a possible implementation, the first error correction capability is less than the first error detection capability.

[0019] In a possible implementation, the first allocation relationship is determined according to the link quality between the first communication apparatus and the second communication apparatus.

[0020] In a possible implementation, the first allocation relationship meets the link quality requirement, and the processing unit is further configured to: reduce the first error correction capability in the first allocation relationship and increase the first error detection capability in the first allocation relationship to obtain a second allocation relationship, where the second allocation relationship meets the link quality requirement.

[0021] In a possible implementation, the link quality includes: link error rate, and / or, the number of data frame retransmissions.

[0022] In a possible implementation, the processing unit is configured to: correct the first FEC codeword according to the first error correction capability to obtain a second FEC codeword; detect the second FEC codeword according to a second error detection capability, where the second error detection capability is equal to the difference between the maximum error correction capability and the first error correction capability.

[0023] In a possible implementation manner, the error detection of the second FEC codeword according to the second error detection capability includes: calculating 2*P syndromes according to the second FEC codeword, where P corresponds to the second error detection capability; if all of the 2*P syndromes are 0, determining that the second FEC codeword does not include an error codeword; or, if not all of the 2*P syndromes are 0, determining that the second FEC codeword includes an error codeword.

[0024] In a possible implementation manner, the first FEC codeword is: a Reed - Solomon (RS) code.

[0025] In a possible implementation manner, the sum of the first error correction capability and the first error detection capability is equal to dmin - 1, where dmin is the minimum Hamming distance between RS codes.

[0026] In a possible implementation manner, if the first FEC codeword is RS(128, 120), then: the first error correction capability is 1, and the first error detection capability is 7; or, the first error correction capability is 2, and the first error detection capability is 6; or, the first error correction capability is 3, and the first error detection capability is 5; or, the first error correction capability is 4, and the first error detection capability is 4.

[0027] In a third aspect, an embodiment of the present application provides a device. The device includes a processor and a memory. The memory is used to store instructions or computer programs. The processor is used to execute the instructions or computer programs in the memory and execute the methods described in the above first aspect and any one of the above first aspects.

[0028] In a fourth aspect, an embodiment of the present application provides an optical module, including an interface circuit and a processing circuit. The interface circuit is used to receive and / or transmit data, and the processing circuit is used to perform data processing. In a specific example, the interface circuit is used to obtain a first forward error correction (FEC) codeword sent by a second communication device, and the processing circuit is used to decode the first FEC codeword according to a first allocation relationship. The first allocation relationship indicates the allocation relationship between the first error correction capability and the first error detection capability for processing the first FEC codeword. The first error correction capability indicates the maximum number of error symbols that can be corrected in a cyclic codeword, and the first error detection capability indicates the maximum number of error symbols that can be detected in a cyclic codeword.

[0029] Fifth aspect, an embodiment of the present application provides a physical layer (PHY) chip, where the PHY chip includes an interface circuit and a processing circuit. The interface circuit is configured to receive and / or transmit data, and the processing circuit is configured to perform data processing. In a specific example, the interface circuit is configured to obtain a first forward error correction (FEC) codeword sent by a second communication device, and the processing circuit is configured to decode the first FEC codeword according to a first allocation relationship, where the first allocation relationship indicates an allocation relationship between a first error correction ability and a first error detection ability for processing the first FEC codeword. The first error correction ability indicates the maximum number of error symbols that can be corrected in a cyclic codeword, and the first error detection ability indicates the maximum number of error symbols that can be detected in a cyclic codeword.

[0030] Sixth aspect, an embodiment of the present application provides a computer-readable storage medium, including instructions or a computer program, which, when running on a computer, causes the computer to execute the method described in the above first aspect and any one of the above first aspects.

[0031] Seventh aspect, an embodiment of the present application provides a computer program product including instructions or a computer program, which, when running on a computer, causes the computer to execute the method described in the above first aspect and any one of the above first aspects. Description of the Drawings

[0032] To more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, the drawings described below are only some embodiments recorded in the present application. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0033] Figure 1a Shows a schematic flowchart of cyclic code decoding in the prior art;

[0034] Figure 1b Is a schematic diagram of codeword error correction provided by an embodiment of the present application;

[0035] Figure 1c Is a schematic diagram of decoding effect provided by an embodiment of the present application;

[0036] Figure 2 Is a schematic flowchart of a data processing method provided by an embodiment of the present application;

[0037] Figure 3 Is a schematic flowchart of decoding provided by an embodiment of the present application;

[0038] Figure 4Schematic diagram of another decoding process provided by an embodiment of the present application;

[0039] Figure 5 Schematic diagram of the structure of a data processing device provided by an embodiment of the present application;

[0040] Figure 6 Schematic diagram of the structure of an optical module provided by an embodiment of the present application;

[0041] Figure 7 Schematic diagram of the structure of a PHY chip provided by an embodiment of the present application;

[0042] Figure 8 Schematic diagram of the structure of a device provided by an embodiment of the present application. Detailed implementation manners

[0043] An embodiment of the present application provides a data processing method, which can improve the performance provided by FEC.

[0044] Currently, there are many encoding algorithms supported by FEC technology. Among them, cyclic codes are a type of code pattern with error correction and error detection capabilities that have been relatively deeply studied, have relatively mature theories, and have relatively wide application scenarios. Cyclic codes can include RS codes, cyclic redundancy check (CRC) codes, BCH (Bose-Chaudhuri-Hocquenghem) codes, and Fire codes, etc.

[0045] FEC can be used for error correction or error detection. However, for a certain fixed code pattern, the current FEC has fixed error correction performance and error detection performance, and generally, the error correction performance and error detection performance are the same. Among them, the error correction performance refers to the maximum number of error symbols that can be corrected in a cyclic code word, and the error detection performance refers to the maximum number of error symbols that can be detected in a cyclic code word. For example, for a certain code pattern, its error correction performance and error detection performance are both a. This means that when there are at most a symbols in the code word that are in error, the symbols in error can be corrected to the correct symbols, and when there are at most a symbols in the code word that are in error, it can also be detected that the code word has an error. In this scenario: As an example, detecting that the code word has an error can be outputting an error detection result indicating that the code word is in error, and this error detection result does not necessarily indicate the specific code word in error in the code word. As another example, the detection result can also locate the specific code word in error. This is because the error detection performance and error correction performance are the same, and error correction must determine the specific code word in error.

[0046] Precisely because the error correction performance and error detection performance of a certain fixed code pattern are fixed, the performance provided by the current FEC cannot meet the requirements. As a specific example, the error detection performance provided by the current FEC technology cannot meet the requirements of the Ethernet standard for MTTFPA. Among them, MTTFPA is a key parameter of the Ethernet standard, and the specific requirement of the Ethernet standard for MTTFPA is: only one incorrect frame reception can occur within the life of the universe (about 13.8 billion years). That is, within the life of the universe, it is required that the communication device can misdetect at most one incorrect frame as a correct data frame.

[0047] In order to enable the performance provided by FEC to meet the requirements, the embodiments of the present application provide a data processing method and apparatus.

[0048] Before introducing the data processing method and apparatus provided by the embodiments of the present application, the relevant content of FEC and cyclic codes will be introduced first.

[0049] I. Related Terms

[0050] 1. Symbol of a cyclic code word: The basic unit that makes up a cyclic code word and is also the basic unit for RS code encoding and decoding calculations. A symbol can include one or more bits. Among them, the number of bits included in a symbol can be represented by the letter m. When m = 1, the symbol has the same meaning as a bit.

[0051] 2. (N, K, T, m) are the four parameters of a cyclic code, where:

[0052] N represents the length of a cyclic code word;

[0053] K represents the length of the valid symbols (also called payload) included in a cyclic code;

[0054] T represents the maximum error correction ability of a code word, that is, a code word can correct at most T symbol errors, and T = (N - K) / 2;

[0055] m represents the number of bits included in 1 symbol, and the value is a positive integer greater than or equal to 1. For BCH, CRC, Fire Code, etc., m usually takes the value of 1, and for RS codes, m usually takes a value greater than 1.

[0056] 3. RS(N, K): The representation of an RS code. RS(N, K) represents an RS code word with a code word length of N and an information length of K.

[0057] 4. Length of an RS code word: The number of symbols included in an RS code word, usually represented by the letter N.

[0058] 5. Information length of RS codeword: The number of valid symbols contained in an RS codeword, usually represented by the letter K.

[0059] 6. Redundancy length of RS codeword: The number of redundant symbols contained in an RS codeword, usually represented by the letter R, and R = N - K.

[0060] 7. Hamming distance (HD): It represents the number of different characters at the corresponding positions of two strings of the same length. Among them, for cyclic codes, once their encoding method is determined, the minimum Hamming distance between the encoded codewords is determined. Specifically, the minimum Hamming distance dmin of the cyclic code (N, K, T, m) is N - K + 1. For example, for RS(128, 120), its minimum Hamming distance is 9.

[0061] II. Encoding and Decoding Principles of Cyclic Codes

[0062] The payload part M(x) of a cyclic code with length K can be represented by the polynomial shown in formula (1) as:

[0063] M(x) = m K-1 ·x K-1 +m K-2 ·x K-2 +…+m1·x + m0 Formula (1)

[0064] The generator polynomial g(x) of the cyclic code can be as shown in formula (2):

[0065] g(x) = g N-K ·x N-K +g N-K-1 ·x N-K-1 +…+g1·x + g0 Formula (2)

[0066] The cyclic code encoding process is to divide M(x) by g(x) to obtain the remainder P(x). A codeword polynomial C(x) of a cyclic code can be composed of M(x) and P(x), as shown in formula (3):

[0067] C(x) = x N-K ·M(x) + p(x) Formula (3)

[0068] Among them, x N-K ·M(x) satisfies the following formula (4):

[0069] x N-K ·M(x) = q(x)·g(x) + p(x) Formula (4)

[0070] Substituting formula (4) into formula (3) gives the following formula (5):

[0071] C(x) = q(x)·g(x), Equation (5)

[0072] According to Equation (5), the roots of the generating polynomial g(x) are also the roots of the codeword polynomial C(x).

[0073] The polynomial r(x) received at the cyclic code decoder can be expressed by Equation (6):

[0074] r(x) = C(x) + e(x) = r0 + r1x + … + r n-1 x n-1 Equation (6)

[0075] In Equation (6): e(x) represents the error polynomial caused by channel transmission, which can be expressed by the following Equation (7):

[0076]

[0077] If there is no error in the transmission of the cyclic codeword, then e(x) is 0, and the decoder receives a correct codeword; if there is an error in the transmission of the cyclic codeword, then e(x) is not 0. α is a primitive element in GF(2 m ), α b+i ∈ GF(2 m ), and i = 0, 1, …, 2t - 1 are the roots of the generating polynomial. Among them: GF(2 m ) is also known as the Galois field, discovered by the French mathematician Evariste Galois. It has multiplication, division, addition, and subtraction operations, and these operations follow certain rules and are closed, that is, the operation results between field elements are still within the field.

[0078] As described above, the roots of the generating polynomial are also the roots of the codeword polynomial. Therefore, the following Equation (8) holds.

[0079] r(α b+i ) = c(α b+i ), i = 0, 1, …, 2t - 1, Equation (8)

[0080] The purpose of decoding is to determine the error positions and the corresponding error values, and then add the obtained error polynomial e(x) to the received polynomial r(x) to obtain the correct codeword polynomial.

[0081] See Figure 1a , Figure 1a which shows a schematic diagram of the cyclic code decoding process in the traditional technology. As Figure 1a shown, the decoding process includes the following 4 steps:

[0082] 1. Calculate 2*T syndromes to determine whether there are errors, where T is the maximum error correction capability.

[0083] 2. Solve the key equation according to the 2*T syndromes to determine the error location polynomial and the error value polynomial.

[0084] In one example, the RiBM (Reformulated inversionless Berlekamap-Massey) algorithm can be used to solve the key equation.

[0085] 3. Determine the positions of the symbols with errors in the cyclic codeword according to the error location polynomial.

[0086] In one example, the Chien search algorithm can be used to process the error location polynomial to determine the positions of the symbols with errors in the cyclic codeword.

[0087] 4. Determine the error values corresponding to the error symbols at the aforementioned positions according to the error value polynomial, and correct the cyclic codeword based on the error values.

[0088] In one example, the Forney algorithm can be used to process the error value polynomial to determine the aforementioned error values.

[0089] For a cyclic code (N, K, T, m), if it only works in the error detection mode, its error detection performance can reach dmin - 1 symbols. For example, for RS(128, 120), if it only works in the error detection mode, its error detection performance can reach 8 symbols.

[0090] In the traditional technology, for the (N, K, T, m) cyclic code, both the error correction performance and the error detection performance are fixed. Specifically, N - K redundant symbols are all used for the error correction function, that is, the error correction capability can reach T symbols, and T is the maximum error correction capability of the (N, K, T, m) cyclic code. Correspondingly, its error detection capability is also T symbols. Using this method can effectively reduce the bit error rate of data transmitted through the channel. For example, before correcting the received codeword, the bit error rate (BER) is 1e - 5, then after using the aforementioned error correction capability, the bit error rate can be reduced to 4.2e - 15.

[0091] However, in the current method where all N-K redundant symbols are used for error correction, the performance provided often fails to meet the requirements. For example, its error correction performance is redundant, while its error detection performance cannot meet the requirements of the Ethernet standard for MTTFPA. For example, in some scenarios, it is required that the bit error rate reaches le-9 or le-10, and there is no need to reach the aforementioned 4.2e-15.

[0092] The inventors of the present application found that for a cyclic code (N, K, T, m), its generating polynomial can be expressed not only in the form of formula (2), but also in the following formula (9).

[0093] g(x) = (x - α 0 )·(x - α 1 )·(x - α 2 )…·(x - α N-K-1 ) Formula (9)

[0094] Combining formula (9) and formula (6), it can be known that the codeword polynomial C(x) satisfies the following formula (10):

[0095] C(α i ) = 0, i = 0, 1, 2, … N-k-1 Formula (10)

[0096] According to formula (10), C(x) can also be regarded as the following codeword:

[0097] 1. C(x) is a codeword polynomial with as the generating polynomial, and its error correction ability reaches 1 symbol;

[0098] 2. C(x) is a codeword polynomial with as the generating polynomial, and its error correction ability reaches 2 symbols;

[0099] And so on:

[0100] 3. C(x) is a codeword polynomial with as the generating polynomial, and its error correction ability reaches symbols.

[0101] Regardless of which of the above situations C(x) is in, its error correction ability is T. Therefore, for a certain cyclic codeword, if T+1 symbols are in error, the codeword may be corrected to another codeword, that is, a codeword miscorrection occurs. As Figure 1b shown, Figure 1b is a schematic diagram of a codeword miscorrection provided by an embodiment of the present application.

[0102] As Figure 1b described, the codeword C w1During the transmission process, e errors occur and the codeword becomes R. If the Hamming distance (HD) between the codeword R and the codeword C w2 is less than or equal to T, it may be mis-corrected to the codeword C w2 . Since the following formulas (11) to (14) are satisfied, formula (15) can be obtained.

[0103]

[0104]

[0105]

[0106]

[0107] HD(C w1 , C w2 ) <= e + T Formula (15)

[0108] Where:

[0109] HD(a, b) represents the Hamming distance between the codewords a and b. For example, HD(C w1 , C w2 ) represents the Hamming distance between the codeword C w1 and the codeword C w2 ;

[0110] represents the exclusive OR calculation of the codewords a and b. For example, represents the exclusive OR calculation of the codeword C w1 and the codeword C w2 .

[0111] According to formula (15), if mis-correction occurs, the minimum number of errors caused is at least e + T.

[0112] Therefore, for the cyclic code (N, K, T, m), as long as e + T is less than its dmin (i.e., N - K + 1), it can definitely be successfully detected without mis-correction. That is: the sum of the error detection ability and the error correction ability can reach dmin - 1. Therefore, for the cyclic code (N, K, T, m), if the error correction ability is t1 (t1 <= T), its error detection ability can reach dmin - 1 - t1 symbols. In other words, the error correction ability and the error detection ability of the cyclic code do not have to be fixed, but can be allocated. For the cyclic code (N, K, T, m), it can achieve the ability of "correct t1 and detect (dmin - 1 - t1)". The so-called "correct t1 and detect (dmin - 1 - t1)" means that the error correction ability is t1 and the error detection ability is (dmin - 1 - t1).

[0113] Taking RS(128, 120) as an example, its dmin = 9, and it can achieve the capabilities of "correcting 1 and detecting 7", "correcting 2 and detecting 6", and "correcting 3 and detecting 5".

[0114] It can be understood in combination with Figure 1c as follows. Figure 1c This is a schematic diagram of the decoding effect provided by the embodiment of the present application.

[0115] As Figure 1c shown in the content (a), for the codeword C w3 in terms of, if traditional FEC decoding is used, its decoding ability and error correction ability are both 4, that is: when the codeword C w3 is programmed into the codeword Q after transmission, if the Hamming distance between the codeword Q and the codeword C w3 is less than or equal to 4, it can be corrected. However, when the decoding mode is "correcting 1 and detecting 7", as long as the Hamming distance between the codeword Q and the codeword C w3 is less than or equal to 7, it can be detected that the codeword Q is an incorrect codeword. Of course, when the Hamming distance between the codeword Q and the codeword C w3 is greater than 1, the codeword Q cannot be corrected to C w3 .

[0116] Similarly, as Figure 1c shown in the content (b), when the decoding mode is "correcting 2 and detecting 6", as long as the Hamming distance between the codeword Q and the codeword C w3 is less than or equal to 6, it can be detected that the codeword Q is an incorrect codeword. Of course, when the Hamming distance between the codeword Q and the codeword C w3 is greater than 2, the codeword Q cannot be corrected to C w3 .

[0117] Similarly, as Figure 1c shown in the content (c), when the decoding mode is "correcting 3 and detecting 5", as long as the Hamming distance between the codeword Q and the codeword C w3 is less than or equal to 5, it can be detected that the codeword Q is an incorrect codeword. Of course, when the Hamming distance between the codeword Q and the codeword C w3 is greater than 3, the codeword Q cannot be corrected to C w3 .

[0118] In view of this, the embodiment of the present application provides a data processing method. For a cyclic code with a certain code type, its error correction ability and error detection ability can be flexibly allocated, so that the performance provided by the cyclic code can meet the requirements.

[0119] Next, in combination with Figure 2 , the data processing method provided by the embodiment of the present application will be introduced. Figure 2A flowchart of a data processing method provided by an embodiment of this application.

[0120] Figure 2 The method shown can be applied to a first communication device. The communication devices mentioned in the embodiments of this application (such as the first communication device and the second communication device) can be network devices such as switches and routers, or can be a part of the components on the network device, such as a single board or a line card on the network device, or can be a functional module on the network device, or can be a chip for implementing the method of this application (such as a physical layer (PHY) chip), or can also be a server or an optical module, etc. The embodiments of this application do not make specific limitations. The communication devices can be directly connected through, for example, but not limited to, an Ethernet cable or an optical cable.

[0121] Figure 2 The method shown can include the following S101 - S102.

[0122] S101: The first communication device obtains a first FEC codeword sent by the second communication device.

[0123] In the embodiments of this application, the second communication device can send the first FEC codeword to the first communication device. Correspondingly, the first communication device can receive the first FEC codeword sent by the second communication device. This first FEC codeword can be a cyclic codeword of a specific type. For example, the first FEC codeword can be an RS codeword. Another example is that the first FEC codeword can be a CRC codeword, a BCH codeword, or a fire codeword, etc. In a specific example, when the first FEC codeword is an RS codeword, the first FEC codeword can be specifically RS(128, 120), that is: the first FEC codeword includes a total of 128 symbols, of which 120 symbols are information symbols and the other 8 symbols are redundant symbols.

[0124] In an example, the first communication device can be a network device acting as a receiving end. Correspondingly, the second communication device can be a network device acting as a sending end.

[0125] In another example, the first communication device and the second communication device can belong to the same network device. As a specific example, the first communication device can be an optical module on the network device, and the second communication device can be a PHY chip on the network device. As another specific example, the first communication device and the second communication device can be two different PHY chips on the network device. For example, the first communication device is the first PHY chip on the network device, and the second communication device is the second PHY chip on the network device.

[0126] S102: The first communication device decodes the first FEC codeword according to a first allocation relationship, where the first allocation relationship indicates the allocation relationship between the first error correction capability and the first error detection capability for processing the first FEC codeword. The first error correction capability indicates the maximum number of error symbols that can be corrected in a cyclic codeword, and the first error detection capability indicates the maximum number of error symbols that can be detected in a cyclic codeword.

[0127] After the first communication device obtains the first FEC codeword, instead of decoding the first FEC codeword in the traditional FEC decoding manner, it decodes the first FEC codeword according to the flexibly allocated first allocation relationship. Taking the first FEC codeword as RS(128, 120) as an example, for RS(128, 120), its corresponding maximum error correction capability is 4. Correspondingly, its error detection capability is also 4. That is, it can correct at most 4 error symbols, and when the number of error symbols in the codeword is less than or equal to 4, it can detect that the codeword has an error. The first communication device does not decode the first FEC codeword with the maximum decoding capability, but decodes the first FEC codeword based on the flexibly allocated first allocation relationship.

[0128] Among them, the first allocation relationship is used to indicate the allocation relationship between the first error correction capability and the first error detection capability for processing the first FEC codeword. The first error correction capability indicates the maximum number of error symbols that can be corrected in a cyclic codeword. For example, the first error correction capability is a first quantity, indicating that when the number of error symbols in the cyclic codeword is less than or equal to the first quantity, the error symbols can be corrected to correct symbols. The first error detection capability indicates the maximum number of error symbols that can be detected in a cyclic codeword. For example, the first error detection capability is a second quantity, indicating that when the number of error symbols in the cyclic codeword is less than or equal to the second quantity, it can be detected that the cyclic codeword has an error. In other words, in the embodiments of the present application, the error correction capability and the error detection capability for decoding a cyclic codeword can be flexibly allocated, so that the performance provided by the FEC technology can meet the requirements.

[0129] The embodiment of the present application does not specifically limit the first error correction capability and the first error detection capability. As can be seen from the previous description of the cyclic code, the traditional FEC decoding method has the same corresponding error correction capability and error detection capability, and the error correction capability is the maximum error correction capability. In the embodiment of the present application, considering that in some scenarios, the traditional FEC decoding method is adopted, its error correction performance is redundant, and the error detection performance cannot meet the requirements of the Ethernet standard for MTTFPA. Therefore, in order to make the error detection performance provided by FEC meet the requirements of the Ethernet standard for MTTFPA as much as possible, the redundant error correction capability can be reduced on the basis of the traditional FEC decoding method. Since the sum of the error correction capability and the error detection capability is equal to dmin-1, reducing the redundant error correction capability can improve the error detection capability. Therefore, in one example, the first error correction capability can be less than the first error detection capability. That is, the aforementioned first number can be less than the aforementioned second number. For example, the first FEC codeword is RS (128, 120), then as described above, the sum of the first number and the second number is equal to 8. Thus: in one example, the first number may be 1 and the second number may be 7; in another example, the first number may be 2 and the second number may be 6; in yet another example, the first number may be 3 and the second number may be 5.

[0130] Of course, the first error correction capability and the first error detection capability may also be the same, for example, the first error correction capability and the first error detection capability are both 4. This embodiment of the present application does not make any specific limitation.

[0131] In one example, the first allocation relationship may be manually specified by a user.

[0132] In another example, the first allocation relationship may also be determined based on the link quality between the first communication device and the second communication device. That is, the first communication device may dynamically adjust the allocation relationship between the error correction capability and the error detection capability for processing a specific type of cyclic code codeword based on the link quality, thereby obtaining the first allocation relationship, so that when decoding the aforementioned specific type of cyclic code codeword based on the first allocation relationship, the obtained link quality meets the link quality requirement.

[0133] In the embodiments of the present application, the link quality mentioned includes, but is not limited to, any parameter that can reflect the quality of the link. As a specific example, considering that the link error rate and the number of data frame retransmissions can reflect the quality of the link, therefore, the link quality may include the link error rate and / or the number of data frame retransmissions. Correspondingly, that the link quality meets the link quality requirement may be that the link error rate meets the error rate requirement and / or the number of data frame retransmissions meets the retransmission number requirement. For example, that the link quality meets the link quality requirement may be that the link error rate is lower than the error rate threshold, and / or the number of data frame retransmissions is lower than the retransmission number threshold.

[0134] In a specific example, the first allocation relationship may be obtained by adjusting the third allocation relationship. The third allocation relationship indicates the allocation relationship between the second error correction ability and the third error detection ability for processing cyclic code codewords of a specific type. The embodiments of the present application do not specifically limit the second error correction ability and the third error detection ability. In an example, the second error correction ability may be the maximum error correction ability for processing cyclic code codewords of a specific type. Correspondingly, the third error detection ability is equal to the second error correction ability. For example, if the cyclic code codewords of the specific type are RS(128, 120), then both the second error correction ability and the third error detection ability are 4. Of course, the second error correction ability may also be less than the third error detection ability, and the embodiments of the present application do not make specific limitations.

[0135] In an example, if the third allocation relationship meets the link quality requirement, it means that the second error correction ability meets the requirement and even has some redundancy. Therefore, the second error correction ability in the third allocation relationship can be reduced to increase the third error detection ability in the third allocation relationship, thereby obtaining the first allocation relationship. For example, it can be understood in combination with Table 1 below.

[0136] Table 1

[0137]

[0138] As can be seen from Table 1, both the second error correction ability and the third error detection ability of the third allocation relationship are 4 characters. When the third allocation relationship meets the link quality requirement, the second error correction ability is reduced to obtain the first error correction ability. Correspondingly, the third error detection ability is increased to the first error detection ability.

[0139] Regarding the third allocation relationship meeting the link quality requirement, it can be understood that when decoding the cyclic code codewords of the aforementioned specific type based on the third allocation relationship, the link quality between the first communication device and the second communication device meets the link quality requirement.

[0140] In one example, if the first allocation relationship meets the link quality requirements, that is, when decoding the aforementioned specific type of cyclic code codeword based on the first allocation relationship, the link quality between the first communication device and the second communication device meets the link quality requirements, then in order to further improve the error correction performance, so that the error detection performance provided by FEC can meet the requirements of the Ethernet standard for MTTFPA as much as possible, the first error correction capability in the first allocation relationship can be further reduced to increase the first error detection capability in the first allocation relationship, and obtain the second allocation relationship, so as to facilitate the subsequent decoding of the aforementioned specific type of cyclic code codeword based on the second allocation relationship. Among them, the second allocation relationship can indicate the allocation relationship between the third error correction capability and the fourth error detection capability for processing the aforementioned specific type of cyclic code codeword. It is not difficult to understand that since the first error correction capability is reduced, therefore, when the aforementioned specific type of cyclic code codeword is processed based on the second allocation relationship, the link quality between the first communication device and the second communication device will be reduced. In the embodiment of the present application, the first error correction capability is not reduced without limit, but the second allocation relationship can be controlled to still meet the link quality requirements after the first error correction capability is reduced.

[0141] Table 2

[0142]

[0143] In the embodiment of the present application, when S102 is specifically implemented, for example, it may include Figure 3 S1021-S1022 shown. Figure 3 A schematic diagram of a decoding process provided in an embodiment of the present application.

[0144] S1021: The first communication device corrects the first FEC codeword according to the first error correction capability to obtain a second FEC codeword.

[0145] For the convenience of description, the first quantity is represented by t1, that is, the first error correction capability is t1. Then S1021 may include the following steps during specific implementation:

[0146] First, 2*t1 syndromes are calculated according to the first FEC codeword. The syndrome calculation method may be a conventional syndrome calculation method, which will not be described again here.

[0147] Then, the 2*t1 syndromes are used to solve the key equations to determine the error position polynomial and the error value polynomial. In one example, the RiBM algorithm may be used to solve the key equations.

[0148] Further, according to the error location polynomial, determine the positions of the symbols in the first FEC codeword where errors occur. In one example, the Chien search algorithm can be used to process the error location polynomial to determine the positions of the symbols in the first FEC codeword where errors occur. And, according to the error value polynomial, determine the error values corresponding to the error symbols at the aforementioned positions, and correct the first FEC codeword based on the error values to obtain the second FEC codeword. In one example, the Forney algorithm can be used to process the error value polynomial to determine the aforementioned error values.

[0149] Regarding how to solve the key equation using the RiBM algorithm, how to process the error location polynomial using the Chien search algorithm, and how to process the error value polynomial using the Forney algorithm, the traditional processing methods can be followed and will not be elaborated here.

[0150] S1022: The first communication device performs error detection on the second FEC codeword according to the second error detection capability, where the second error detection capability is equal to the difference between the maximum error correction capability and the first error correction capability.

[0151] After obtaining the second FEC codeword, error detection can be further performed on the second FEC codeword based on the second error detection capability. Among them, the second error detection capability is equal to the difference between the maximum error correction capability T and the first error correction capability t1. Since the sum of the first error correction capability and the first error detection capability is equal to twice the maximum error correction capability, the second error detection capability is also equal to half of the difference between the first error detection capability and the first error correction capability.

[0152] For convenience of description, let P represent the second error detection capability. That is, if the second error detection capability is P, then in specific implementation of S1022, 2*P syndromes can be calculated according to the second FEC codeword. Further, based on the 2*P syndromes, it is determined whether there is an error in the second FEC codeword. Specifically, if all of the 2*P syndromes are 0, it can be determined that the second FEC codeword does not include an error codeword; if the 2*P syndromes are not all 0, it can be determined that the second FEC codeword includes an error codeword. In other words, if all of the 2*P syndromes are 0, the obtained error detection result is that the second FEC codeword does not include an error codeword. If the 2*P syndromes are not all 0, the obtained error detection result is that the second FEC codeword includes an error codeword. In other words, the error detection result obtained by executing S1022 can be used to indicate whether the second FEC codeword is in error (i.e., whether it includes an error codeword), but cannot be used to indicate the specific error codeword in the second FEC codeword. In another example, the key equation can be further solved for the 2*P syndromes to determine the error location polynomial to determine the specific error codeword in the second FEC codeword.

[0153] Next, in combination with Figure 4 the decoding flowchart shown, the specific implementation of S102 will be introduced. Figure 4 It is a schematic diagram of another decoding process provided by an embodiment of the present application.

[0154] As Figure 4 shown, the decoding process includes the following 4 steps:

[0155] 1. Calculate 2*t1 syndromes according to the first FEC codeword to determine whether there is an error, where t1 is the first error correction capability.

[0156] 2. Solve the key equation for the 2*t1 syndromes to determine the error location polynomial and the error value polynomial.

[0157] In one example, the RiBM algorithm can be used to solve the key equation.

[0158] 3. Determine the positions of the symbols in error in the first FEC codeword according to the error location polynomial.

[0159] In one example, the Chien search algorithm can be used to process the error location polynomial to determine the positions of the symbols in error in the cyclic codeword.

[0160] 4. Determine the error values corresponding to the error symbols at the foregoing positions according to the error value polynomial, and correct the first FEC codeword based on the error values to obtain the second FEC codeword.

[0161] In one example, the Forney algorithm can be used to process the error value polynomial to determine the aforementioned error value.

[0162] 5. Calculate 2*P syndromes to determine whether there is an error in the second FEC codeword, where 2*P = 2*(T - t1).

[0163] By comparing Figure 4 and Figure 1a it can be seen that compared with the decoding process of the traditional technology, the decoding process of the present application splits the calculation part of the syndrome in the traditional technology into two parts. In the error correction stage, the number of calculated syndromes is reduced (from 2*T to 2*P). Correspondingly, the number of syndromes processed in the error correction stage becomes smaller, and correspondingly, the power consumption of decoding is reduced.

[0164] Based on the data processing method provided in the above method embodiments, the present application embodiments also provide a corresponding data processing device. Refer to Figure 5 This figure is a schematic structural diagram of a data processing device provided by an embodiment of the present application. Figure 5 The data processing device 500 shown can be applied to the first communication device in the above method embodiments to execute the data processing method executed by the first communication device provided in the above method embodiments.

[0165] As Figure 5 shown, the data processing device 500 includes: a receiving unit 501 and a processing unit 502.

[0166] The receiving unit 501 is configured to obtain a first forward error correction (FEC) codeword sent by a second communication device;

[0167] The processing unit 502 is configured to decode the first FEC codeword according to a first allocation relationship, where the first allocation relationship indicates the allocation relationship between the first error correction ability and the first error detection ability for processing the first FEC codeword. The first error correction ability indicates the maximum number of error symbols that can be corrected in a cyclic codeword, and the first error detection ability indicates the maximum number of error symbols that can be detected in a cyclic codeword.

[0168] In a possible implementation, the first error correction ability is less than the first error detection ability.

[0169] In a possible implementation, the first allocation relationship is determined according to the link quality between the first communication device and the second communication device.

[0170] In a possible implementation, the first allocation relationship meets the link quality requirement, and the processing unit 502 is further configured to: reduce the first error correction capability in the first allocation relationship and increase the first error detection capability in the first allocation relationship to obtain a second allocation relationship, where the second allocation relationship meets the link quality requirement.

[0171] In a possible implementation, the link quality includes: link bit error rate, and / or, data frame retransmission times.

[0172] In a possible implementation, the processing unit 502 is configured to: perform error correction on the first FEC codeword according to the first error correction capability to obtain a second FEC codeword; perform error detection on the second FEC codeword according to the second error detection capability, where the second error detection capability is equal to the difference between the maximum error correction capability and the first error correction capability.

[0173] In a possible implementation, the performing error detection on the second FEC codeword according to the second error detection capability includes: calculating 2*P syndromes according to the second FEC codeword, where P corresponds to the second error detection capability; if all of the 2*P syndromes are 0, determining that the second FEC codeword does not include an error codeword; or, if not all of the 2*P syndromes are 0, determining that the second FEC codeword includes an error codeword.

[0174] In a possible implementation, the first FEC codeword is: Reed - Solomon RS code.

[0175] In a possible implementation, the sum of the first error correction capability and the first error detection capability is equal to dmin - 1, where dmin is the minimum Hamming distance between RS codes.

[0176] In a possible implementation, if the first FEC codeword is RS(128, 120), then: the first error correction capability is 1, and the first error detection capability is 7; or, the first error correction capability is 2, and the first error detection capability is 6; or, the first error correction capability is 3, and the first error detection capability is 5; or, the first error correction capability is 4, and the first error detection capability is 4.

[0177] Based on the data processing method provided in the above method embodiments, an optical module is further provided in an embodiment of the present application. Refer to Figure 6 , which is a schematic structural diagram of an optical module provided in an embodiment of the present application. Figure 6 The optical module 600 shown can correspond to the first communication device in the above method embodiments and is configured to execute the data processing method executed by the first communication device provided in the above method embodiments.

[0178] AsFigure 6 As shown, the optical module 600 includes: an interface circuit 601 and a processing circuit 602.

[0179] The interface circuit 601 is used to receive and / or transmit data, and the processing circuit 602 is used to process data.

[0180] In a specific example, the interface circuit 601 is used to obtain a first forward error correction (FEC) codeword sent by a second communication device;

[0181] The processing circuit 602 is used to decode the first FEC codeword according to a first allocation relationship, where the first allocation relationship indicates the allocation relationship between a first error correction ability and a first error detection ability for processing the first FEC codeword. The first error correction ability indicates the maximum number of error symbols that can be corrected in a cyclic codeword, and the first error detection ability indicates the maximum number of error symbols that can be detected in a cyclic codeword.

[0182] For the specific implementation of the interface circuit 601 and the processing circuit 602, reference can be made to the relevant description part of the above method embodiments, and no repeated description will be given here.

[0183] Based on the data processing method provided in the above method embodiments, an embodiment of the present application further provides a PHY chip. Refer to Figure 7 , which is a schematic structural diagram of a PHY chip provided by an embodiment of the present application. Figure 7 The shown PHY chip 700 can correspond to the first communication device in the above method embodiments and is used to execute the data processing method executed by the first communication device provided in the above method embodiments.

[0184] As Figure 7 shown, the PHY chip 700 includes: an interface circuit 701 and a processing circuit 702.

[0185] The interface circuit 701 is used to receive and / or transmit data, and the processing circuit 702 is used to process data.

[0186] In a specific example, the interface circuit 701 is used to obtain a first forward error correction (FEC) codeword sent by a second communication device;

[0187] The processing circuit 702 is used to decode the first FEC codeword according to a first allocation relationship, where the first allocation relationship indicates the allocation relationship between a first error correction ability and a first error detection ability for processing the first FEC codeword. The first error correction ability indicates the maximum number of error symbols that can be corrected in a cyclic codeword, and the first error detection ability indicates the maximum number of error symbols that can be detected in a cyclic codeword.

[0188] For specific implementations of the interface circuit 701 and the processing circuit 702, reference may be made to the relevant description parts of the foregoing method embodiments, and no repeated description will be given here.

[0189] It should be noted that for the data processing device 500, the optical module 600, and the PHY chip 700 mentioned above, their hardware structures can all be the structures as Figure 8 shown, Figure 8 which is a schematic structural diagram of a device provided by an embodiment of the present application.

[0190] Please refer to Figure 8 as shown. The device 800 includes: a processor 810, a communication interface 820, and a memory 830. Among them, the number of processors 810 in the device 800 can be one or more, Figure 8 and one processor is taken as an example here. In the embodiment of the present application, the processor 810, the communication interface 820, and the memory 830 can be connected through a bus system or other means. Among them, Figure 8 connection through the bus system 840 is taken as an example here.

[0191] The processor 810 can be a central processing unit (CPU), an NP, or a combination of a CPU and an NP. The processor 810 can further include a hardware chip. The above-mentioned hardware chip can be an ASIC, a programmable logic device (PLD), or a combination thereof. The above-mentioned PLD can be a complex programmable logic device (CPLD), a field-programmable gate array (FPGA), a generic array logic (GAL), or any combination thereof.

[0192] The memory 830 can include volatile memory, such as random-access memory (RAM); the memory 830 can also include non-volatile memory, such as flash memory, a hard disk drive (HDD), or a solid-state drive (SSD); the memory 830 can also include a combination of the above types of memories. The memory 830 can store, for example, the foregoing first allocation relationship.

[0193] Optionally, the memory 830 stores an operating system and programs, executable modules, or data structures, or subsets or extended sets thereof, where the programs may include various operation instructions for implementing various operations. The operating system may include various system programs for implementing various basic services and processing hardware-based tasks. The processor 810 may read the programs in the memory 830 to implement the data processing method provided by the embodiments of the present application.

[0194] The bus system 840 may be a peripheral component interconnect (PCI) bus, an extended industry standard architecture (EISA) bus, or the like. The bus system 840 may be divided into an address bus, a data bus, a control bus, etc. For ease of representation, Figure 8 only a thick line is used to represent it in the figure, but it does not mean that there is only one bus or one type of bus.

[0195] The embodiments of the present application provide a computer-readable storage medium including instructions or a computer program, which when running on a computer, causes the computer to execute the method described in the above method embodiments.

[0196] The embodiments of the present application provide a computer program product including instructions or a computer program, which when running on a computer, causes the computer to execute the method described in the above method embodiments.

[0197] The terms "first", "second", "third", "fourth", etc. (if any) in the specification, claims, and drawings of the present application are used to distinguish similar objects and do not necessarily describe a specific order or sequence. It should be understood that the data used in this way can be interchanged under appropriate circumstances so that the embodiments described here can be implemented in an order different from that shown or described here. In addition, the terms "include" and "have" and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or device including a series of steps or units does not necessarily have to be limited to those steps or units clearly listed, but may include other steps or units not clearly listed or inherent to these processes, methods, products, or devices.

[0198] Those skilled in the art can clearly understand that for the convenience and brevity of description, the specific working processes of the systems, devices, and units described above can refer to the corresponding processes in the foregoing method embodiments and will not be elaborated here.

[0199] In several embodiments provided in the present application, it should be understood that the disclosed systems, devices, and methods can be implemented in other ways. For example, the device embodiments described above are merely illustrative. For example, the division of units is only a logical service division. In actual implementation, there may be other division methods. For example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the displayed or discussed couplings or direct couplings or communication connections to each other can be through some interfaces, indirect couplings or communication connections of devices or units, and can be in electrical, mechanical, or other forms.

[0200] The units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they can be located in one place or distributed to multiple network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0201] In addition, in each embodiment of the present application, each service unit can be integrated in a processing unit, or each unit can exist physically alone, or two or more units can be integrated in one unit. The above-mentioned integrated units can be implemented in the form of hardware or in the form of software service units.

[0202] If the integrated unit is implemented in the form of a software service unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on such an understanding, the technical solution of the present application, in essence, or the part that contributes to the prior art, or all or part of this technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to enable a computer device (which can be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the methods in each embodiment of the present application. The foregoing storage medium includes: various media such as USB flash drives, mobile hard disks, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical discs that can store program codes.

[0203] Those skilled in the art should be able to realize that in one or more of the above examples, the operations described in the present invention can be implemented by hardware, software, firmware, or any combination thereof. When implemented using software, these operations can be stored in a computer-readable medium or transmitted as one or more instructions or codes on a computer-readable medium. A computer-readable medium includes computer storage media and communication media, where the communication media includes any medium that facilitates the transfer of a computer program from one place to another. The storage media can be any available medium accessible by a general-purpose or special-purpose computer.

[0204] The above specific implementation manners further elaborate on the purpose, technical solution, and beneficial effects of the present invention. It should be understood that the above is only the specific implementation manners of the present invention.

[0205] The above, the above embodiments are only used to illustrate the technical solutions of the present application, rather than limiting them; although the present application has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still modify the technical solutions recorded in the foregoing embodiments, or perform equivalent replacements on some of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A data processing method, characterized in that, The method includes: A first communication device obtains a first forward error correction (FEC) codeword sent by a second communication device; The first communication device decodes the first FEC codeword according to a first allocation relationship, where the first allocation relationship indicates an allocation relationship between a first error correction capability and a first error detection capability for processing the first FEC codeword. The first error correction capability indicates the maximum number of error symbols that can be corrected in a cyclic codeword, and the first error detection capability indicates the maximum number of error symbols that can be detected in a cyclic codeword.

2. The method according to claim 1, wherein The first error correction capability is less than the first error detection capability.

3. The method according to claim 1 or 2, characterized in that, The first allocation relationship is determined according to the link quality between the first communication device and the second communication device.

4. The method according to claim 3, wherein The first allocation relationship meets the link quality requirement, and the method further includes: Reducing the first error correction capability in the first allocation relationship and increasing the first error detection capability in the first allocation relationship to obtain a second allocation relationship, where the second allocation relationship meets the link quality requirement.

5. The method according to claim 3 or 4, characterized in that, The link quality includes: Link error rate, and / or, the number of data frame retransmissions.

6. The method according to claim 2, wherein The first communication device decodes the first FEC codeword according to the first allocation relationship, including: The first communication device corrects the first FEC codeword according to the first error correction capability to obtain a second FEC codeword; The first communication device detects the second FEC codeword according to a second error detection capability, where the second error detection capability is equal to the difference between the maximum error correction capability and the first error correction capability.

7. The method according to claim 6, characterized in that The first communication device detects the second FEC codeword according to the second error detection capability, including: The first communication device calculates 2*P syndromes according to the second FEC codeword, where P corresponds to the second error detection capability; If all of the 2*P syndromes are 0, the first communication device determines that the second FEC codeword does not include an error codeword; or, If not all of the 2*P syndromes are 0, the first communication device determines that the second FEC codeword includes an error codeword.

8. The method according to any one of claims 1-7, characterized in that, The first FEC codeword is: Reed-Solomon (RS) code.

9. The method according to claim 8, wherein The sum of the first error correction capability and the first error detection capability is equal to dmin - 1, where dmin is the minimum Hamming distance between RS codes.

10. The method according to claim 8, wherein If the first FEC codeword is RS(128, 120), then: The first error correction capability is 1 and the first error detection capability is 7; or, The first error correction capability is 2 and the first error detection capability is 6; or, The first error correction capability is 3 and the first error detection capability is 5; or, The first error correction capability is 4 and the first error detection capability is 4.

11. A data processing device, characterized in that, Applied to a first communication device, the first communication device includes a receiving unit and a processing unit; The receiving unit is configured to obtain a first forward error correction (FEC) codeword sent by a second communication device; The processing unit is configured to decode the first FEC codeword according to a first allocation relationship, where the first allocation relationship indicates an allocation relationship between a first error correction capability and a first error detection capability for processing the first FEC codeword. The first error correction capability indicates the maximum number of error symbols that can be corrected in a cyclic codeword, and the first error detection capability indicates the maximum number of error symbols that can be detected in a cyclic codeword.

12. The device according to claim 11, characterized in that, The first error correction capability is less than the first error detection capability.

13. The device according to claim 11 or 12, characterized in that, The first allocation relationship is determined according to the link quality between the first communication device and the second communication device.

14. The device according to claim 13, characterized in that, The first allocation relationship meets the link quality requirement. The processing unit is further configured to: Reduce the first error correction capability in the first allocation relationship and increase the first error detection capability in the first allocation relationship to obtain a second allocation relationship that meets the link quality requirement.

15. The device according to claim 13 or 14, characterized in that, The link quality includes: Link error rate, and / or, the number of data frame retransmissions.

16. The device according to claim 12, characterized in that, The processing unit is configured to: Correct the first FEC codeword according to the first error correction capability to obtain a second FEC codeword; Detect the second FEC codeword according to a second error detection capability, where the second error detection capability is equal to the difference between the maximum error correction capability and the first error correction capability.

17. The device according to claim 16, characterized in that, The detecting the second FEC codeword according to the second error detection capability includes: Calculating 2*P syndromes according to the second FEC codeword, where P corresponds to the second error detection capability; If all of the 2*P syndromes are 0, determining that the second FEC codeword does not include an error codeword; or, If not all of the 2*P syndromes are 0, determining that the second FEC codeword includes an error codeword.

18. The device according to any one of claims 11-17, characterized in that, The first FEC codeword is: Reed Solomon (RS) code.

19. The device according to claim 18, characterized in that, The sum of the first error correction capability and the first error detection capability is equal to dmin - 1, where dmin is the minimum Hamming distance between RS codes.

20. The device according to claim 18, wherein If the first FEC codeword is RS(128, 120), then: The first error correction capability is 1 and the first error detection capability is 7; or, The first error correction capability is 2 and the first error detection capability is 6; or, The first error correction capability is 3 and the first error detection capability is 5; or, The first error correction capability is 4 and the first error detection capability is 4.

21. A communication device, characterized in that, The communication device includes: an interface circuit and a processing circuit; The interface circuit is configured to obtain a first forward error correction (FEC) codeword sent by a second communication device; The processing circuit is configured to decode the first FEC codeword according to a first allocation relationship, where the first allocation relationship indicates an allocation relationship between a first error correction capability and a first error detection capability for processing the first FEC codeword. The first error correction capability indicates the maximum number of error symbols that can be corrected in a cyclic codeword, and the first error detection capability indicates the maximum number of error symbols that can be detected in a cyclic codeword.

22. The communication device according to claim 21, wherein, The communication device is: An optical module or a physical layer (PHY) chip.

23. A device, characterized in that, Including: A processor and a memory; The memory is configured to store instructions or computer programs; The processor is configured to execute the instructions or computer program and perform the method according to any one of claims 1-10.

24. A computer-readable storage medium, characterized in that, It includes instructions or a computer program which, when running on a computer, causes the computer to perform the method according to any one of claims 1-10 above.

25. A computer program product, characterized in that, It includes a computer program which, when running on a processor, performs the method according to any one of claims 1-10 above.

Images