Active power synthesis network based on micro-strip and waveguide hybrid architecture

Abstract

The invention discloses an active power synthesis network of a micro-strip and waveguide hybrid architecture. The active power synthesis network comprises a micro-strip power division network, a micro-strip power amplification circuit, a waveguide power combiner and a power-on / power-off sequence control circuit. The power synthesis network is designed by adopting a micro-strip and waveguide hybrid architecture, so that the overall size can be greatly reduced on the premise of ensuring the power capacity of the power synthesis network; the power-on / power-off sequence control circuit based on the Zener diode is designed, the power amplification chip can be effectively protected and prevented from being damaged due to the wrong power-on / power-off sequence, meanwhile, the number of power needing to be supplied to the power amplification chip at the same time is reduced, and the use complexity of the power synthesis module is reduced.

Description

Technical Field

[0001] The present invention belongs to an active power combining network, and particularly relates to an active power combining network based on a hybrid architecture of microstrip and waveguide. Background Art

[0002] In engineering applications, the demand for high-power solid-state power amplifiers is increasing with the rapid development of modern wireless communication and radar technologies. Therefore, the development of solid-state power amplification technology has also been promoted accordingly. In the early stage of the development of this field, the function of power amplification was usually realized by traveling-wave tube amplifiers. This technology can provide broadband signals with high power, so it is often used for power amplification. However, traveling-wave tubes are usually large in volume and weight, and have disadvantages such as non-linearity and vacuum conditions, making it inconvenient to use in many communication fields. Solid-state circuits are the most commonly used power amplification methods in addition to vacuum amplification devices such as traveling-wave tubes. Since the energy of the signal output by a single power amplification circuit within the operating frequency band usually cannot reach the level we need, power combining technology is crucial.

[0003] A power combiner can decompose the input signal into multiple paths, use power amplification chips to amplify each path of the signal separately, and then superimpose and output the multiple amplified signals. Using this technology, an output power much larger than that obtained by a single power amplification circuit can be finally obtained, thereby effectively amplifying small signals. After years of development, the power combining technology based on solid-state devices mainly has three forms: circuit-level power combining network, chip-level power combining network, and spatial power combining network. In actual engineering applications, different forms of power combining technology and their combination schemes can be adopted according to specific project requirements. Among them, the spatial power combining network can be further divided into quasi-optical power combining and free-space wave power combining. To ensure the combining efficiency and output power of multiple paths of power, the spatial power combining technology needs to ensure that the power levels of the signals amplified in each path are the same, so as to achieve the maximum combining efficiency.

[0004] Power combiners based on planar microstrip structures and spatial waveguide structures have their respective characteristics in practical applications. As a power combiner, the power capacity of the microstrip structure is relatively low, and it will exhibit a large insertion loss when operating at high frequencies. The waveguide-based power combiner has been more widely studied and applied due to its lower loss characteristics and higher power capacity. However, its larger size and more complex structure also limit its application range to a certain extent. Summary of the Invention

[0005] The object of the present invention is to provide a four-way high-power power combining network based on a hybrid microstrip and waveguide architecture, which combines four output signals amplified by power amplifier chips, and then obtains an output signal with a power much higher than the saturation output power of a single power amplifier chip.

[0006] To achieve this object, the technical solution adopted by the present invention is as follows: An active power combining network based on a hybrid microstrip and waveguide architecture, comprising:

[0007] A microstrip power splitting network, a microstrip power amplification circuit, a waveguide power combiner, and a power-on / power-off sequence control circuit. The microstrip power splitting network includes a microstrip Wilkinson power splitter and two microstrip directional couplers. The two output ports of the microstrip Wilkinson power splitter are respectively connected to the input ends of a microstrip directional coupler. The in-phase output end and the anti-phase output end of each microstrip directional coupler are respectively connected to a microstrip amplification circuit. The output end of the microstrip amplification circuit is connected to the waveguide power combiner. The waveguide power combiner couples four signals with equal amplitude and different phases into two signals with equal amplitude and the same phase, and superimposes them inside the waveguide to form a high-power signal. The power-on / power-off sequence control circuit is used to supply power to the microstrip power amplification circuit.

[0008] Preferably, each microstrip power amplification circuit includes two groups of power amplifier chips and microstrip-waveguide transition probes. The input ports of each group of power amplifier chips are connected to the in-phase output end or the anti-phase output end of the microstrip directional coupler. The output end of each group of power amplifier chips is connected to one end of the microstrip-waveguide transition probe. The other end of the microstrip-waveguide transition probe is placed in the waveguide power combiner.

[0009] Preferably, the saturation output power of the power amplifier chip is 37 dBm.

[0010] Preferably, the waveguide power combiner is composed of two waveguide directional couplers. The other ends of the two microstrip-waveguide transition probes of each microstrip power amplification circuit are respectively placed in the in-phase input end and the anti-phase input end of each waveguide directional coupler.

[0011] Preferably, the power-on / power-off sequence control circuit includes a negative voltage conversion circuit, a negative voltage protection circuit, and a gate drive circuit. The negative voltage protection circuit includes a triode integrated chip U1, a field effect transistor U2, a Zener diode D1, a first tantalum capacitor C1, a second tantalum capacitor C2, a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a fifth resistor R5, and a sixth resistor R6. The 1-pin of the field effect transistor U2 is the gate, the 2-pin and 4-pin are the drains, and the 3-pin is the source. The 1-pin of the Zener diode D1 is the cathode, and the 2-pin is the anode. The 1-pin and 4-pin of the triode integrated chip U1 are grounded, the 2-pin is connected to the right end of the sixth resistor R6, the 3-pin is connected to the left end of the fifth resistor R5, the 5-pin is connected to the right end of the third resistor R3, and the 6-pin is connected to the connection point of the third resistor R3 and the second resistor R2. The 1-pin of the field effect transistor U2 is connected to the connection point of the fourth resistor R4 and the fifth resistor R5, the 2-pin is left unconnected, and the 3-pin is connected to the external supply voltage Vds. The 1-pin of the Zener diode D1 is connected to the connection point of the first resistor R1 and the sixth resistor R6, and the 2-pin is connected to the 6-pin of the negative voltage regulator chip U3 in the negative voltage conversion circuit. The positive electrode of the first tantalum capacitor C1 is connected to the 1-pin of the field effect transistor U2, and the negative electrode is grounded. The positive electrode of the second tantalum capacitor C2 is connected to the 4-pin of the field effect transistor U2, and the negative electrode is grounded. The upper end of the first resistor R1 is connected to the 3-pin of the field effect transistor U2, and the lower end is connected to the 1-pin of the Zener diode D1. The left end of the second resistor R2 is connected to the 3-pin of the field effect transistor U2, and the right end is connected to the 6-pin of the triode integrated chip U1. The left end of the third resistor R3 is connected to the 6-pin of the triode integrated chip U1, and the right end is connected to the 5-pin of the triode integrated chip U1. The upper end of the fourth resistor R4 is connected to the 3-pin of the field effect transistor U2, and the lower end is connected to the 1-pin of the field effect transistor U2. The left end of the fifth resistor R5 is connected to the 3-pin of the triode integrated chip U1, and the right end is connected to the 1-pin of the field effect transistor U2. The left end of the sixth resistor R6 is connected to the 1-pin of the Zener diode D1, and the right end is connected to the 2-pin of the triode integrated chip U1;

[0012] The negative voltage conversion circuit includes a negative voltage regulator chip U3, a third tantalum capacitor C3, a fourth tantalum capacitor C4, a fifth tantalum capacitor C5, a sixth tantalum capacitor C6, a sixteenth resistor R16, a seventh resistor R7, an eighth resistor R8, and a ninth resistor R9. The 1-pin of the negative voltage regulator chip U3 is connected to the positive electrode of the fourth tantalum capacitor C4, the 2-pin is connected to the negative electrode of the fourth tantalum capacitor C4, the 3-pin is connected to the negative electrode of the fifth tantalum capacitor C5, the 4-pin is left unconnected, the 5-pin is connected to the connection point of the seventh resistor R7, the eighth resistor R8, and the ninth resistor R9, the 6-pin is connected to the 2-pin of the Zener diode D1 in the negative voltage protection circuit, the 7-pin is grounded, and the 8-pin is connected to the external power supply voltage Vds. The upper ends of the seventh resistor R7 and the eighth resistor R8 are connected to the 6-pin of the negative voltage regulator chip U3, and the lower ends are connected to the 5-pin of the negative voltage regulator chip U3. The upper end of the ninth resistor R9 is connected to the 5-pin of the negative voltage regulator chip U3, and the lower end is grounded. The positive electrode of the third tantalum capacitor C3 is connected to the 8-pin of the negative voltage regulator chip U3, and the negative electrode is grounded. The positive electrode of the fourth tantalum capacitor C4 is connected to the 1-pin of the negative voltage regulator chip U3, and the negative electrode is connected to the 2-pin of U3. The positive electrode of the fifth tantalum capacitor C5 is grounded, and the negative electrode is connected to the 3-pin of the negative voltage regulator chip U3. The positive electrode of the sixth tantalum capacitor C6 is grounded, and the negative electrode is connected to the 6-pin of the negative voltage regulator chip U3.

[0013] The gate drive circuit includes a transistor T1, a tenth resistor R10, an eleventh resistor R11, a twelfth resistor R12, and a thirteenth resistor R13. The 1-pin of the transistor T1 is the base, the 2-pin is the emitter, and the 3-pin is the collector. The 1-pin of the transistor T1 is connected to the connection point of the tenth resistor R10 and the thirteenth resistor R13, the 2-pin outputs the gate voltage, and the 3-pin is connected to the eleventh resistor R11. The upper end of the tenth resistor R10 is connected to the 6-pin of the negative voltage regulator chip U3 in the negative voltage conversion circuit, and the lower end is connected to the 1-pin of the transistor T1. The upper end of the eleventh resistor R11 is connected to the 6-pin of the negative voltage regulator chip U3 in the negative voltage conversion circuit, and the lower end is connected to the 3-pin of the transistor T1. The upper end of the twelfth resistor R12 is connected to the 2-pin of the transistor T1, and the lower end is grounded. The upper end of the thirteenth resistor R13 is connected to the 1-pin of the transistor T1, and the lower end is grounded.

[0014] The triode integrated chip U1 contains two triodes, namely triode 1 and triode 2. When the negative voltage conversion circuit has no output, the Zener diode is in the off state. At this time, triode 1 conducts, and the collector of triode 1 is at a low level, which in turn causes triode 2 to turn off. At this time, for the field effect transistor, the field effect transistor turns off, and there is no voltage output at the output end of the field effect transistor. When the output end of the negative voltage conversion circuit starts to output a negative voltage, the output negative voltage exceeds the breakdown voltage of the Zener diode. At this time, the Zener diode is reversely broken down and conducts, and triode 1 is cut off. At this time, the collector of triode 1 is at a high level, and then triode 2 conducts. At this time, the voltage between the gate and the source of the field effect transistor is much less than -4V. Therefore, the field effect transistor conducts, and the drain of the field effect transistor directly outputs the external power supply voltage Vds to the drain of the power amplifier chip;

[0015] The gate drive circuit is placed after the gate voltage output end of the negative voltage conversion circuit to ensure the stable and continuous output of the gate voltage.

[0016] Preferably, the power-on / power-off sequence control circuit is placed on the back of the dielectric substrate of the microstrip power divider network and the microstrip power amplifier circuit, and is connected to the front through a wire to supply power to the microstrip power amplifier circuit.

[0017] Preferably, the output microstrip line of the microstrip Wilkinson power divider adopts a bent structure.

[0018] Preferably, the power-on / power-off sequence control circuit is connected to the insulator through a wire to supply power to the upper-layer microstrip power amplifier circuit.

[0019] Compared with the prior art, the significant advantages of the present invention are as follows: The present invention adopts a hybrid architecture of microstrip and waveguide to design the power combining network. Since the input signal is small, a microstrip structure with a relatively small power capacity is used from the signal input to the power amplifier chip part, so as to minimize the overall structure size and make it applicable to more application scenarios. At the same time, after the signal is amplified by the power amplifier chip, the microstrip-waveguide transition probe radiates the energy into the waveguide space, so that it can have a larger power capacity compared with the design of a pure microstrip structure, and reduce the loss, making the combined output power approach the sum of the limit output powers of the power amplifier chips. In addition, the present invention designs a power-on / power-off sequence control circuit based on a Zener diode, which can effectively protect the power amplifier chip from being damaged due to incorrect power-on sequence, and at the same time reduces the number of power amplifier chips that need to be powered simultaneously, reducing the complexity of the power combining module. Description of the Drawings

[0020] Figure 1 It is the structural block diagram of the power combiner in the specific embodiment of the present invention;

[0021] Figure 2 It is the three-dimensional structure diagram of the power combiner in the specific embodiment of the present invention;

[0022] Figure 3 It is the schematic diagram of the power-on / power-off sequence control circuit in the specific implementation scheme of the present invention;

[0023] Figure 4 It is the specific illustration diagram of the internal negative voltage protection part of the power-on / power-off sequence control circuit in the specific implementation scheme of the present invention;

[0024] Figure 5 It is the S-parameter diagram of the passive power combining network obtained by simulation of the present invention;

[0025] Figure 6 It is the spectrogram actually measured for the present invention. Specific Embodiment

[0026] The technical solution of the present invention will be further introduced below in combination with the specific embodiment and the accompanying drawings.

[0027] This specific embodiment discloses an active power combining network based on a hybrid microstrip and waveguide architecture, and its basic structural block diagram is as Figure 1 shown, including a microstrip power divider network, a microstrip power amplifier circuit, a waveguide power combiner, and a power-on / power-off sequence control circuit. As Figure 2 shown, after the externally input RF signal enters the power combiner, it first passes through the microstrip power divider network; then passes through the power amplifier circuit connected thereto; at this time, the power-on / power-off sequence control circuit is assembled on its back to supply power to the power amplifier chip; finally, it passes through the waveguide coupler and is output from the waveguide port.

[0028] In a further embodiment, the microstrip power divider network is composed of a microstrip Wilkinson power divider and two microstrip directional couplers. The input end of the microstrip directional coupler is connected to the output end of the Wilkinson power divider, the in-phase output end and the anti-phase output end are respectively connected to the microstrip amplifier circuit, and the isolation end is connected to the load. The externally input RF signal enters from the input end, and the equal-amplitude and in-phase power distribution function is realized through the two quarter-wavelength transmission lines of the Wilkinson power divider. The two equal-amplitude and in-phase signals after being distributed are respectively input to the input ends of the two directional couplers. Among them, a 100Ω high-power isolation resistor is used for isolation between the two quarter-wavelength transmission lines of the power divider. The output section microstrip transmission line of the power divider adopts a bent structure, which can make the overall structure more compact without affecting the performance of the power combiner.

[0029] The input end of the directional coupler is connected to the output end of the power divider, and the two output ends of the coupler output two equal-amplitude and anti-phase signals, and the isolation end is connected to the load.

[0030] The entire microstrip part of the power combiner, including the microstrip power divider network part and the microstrip power amplifier part, uses a Rogers 5880 dielectric substrate with a thickness of 0.254 mm and a copper skin thickness of 0.035 mm for the microstrip line. The input and output impedances of the microstrip power divider network part are both 50 Ω.

[0031] The microstrip power amplifier circuit is as Figure 2 shown, and includes a power amplifier chip and a microstrip-waveguide transition probe. In the present invention, a power amplifier chip designed based on GaAs technology is used. The saturated output power of this chip is 37 dBm, and the power gain is 23 dB. The signal output from the coupler is amplified by this power amplifier chip and transmitted to the microstrip-waveguide transition probe. The signal is radiated from the microstrip probe into the waveguide space and will continue to propagate in the waveguide power combiner.

[0032] The waveguide power combiner consists of two waveguide directional couplers. The working center frequency of the present invention is 10 GHz, so the waveguide uses the BJ100 / WR90 standard size, as Figure 2 shown, and its standard size is a = 22.86 mm, b = 10.16 mm. The four signals transmitted from the microstrip power divider network are two in-phase and two out-of-phase. Therefore, a pair of reverse signals are respectively input into the in-phase input terminal and the out-of-phase input terminal of the waveguide coupler, are coupled inside the coupler, and output at the in-phase output terminal. The isolation terminal of the waveguide coupler is connected to the matching load. The four signals with equal amplitude and different phases are respectively coupled into two signals with equal amplitude and the same phase inside the two directional couplers, and will be further superimposed inside the waveguide to form a high-power signal and output at the waveguide output port.

[0033] As Figure 2 shown, the power-on / power-off sequence control circuit is located on the back of the microstrip and waveguide hybrid architecture power amplifier circuit structure, and is connected to the front power amplifier circuit through wires and power supply insulators, and supplies the gate voltage and drain voltage to the power amplifier chip. Since the power amplifier chip designed based on GaAs technology needs to supply the gate voltage (negative voltage) and drain voltage (positive voltage) in strict accordance with the power supply sequence, the power-on / power-off sequence control circuit is designed based on this requirement. Figure 3 What is shown is the schematic diagram of this power-on / power-off sequence control circuit. The power-on / power-off sequence control circuit consists of a negative voltage conversion circuit, a negative voltage protection circuit, and a gate drive circuit. After the external power supply voltage is input, it is first converted by the negative voltage conversion circuit into the voltage required for the gate of the power amplifier chip. The negative voltage conversion circuit consists of a voltage regulator chip U3, a peripheral circuit composed of several capacitors and resistors, and several voltage dividing resistors, and provides the gate voltage for the power amplifier chip; the negative voltage protection circuit consists of a transistor integrated chip U1, a field effect transistor U2, and several voltage dividing resistors; the gate drive circuit consists of a transistor T1 and several voltage dividing resistors.

[0034] Specifically, the power-on / power-off sequence control circuit includes a negative voltage conversion circuit, a negative voltage protection circuit, and a gate drive circuit. The negative voltage protection circuit includes a triode integrated chip U1, a field effect transistor U2, a Zener diode D1, a first tantalum capacitor C1, a second tantalum capacitor C2, a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a fifth resistor R5, and a sixth resistor R6. The 1-pin of the field effect transistor U2 is the gate, the 2-pin and 4-pin are the drains, and the 3-pin is the source. The 1-pin of the Zener diode D1 is the cathode, and the 2-pin is the anode. The 1-pin and 4-pin of the triode integrated chip U1 are grounded, the 2-pin is connected to the right end of the sixth resistor R6, the 3-pin is connected to the left end of the fifth resistor R5, the 5-pin is connected to the right end of the third resistor R3, and the 6-pin is connected to the connection point of the third resistor R3 and the second resistor R2. The 1-pin of the field effect transistor U2 is connected to the connection point of the fourth resistor R4 and the fifth resistor R5, the 2-pin is left unconnected, and the 3-pin is connected to the external power supply voltage Vds. The 1-pin of the Zener diode D1 is connected to the connection point of the first resistor R1 and the sixth resistor R6, and the 2-pin is connected to the 6-pin of the negative voltage regulator chip U3 in the negative voltage conversion circuit. The positive electrode of the first tantalum capacitor C1 is connected to the 1-pin of the field effect transistor U2, and the negative electrode is grounded. The positive electrode of the second tantalum capacitor C2 is connected to the 4-pin of the field effect transistor U2, and the negative electrode is grounded. The upper end of the first resistor R1 is connected to the 3-pin of the field effect transistor U2, and the lower end is connected to the 1-pin of the Zener diode D1. The left end of the second resistor R2 is connected to the 3-pin of the field effect transistor U2, and the right end is connected to the 6-pin of the triode integrated chip U1. The left end of the third resistor R3 is connected to the 6-pin of the triode integrated chip U1, and the right end is connected to the 5-pin of the triode integrated chip U1. The upper end of the fourth resistor R4 is connected to the 3-pin of the field effect transistor U2, and the lower end is connected to the 1-pin of the field effect transistor U2. The left end of the fifth resistor R5 is connected to the 3-pin of the triode integrated chip U1, and the right end is connected to the 1-pin of the field effect transistor U2. The left end of the sixth resistor R6 is connected to the 1-pin of the Zener diode D1, and the right end is connected to the 2-pin of the triode integrated chip U1.

[0035] The negative voltage conversion circuit includes a negative voltage regulator chip U3, a third tantalum capacitor C3, a fourth tantalum capacitor C4, a fifth tantalum capacitor C5, a sixth tantalum capacitor C6, a sixteenth resistor R16, a seventh resistor R7, an eighth resistor R8, and a ninth resistor R9; the 1-pin of the negative voltage regulator chip U3 is connected to the positive electrode of the fourth tantalum capacitor C4, the 2-pin is connected to the negative electrode of the fourth tantalum capacitor C4, the 3-pin is connected to the negative electrode of the fifth tantalum capacitor C5, the 4-pin is left unconnected, the 5-pin is connected to the connection point of the seventh resistor R7, the eighth resistor R8, and the ninth resistor R9, the 6-pin is connected to the 2-pin of the Zener diode D1 in the negative voltage protection circuit, the 7-pin is grounded, and the 8-pin is connected to the external power supply voltage Vds; the upper ends of the seventh resistor R7 and the eighth resistor R8 are connected to the 6-pin of the negative voltage regulator chip U3, and the lower ends are connected to the 5-pin of the negative voltage regulator chip U3; the upper end of the ninth resistor R9 is connected to the 5-pin of the negative voltage regulator chip U3, and the lower end is grounded; the positive electrode of the third tantalum capacitor C3 is connected to the 8-pin of the negative voltage regulator chip U3, and the negative electrode is grounded; the positive electrode of the fourth tantalum capacitor C4 is connected to the 1-pin of the negative voltage regulator chip U3, and the negative electrode is connected to the 2-pin of U3; the positive electrode of the fifth tantalum capacitor C5 is grounded, and the negative electrode is connected to the 3-pin of the negative voltage regulator chip U3; the positive electrode of the sixth tantalum capacitor C6 is grounded, and the negative electrode is connected to the 6-pin of the negative voltage regulator chip U3;

[0036] The gate drive circuit includes a transistor T1, a tenth resistor R10, an eleventh resistor R11, a twelfth resistor R12, and a thirteenth resistor R13; the 1-pin of the transistor T1 is the base, the 2-pin is the emitter, and the 3-pin is the collector; the 1-pin of the transistor T1 is connected to the connection point of the tenth resistor R10 and the thirteenth resistor R13, the 2-pin outputs the gate voltage, and the 3-pin is connected to the eleventh resistor R11; the upper end of the tenth resistor R10 is connected to the 6-pin of the negative voltage regulator chip U3 in the negative voltage conversion circuit, and the lower end is connected to the 1-pin of the transistor T1; the upper end of the eleventh resistor R11 is connected to the 6-pin of the negative voltage regulator chip U3 in the negative voltage conversion circuit, and the lower end is connected to the 3-pin of the transistor T1; the upper end of the twelfth resistor R12 is connected to the 2-pin of the transistor T1, and the lower end is grounded; the upper end of the thirteenth resistor R13 is connected to the 1-pin of the transistor T1, and the lower end is grounded;

[0037] The triode integrated chip U1 contains two triodes, namely triode 1 and triode 2. When the negative voltage conversion circuit has no output, the Zener diode is in the off state. At this time, triode 1 conducts, and the collector of triode 1 is at a low level, which in turn causes triode 2 to turn off. At this time, for the field effect transistor, so the field effect transistor turns off, and there is no voltage output at the output end of the field effect transistor. When the output end of the negative voltage conversion circuit starts to output negative voltage, the output negative voltage exceeds the breakdown voltage of the Zener diode. At this time, the Zener diode is reversely broken down and conducts, and triode 1 is cut off. At this time, the collector of triode 1 is at a high level, and then triode 2 conducts. At this time, the voltage between the gate and the source of the field effect transistor is much less than -4V. Therefore, the field effect transistor conducts, and the drain of the field effect transistor directly outputs the external power supply voltage Vds to the drain of the power amplification chip;

[0038] The gate drive circuit is placed after the gate voltage output end of the negative voltage conversion circuit to ensure the stable and continuous output of the gate voltage.

[0039] Figure 4 It is the equivalent circuit diagram of the negative voltage protection circuit in the power-on / power-off sequence control circuit. The negative voltage protection circuit consists of a Zener diode, two triodes, a field effect transistor and several voltage dividing resistors. The anode of the Zener diode is connected to the output end of the negative voltage conversion circuit, the cathode is connected to triode 1 and triode 2, triode 2 is connected to the field effect transistor, and the source of the field effect transistor is connected to the output end of the external power supply voltage Vds. When the negative voltage conversion circuit has no output, the Zener diode is in the off state. At this time, triode 1 conducts, and the collector of triode 1 is at a low level, which in turn causes triode 2 to turn off. At this time, for the field effect transistor, so the field effect transistor turns off, and there is no voltage output at the output end of the field effect transistor. When the output end of the negative voltage conversion circuit starts to output negative voltage, the output negative voltage exceeds the breakdown voltage of the Zener diode. At this time, the Zener diode is reversely broken down and conducts, and triode 1 is cut off. At this time, the collector of triode 1 is at a high level, and then triode 2 conducts. At this time, the voltage between the gate and the source of the field effect transistor is much less than -4V. Therefore, the field effect transistor conducts, and the drain of the field effect transistor directly outputs the external power supply voltage to the drain of the power amplification chip.

[0040] The gate drive circuit consists of a triode and several voltage dividing resistors. It is placed after the gate voltage output end of the negative voltage conversion circuit to ensure the stable and continuous output of the gate voltage.

[0041] Figure 5This is the S-parameter graph obtained by simulating the present invention using Ansys HFSS software. Its insertion loss is 0.9 dB at the center frequency, and the return loss is better than 10 dB in the range of 8.64 GHz to 11.03 GHz. For the present invention, its insertion loss is mainly concentrated in the microstrip part, and the loss of the waveguide part is small, so the impact on the output power is very small.

[0042] Figure 6 This is the output spectrum graph of the present invention when the input power is 21 dBm. The gate voltage during the operation of the present invention is -0.5 V, the drain voltage is +8 V, the static current during its operation is 3.2 A, and the dynamic current is 4.2 A. When the power of the input signal is 21 dBm, its saturated output power can reach 43.1 dBm, approximately 20 watts.

Claims

1. An active power combining network based on a hybrid microstrip and waveguide architecture, characterized in that Including: A microstrip power divider network, a microstrip power amplifier circuit, a waveguide power combiner, and a power-on / power-off sequence control circuit. The microstrip power divider network includes a microstrip Wilkinson power divider and two microstrip directional couplers. The two output ports of the microstrip Wilkinson power divider are respectively connected to the input ends of a microstrip directional coupler. The in-phase output end and the anti-phase output end of each microstrip directional coupler are respectively connected to a microstrip amplifier circuit. The output end of the microstrip amplifier circuit is connected to the waveguide power combiner. Through the waveguide power combiner, four signals with equal amplitude and different phases are coupled into two signals with equal amplitude and the same phase, and are superimposed inside the waveguide to form a high-power signal. The power-on / power-off sequence control circuit is used to supply power to the microstrip power amplifier circuit.

2. The active power combining network based on a hybrid microstrip and waveguide architecture according to claim 1, characterized in that Each microstrip power amplifier circuit includes two groups of power amplifier chips and microstrip-to-waveguide transition probes. The input port of each group of power amplifier chips is connected to the in-phase output end or the anti-phase output end of the microstrip directional coupler. The output end of each group of power amplifier chips is connected to one end of the microstrip-to-waveguide transition probe. The other end of the microstrip-to-waveguide transition probe is placed in the waveguide power combiner.

3. The active power combining network based on a microstrip and waveguide hybrid architecture according to claim 1, wherein The saturation output power of the power amplifier chip is 37 dBm.

4. The active power combining network based on a microstrip and waveguide hybrid architecture according to claim 2, wherein The waveguide power combiner is composed of two waveguide directional couplers. The other ends of the two microstrip-to-waveguide transition probes of each microstrip power amplifier circuit are respectively placed in the in-phase input end and the anti-phase input end of each waveguide directional coupler.

5. The active power combining network based on the hybrid microstrip and waveguide architecture according to claim 1, characterized in that The power-on / off sequence control circuit includes a negative voltage conversion circuit, a negative voltage protection circuit, and a gate drive circuit. The negative voltage protection circuit includes a triode integrated chip U1, a field effect transistor U2, a Zener diode D1, a first tantalum capacitor C1, a second tantalum capacitor C2, a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a fifth resistor R5, and a sixth resistor R6. The 1-pin of the field effect transistor U2 is the gate, the 2-pin and 4-pin are the drains, and the 3-pin is the source. The 1-pin of the Zener diode D1 is the cathode, and the 2-pin is the anode. The 1-pin and 4-pin of the triode integrated chip U1 are grounded, the 2-pin is connected to the right end of the sixth resistor R6, the 3-pin is connected to the left end of the fifth resistor R5, the 5-pin is connected to the right end of the third resistor R3, and the 6-pin is connected to the connection point of the third resistor R3 and the second resistor R2. The 1-pin of the field effect transistor U2 is connected to the connection point of the fourth resistor R4 and the fifth resistor R5, the 2-pin is left unconnected, and the 3-pin is connected to the external power supply voltage Vds. The 1-pin of the Zener diode D1 is connected to the connection point of the first resistor R1 and the sixth resistor R6, and the 2-pin is connected to the 6-pin of the negative voltage regulator chip U3 in the negative voltage conversion circuit. The positive electrode of the first tantalum capacitor C1 is connected to the 1-pin of the field effect transistor U2, and the negative electrode is grounded. The positive electrode of the second tantalum capacitor C2 is connected to the 4-pin of the field effect transistor U2, and the negative electrode is grounded. The upper end of the first resistor R1 is connected to the 3-pin of the field effect transistor U2, and the lower end is connected to the 1-pin of the Zener diode D1. The left end of the second resistor R2 is connected to the 3-pin of the field effect transistor U2, and the right end is connected to the 6-pin of the triode integrated chip U1. The left end of the third resistor R3 is connected to the 6-pin of the triode integrated chip U1, and the right end is connected to the 5-pin of the triode integrated chip U1. The upper end of the fourth resistor R4 is connected to the 3-pin of the field effect transistor U2, and the lower end is connected to the 1-pin of the field effect transistor U2. The left end of the fifth resistor R5 is connected to the 3-pin of the triode integrated chip U1, and the right end is connected to the 1-pin of the field effect transistor U2. The left end of the sixth resistor R6 is connected to the 1-pin of the Zener diode D1, and the right end is connected to the 2-pin of the triode integrated chip U1; The negative voltage conversion circuit includes a negative voltage regulator chip U3, a third tantalum capacitor C3, a fourth tantalum capacitor C4, a fifth tantalum capacitor C5, a sixth tantalum capacitor C6, a sixteenth resistor R16, a seventh resistor R7, an eighth resistor R8, and a ninth resistor R9; the 1st pin of the negative voltage regulator chip U3 is connected to the positive electrode of the fourth tantalum capacitor C4, the 2nd pin is connected to the negative electrode of the fourth tantalum capacitor C4, the 3rd pin is connected to the negative electrode of the fifth tantalum capacitor C5, the 4th pin is left unconnected, the 5th pin is connected to the connection point of the seventh resistor R7, the eighth resistor R8, and the ninth resistor R9, the 6th pin is connected to the 2nd pin of the Zener diode D1 in the negative voltage protection circuit, the 7th pin is grounded, and the 8th pin is connected to the external power supply voltage Vds; the upper ends of the seventh resistor R7 and the eighth resistor R8 are connected to the 6th pin of the negative voltage regulator chip U3, and the lower ends are connected to the 5th pin of the negative voltage regulator chip U3; the upper end of the ninth resistor R9 is connected to the 5th pin of the negative voltage regulator chip U3, and the lower end is grounded; the positive electrode of the third tantalum capacitor C3 is connected to the 8th pin of the negative voltage regulator chip U3, and the negative electrode is grounded; the positive electrode of the fourth tantalum capacitor C4 is connected to the 1st pin of the negative voltage regulator chip U3, and the negative electrode is connected to the 2nd pin of U3; the positive electrode of the fifth tantalum capacitor C5 is grounded, and the negative electrode is connected to the 3rd pin of the negative voltage regulator chip U3; the positive electrode of the sixth tantalum capacitor C6 is grounded, and the negative electrode is connected to the 6th pin of the negative voltage regulator chip U3; The gate drive circuit includes a transistor T1, a tenth resistor R10, an eleventh resistor R11, a twelfth resistor R12, and a thirteenth resistor R13; the 1st pin of the transistor T1 is the base, the 2nd pin is the emitter, and the 3rd pin is the collector; the 1st pin of the transistor T1 is connected to the connection point of the tenth resistor R10 and the thirteenth resistor R13, the 2nd pin outputs the gate voltage, and the 3rd pin is connected to the eleventh resistor R11; the upper end of the tenth resistor R10 is connected to the 6th pin of the negative voltage regulator chip U3 in the negative voltage conversion circuit, and the lower end is connected to the 1st pin of the transistor T1; the upper end of the eleventh resistor R11 is connected to the 6th pin of the negative voltage regulator chip U3 in the negative voltage conversion circuit, and the lower end is connected to the 3rd pin of the transistor T1; the upper end of the twelfth resistor R12 is connected to the 2nd pin of the transistor T1, and the lower end is grounded; the upper end of the thirteenth resistor R13 is connected to the 1st pin of the transistor T1, and the lower end is grounded; The transistor integrated chip U1 contains two transistors inside, namely transistor 1 and transistor 2. When the negative voltage conversion circuit has no output, the Zener diode is in the off state. At this time, transistor 1 conducts, and the collector of transistor 1 is at a low level, which in turn causes transistor 2 to turn off. At this time, for the field effect transistor, so the field effect transistor turns off, and there is no voltage output at the output end of the field effect transistor. When the output end of the negative voltage conversion circuit starts to output negative voltage, the output negative voltage exceeds the breakdown voltage of the Zener diode. At this time, the Zener diode is reversely broken down and conducts, transistor 1 is cut off, and the collector of transistor 1 is at a high level. Then transistor 2 conducts. At this time, the voltage between the gate and the source of the field effect transistor is much less than -4V. Therefore, the field effect transistor conducts, and the drain of the field effect transistor directly outputs the external power supply voltage Vds to the drain of the power amplification chip; The gate drive circuit is placed after the gate voltage output end of the negative voltage conversion circuit to ensure the stable and continuous output of the gate voltage.

6. The active power combining network based on the hybrid microstrip and waveguide architecture according to claim 1, characterized in that, The power-on / power-off sequence control circuit is placed on the back of the dielectric substrate of the microstrip power divider network and the microstrip power amplifier circuit, and is connected by wires to the front to supply power to the microstrip power amplifier circuit.

7. The active power combining network based on the hybrid microstrip and waveguide architecture according to claim 1, characterized in that, The output microstrip line of the microstrip Wilkinson power divider adopts a bent structure.

8. The active power combining network based on the hybrid microstrip and waveguide architecture according to claim 1, characterized in that, The power-on / power-off sequence control circuit is connected to the insulator through wires, so as to supply power to the upper-layer microstrip power amplifier circuit.

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