Memory structure and forming method thereof
By using transition metal sulfide as channel material and graphene as floating gate in NOR flash memory, the problems of channel length shortening and leakage are solved, and the performance and reliability of the memory are improved.
Patent Information
- Application Number
- CN202410090761.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-01-22
- Publication Date
- 2025-07-25
AI Technical Summary
When existing NOR flashes have nodes below 28nm, the shortening of the channel length and thinning of the gate oxygen layer lead to degradation of memory performance, resulting in short channel effect and leakage problems.
Transition metal sulfide is used as channel material and graphene material as floating gate. A natural barrier is formed through the unique Dirac cone energy band structure, which reduces short channel effects and leakage, and improves memory performance and reliability.
It effectively reduces short channel effect and leakage problems, improves memory performance and reduces memory area, and enhances memory reliability.
Smart Images
Figure CN120379259A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of semiconductors, and particularly to a memory structure and a method for forming the same. Background Art
[0002] As a non-volatile memory, NOR Flash has characteristics such as non-volatility, high device density, low power consumption, and electrical rewritability, and is widely used in portable electronic products such as mobile phones, digital cameras, smart cards, etc. With the gradual intelligence of the automotive, industrial, etc. and the trend of in-memory computing, higher requirements are put forward for the area of a single cell and the storage density in NOR Flash.
[0003] Currently, a memory generally includes an erase gate, a control gate, and a floating gate. However, as the memory nodes are reduced, especially at nodes below 28 nm, the channel length is shortened and the thickness of the gate oxide layer between the substrate and the floating gate also becomes thinner, resulting in a shortened electron storage time and reducing the performance of the memory.
[0004] Therefore, the performance of the existing memory needs to be further improved. Summary of the Invention
[0005] The technical problem solved by the present invention is to provide a memory structure and a method for forming the same to improve the performance of the memory structure.
[0006] To solve the above technical problem, an embodiment of the present invention provides a memory structure, including: a substrate; a channel structure located on the substrate, the channel structure including a bit line region and a source line region, and the material of the channel structure including transition metal sulfide; an erase gate located on the source line region, a floating gate located on the source line region, a control gate structure located on the floating gate, a word line gate located on the source line region, the floating gate being located between the erase gate and the word line gate, and the material of the floating gate including graphene material; a bit line located on the bit line region.
[0007] Optionally, the transition metal sulfide includes a single-layer structure or a multi-layer structure; the thickness range of the channel structure is from 1 nanometer to 50 nanometers.
[0008] Optionally, the graphene material includes a single-layer structure or a multi-layer structure; the thickness range of the floating gate is from 0.3 nanometer to 30 nanometers.
[0009] Optionally, it further includes: a source line lead-out structure located on the surface of the source line region, and the source line lead-out structure is connected to the source line region through an ohmic contact.
[0010] Optionally, it further includes: a bit line lead-out structure located on the surface of the bit line region, the bit line lead-out structure being located on one side of the word line gate, and the bit line lead-out structure is connected to the bit line region through an ohmic contact.
[0011] Optionally, it further includes: a first oxide layer located between the substrate and the channel structure, and a second oxide layer located on the surface of the channel structure. The floating gate, word line gate, and erase gate are located on the surface of the second oxide layer.
[0012] Optionally, it further includes: an interlayer dielectric layer located on the substrate, and the interlayer dielectric layer is located on the surfaces of the erase gate, floating gate, control gate structure, and word line gate.
[0013] Optionally, the control gate structure includes: a control gate dielectric layer located on the top surface of the floating gate, a control gate layer located on the surface of the control gate dielectric layer, and a control gate sidewall located on the sidewall surface of the control gate layer.
[0014] Optionally, the control gate dielectric layer and the control gate sidewall include a third dielectric layer located on the sidewall surface and the bottom surface of the control gate layer, a first dielectric layer located on the surface of the third dielectric layer, and a second dielectric layer located between the first dielectric layer and the third dielectric layer. The material of the second dielectric layer is different from that of the first dielectric layer and the third dielectric layer.
[0015] Optionally, it further includes: a capping layer located on the top surface of the control gate layer.
[0016] Optionally, it further includes: a first conductive plug located on the top surface of the word line gate and the top surface of the erase gate respectively; a second conductive plug penetrating the capping layer, and the second conductive plug is located on the top surface of the control gate layer.
[0017] Optionally, the sidewall of the floating gate protrudes compared to the sidewall of the control gate layer; the bottom surface of the erase gate is recessed towards the top of the erase gate, and the included angle between the bottom surface and the sidewall surface of the erase gate is an acute angle.
[0018] Correspondingly, the technical solution of the present invention also provides a method for forming a memory structure, including: providing a substrate; forming a channel structure on the substrate, the channel structure includes a bit line region and a source line region, and the material of the channel structure includes transition metal sulfide; forming a floating gate on the source line region, and the material of the floating gate includes graphene material; forming a control gate structure on the floating gate; forming a word line gate and an erase gate on the source line region, and the floating gate is located between the erase gate and the word line gate; forming a bit line on the bit line region.
[0019] Optionally, after forming the channel structure, it further includes: forming a source line lead-out structure on the surface of the source line region, and the source line lead-out structure is connected to the source line region through an ohmic contact.
[0020] Optionally, after forming the channel structure, it further includes: forming a bit line lead-out structure on the surface of the bit line region, the bit line lead-out structure is located on one side of the word line gate, and the bit line lead-out structure is connected to the bit line region through an ohmic contact.
[0021] Optionally, before forming the channel structure, the method further includes: forming a first oxide layer between the substrate and the channel structure, forming a second oxide layer on the surface of the channel structure, and the floating gate, word line gate, and erase gate are located on the surface of the second oxide layer.
[0022] Optionally, after forming the erase gate, floating gate, control gate structure, and word line gate, the method further includes: forming an interlayer dielectric layer on the substrate, and the interlayer dielectric layer is located on the surfaces of the erase gate, floating gate, control gate structure, and word line gate.
[0023] Optionally, the control gate structure includes: a control gate dielectric layer located on the top surface of the floating gate, a control gate layer located on the surface of the control gate dielectric layer, a capping layer located on the top surface of the control gate layer, and a control gate sidewall located on the sidewall surfaces of the control gate layer, the capping layer, and the control gate dielectric layer sidewall.
[0024] Optionally, the method for forming the floating gate and the control gate structure includes: forming a floating gate layer on the channel structure; forming a control gate dielectric material layer on the top surface of the floating gate layer; forming an initial control gate layer on the surface of the control gate dielectric material layer; forming a capping layer on the top surface of the initial control gate layer; using the capping layer as a mask to etch the initial control gate layer and the control gate dielectric material layer to form a control gate, and the control gate includes a control gate layer and a control gate dielectric layer; forming a control gate sidewall on the sidewall surface of the control gate; using the control gate sidewall and the control gate as a mask to etch the floating gate layer to form a floating gate on the channel structure.
[0025] Optionally, after forming the interlayer dielectric layer, the method further includes: etching the interlayer dielectric layer until the top surfaces of the word line gate and the erase gate are exposed to form a first groove; forming a first conductive plug in the first groove; etching the interlayer dielectric layer and the capping layer until the top surface of the control gate layer is exposed to form a second groove; forming a second conductive plug in the second groove, and the second conductive plug is located on the top surface of the control gate layer.
[0026] Compared with the prior art, the technical solution of the embodiment of the present invention has the following beneficial effects:
[0027] In the memory structure provided by the technical solution of the present invention, a transition metal sulfide is used as the channel material, which reduces the short-channel effect caused by the shortening of the channel length and the leakage problem between the channel and the floating gate, improves the performance of the memory structure and reduces the storage area; on this basis, graphene material is used as the floating gate. Since the graphene material has a unique Dirac cone energy band structure, the electrons written into the floating gate are at an energy level lower than the conduction band energy level of the transition metal sulfide in the floating gate. Thus, a natural potential barrier is generated between the floating gate and the channel structure, which hinders the risk of electron leakage from the floating gate to the channel structure and improves the reliability of the memory structure.
[0028] Furthermore, the transition metal sulfide material includes a single-layer structure or a multi-layer structure, that is, the transition metal sulfide material has the characteristic of adjustable number of layers, which enhances the control of the floating gate, the word line gate, and the control gate over the channel structure, and further improves the performance of the memory structure.
[0029] In the method for forming the memory structure provided by the technical solution of the present invention, a transition metal sulfide is used to form a channel structure, which reduces the short-channel effect caused by the shortening of the channel length and the leakage problem between the channel and the floating gate, improves the performance of the memory structure and reduces the storage area; on this basis, a graphene material is used to form the floating gate. Since the graphene material has a unique Dirac cone energy band structure, the electrons written into the floating gate are at an energy level lower than the conduction band energy level of the transition metal sulfide in the floating gate. Thus, a natural potential barrier is generated between the floating gate and the channel structure, which hinders the risk of electron leakage from the floating gate to the channel structure and improves the reliability of the memory structure. BRIEF DESCRIPTION OF THE DRAWINGS
[0030] Figure 1 is a schematic structural diagram of a memory structure;
[0031] Figures 2 to 9 is a schematic structural diagram of the formation process of the memory structure in the embodiment of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS
[0032] It should be noted that the "surface" and "upper" in this specification are used to describe the relative positional relationship in space and do not limit whether there is direct contact.
[0033] As in the background art, the existing memory structure needs to be further improved. The following is an analysis and description in combination with specific embodiments.
[0034] Please refer to Figure 1 , the memory structure includes: a substrate 100, the substrate 100 includes a floating gate region, an erasing region and a word line gate region distributed on both sides of the floating gate region; an erasing gate structure 104 located on the erasing region; a floating gate structure 105 located on the floating gate region, and a control gate structure 106 located on the floating gate structure 105; a word line gate structure 108 located on the word line gate region, and the floating gate structure 105 is located between the erasing gate structure 104 and the word line gate structure 108.
[0035] In this embodiment, the memory structure further includes a source line doping region 103 located in the erasing region, and the erasing gate structures 104 on the erasing regions between adjacent floating gate regions share the source line doping region 103.
[0036] In this embodiment, the memory structure further includes a bit line doping region 101 located in the substrate 100, and the bit line doping region 101 is located on one side of the word line gate structure.
[0037] In this embodiment, an oxide layer 110 located on the substrate 100 is further included, and the oxide layer 110 covers the erase gate structure 104, the control gate structure 106, the floating gate structure 105, and the word line gate structure.
[0038] In this embodiment, a dielectric layer 107 located on the surface of the control gate structure 106 is further included.
[0039] In this embodiment, a conductive plug 109 located on the surface of the bit line doping region 101, on the surface of the word line gate structure 108, through the dielectric layer 107, and on the surface of the erase gate structure 104 is further included.
[0040] In this embodiment, a gate oxide layer 111 located between the floating gate structure 105 and the channel 102 is further included.
[0041] In the memory structure in the above solution, the bit line doping region 101 and the source line doping region 103 are located in the substrate 100, that is, the channel 102 is also located in the substrate 100. By applying pressure on the word line gate structure 108 and the control gate structure 106, an inversion layer is formed on the surface of the substrate 100 to control the on / off of the channel 102. However, as the memory nodes are reduced, especially at nodes below 28 nm, the shortening of the channel 102 length results in a serious short channel 102, reducing the performance of the memory.
[0042] In addition, the material of the floating gate structure 105 usually uses doped polysilicon material, which often requires the gate oxide layer 111 between the floating gate structure 105 and the channel 102 to have a larger thickness to prevent the leakage of stored electrons. As the memory nodes are reduced, the gate oxide layer 111 becomes thinner, which is likely to cause a leakage problem between the channel 102 and the floating gate structure 105, further reducing the performance of the memory.
[0043] To solve the above problems, the present invention provides a memory structure and a method for forming the same, using transition metal sulfide as the channel material, reducing the short channel effect caused by the shortening of the channel length and the leakage problem between the channel and the floating gate, improving the performance of the memory structure and reducing the storage area. On this basis, graphene material is used as the floating gate. Since the graphene material has a unique Dirac cone energy band structure, the electrons written into the floating gate are at an energy level lower than the conduction band energy level of the transition metal sulfide in the floating gate. Thus, a natural potential barrier is generated between the floating gate and the channel structure, hindering the risk of electron leakage from the floating gate to the channel structure and improving the reliability of the memory structure.
[0044] To make the above objects, features, and beneficial effects of the present invention more obvious and understandable, the following detailed description of the specific embodiments of the present invention will be given with reference to the accompanying drawings.
[0045] Figures 2 to 9It is a schematic structural diagram of the formation process of the memory structure in the embodiment of the present invention.
[0046] Please refer to Figure 2 , a substrate 200 is provided; a channel structure 202 is formed on the substrate 200. The channel structure 202 includes a bit line region II and a source line region I. The material of the channel structure 202 includes transition metal sulfide.
[0047] The transition metal sulfide includes molybdenum disulfide, tungsten disulfide, rhenium disulfide, molybdenum diselenide, tungsten diselenide, titanium diselenide, niobium diselenide or rhenium diselenide.
[0048] In this embodiment, since the transition metal sulfide material has a large energy gap and moderate carrier mobility, using the transition metal sulfide nanosheet as the material of the channel structure 202 can enhance the control of the gate over the channel structure, and reduce the short-channel effect caused by the shortening of the channel length and the leakage problem between the channel and the floating gate.
[0049] The number of layers of the channel structure 202 ranges from 1 layer to 30 layers.
[0050] The thickness of the channel structure 202 ranges from 1 nanometer to 50 nanometers.
[0051] The thickness of each layer in the channel structure 202 is 1 nanometer.
[0052] The manufacturing process of the channel structure 202 includes: direct method and indirect method. The direct method includes mechanical exfoliation method and liquid-phase exfoliation method. The indirect method includes molecular beam epitaxy method, chemical vapor deposition method, metalorganic chemical vapor deposition method and atomic layer deposition method.
[0053] Before forming the channel structure 202, it further includes: forming a first oxide layer 201 between the substrate 200 and the channel structure 202.
[0054] In this embodiment, the material of the substrate 200 is silicon.
[0055] In other embodiments, the material of the substrate 200 includes silicon carbide, silicon germanium, a multi-semiconductor material composed of group III-V elements, silicon on insulator (SOI) or germanium on insulator (GOI). Among them, the multi-semiconductor material composed of group III-V elements includes InP, GaAs, GaP, InAs, InSb, InGaAs or InGaAsP.
[0056] In this embodiment, the material of the first oxide layer 201 is silicon oxide.
[0057] In this embodiment, the formation process of the first oxide layer 201 is chemical vapor deposition process.
[0058] In other embodiments, the formation process of the first oxide layer 201 may also be a physical vapor deposition process or an atomic layer deposition process.
[0059] In the above solutions, a transition metal sulfide is used as the channel material, reducing the short-channel effect caused by the shortening of the channel length and the leakage problem between the channel and the floating gate, improving the performance of the memory structure and reducing the storage area.
[0060] In addition, the transition metal sulfide material includes a single-layer structure or a multi-layer structure, that is, the transition metal sulfide material has the characteristic of adjustable number of layers, enabling the floating gate, word line gate, and control gate to enhance the control of the channel structure, further improving the performance of the memory structure.
[0061] Please refer to Figure 3 , and a second oxide layer 203 is formed on the surface of the channel structure 202.
[0062] In this embodiment, the material of the second oxide layer 203 is silicon oxide.
[0063] In this embodiment, the formation process of the second oxide layer 203 is a chemical vapor deposition process.
[0064] In other embodiments, the formation process of the second oxide layer 203 may also be a physical vapor deposition process or an atomic layer deposition process.
[0065] Please refer to Figure 4 , a floating gate layer 204 is formed on the surface of the second oxide layer 203; a control gate structure is formed on the surface of the floating gate layer 204.
[0066] The control gate structure includes: a control gate dielectric layer 205 located on the top surface of the floating gate layer 204, a control gate layer 206 located on the surface of the control gate dielectric layer 205, a covering layer 207 located on the top surface of the control gate layer 206, and a control gate sidewall located on the sidewall surfaces of the control gate layer 206, the covering layer 207, and the control gate dielectric layer 205 sidewall surfaces.
[0067] The method for forming the control gate structure includes: forming a control gate dielectric material layer on the top surface of the floating gate layer 204; forming an initial control gate layer (not shown in the figure) on the surface of the control gate dielectric material layer; forming a covering layer 207 on the top surface of the initial control gate layer (not shown in the figure); using the covering layer 207 as a mask to etch the initial control gate layer (not shown in the figure) and the control gate dielectric material layer to form a control gate, the control gate including a control gate layer 206 and a control gate dielectric layer 205; forming a control gate sidewall on the sidewall surface of the control gate.
[0068] The control gate sidewall includes: a first control gate sidewall 208 located on the sidewall surface of the control gate layer 206, the sidewall surface of the covering layer 207, and the sidewall surface of the control gate dielectric layer 205, and a second control gate sidewall 209 located on the sidewall of the first control gate sidewall 208. The materials of the first control gate sidewall 208 and the second control gate sidewall 209 are different.
[0069] The control gate dielectric layer 205 and the control gate sidewall include a third dielectric layer located on the sidewall surface and the bottom surface of the control gate layer 206, a first dielectric layer located on the surface of the third dielectric layer, and a second dielectric layer located between the first dielectric layer and the third dielectric layer. The material of the second dielectric layer is different from the materials of the first dielectric layer and the third dielectric layer.
[0070] The material of the first dielectric layer includes silicon oxide, the material of the second dielectric layer includes silicon nitride, and the material of the third dielectric layer includes silicon oxide.
[0071] Please refer to Figure 5 , using the control gate sidewall and the control gate as masks to etch the floating gate layer 204, and forming a floating gate 211 on the channel structure 202.
[0072] In this embodiment, the sidewall of the floating gate protrudes compared to the sidewall of the control gate layer 206, so that the floating gate extends into the subsequently formed erase gate 214, which is beneficial to improving the erasing efficiency.
[0073] Please refer to Figure 6 , forming a word line gate 215 and an erase gate 214 on the source line region I, and the floating gate is located between the erase gate 214 and the word line gate 215.
[0074] The bottom surface of the erase gate 214 is recessed towards the top of the erase gate 214, and the included angle formed by the bottom surface and the sidewall surface of the erase gate 214 is an acute angle.
[0075] The materials of the erase gate 214, the word line gate 215, the floating gate 211, and the control gate layer 206 include: single crystal silicon, polycrystalline silicon, amorphous silicon, hafnium oxide, iridium oxide, ruthenium oxide.
[0076] The methods for forming the erase gate 214, the word line gate 215, the floating gate 211, and the control gate layer 206 include: one or more of chemical vapor deposition, physical deposition, atomic layer deposition, and jet vapor deposition. The deposition gases include: hydrogen and silane, and the reaction temperature range is from 400 degrees Celsius to 800 degrees Celsius.
[0077] In this embodiment, the material of the floating gate 211 includes a graphene material.
[0078] In this embodiment, the graphene material includes a single-layer structure or a multi-layer structure.
[0079] In this embodiment, the thickness range of the floating gate 211 is from 0.3 nanometers to 30 nanometers.
[0080] Before forming the word line gate 215 and the erase gate 214, it further includes: removing the second control gate sidewall 209; forming an erase gate dielectric layer 212 between the erase gate 214 and the channel structure 202, between the erase gate 214 and the floating gate, and between the erase gate 214 and the first control gate sidewall 208; forming a word line gate dielectric layer 213 between the word line gate 215 and the channel structure 202, between the word line gate 215 and the floating gate, and between the word line gate 215 and the first control gate sidewall 208.
[0081] In this embodiment, each erase gate 214 is located between two adjacent floating gates, and one erase gate 214 is shared between two control gate structures.
[0082] In the above solution, a graphene material is used to form the floating gate. Due to the unique Dirac cone energy band structure of the graphene material, the electrons written into the floating gate are at an energy level lower than the conduction band energy level of the transition metal sulfide in the floating gate. Thus, a natural potential barrier is generated between the floating gate and the channel structure, which hinders the risk of electron leakage from the floating gate to the channel structure and improves the reliability of the memory structure.
[0083] Please refer to Figure 7 , after forming the erase gate 214, the floating gate, the control gate structure, and the word line gate 215, it further includes: forming an interlayer dielectric layer 216 on the substrate 200, and the interlayer dielectric layer 216 is located on the surfaces of the erase gate 214, the floating gate, the control gate structure, and the word line gate 215.
[0084] The material of the interlayer dielectric layer 216 includes: silicon oxide, nitrogen-doped silicon oxide, or silicon oxynitride.
[0085] Please refer to Figure 8 , forming a bit line lead-out structure 217 on the surface of the bit line region II.
[0086] The formation method of the bit line lead-out structure 217 includes: etching the interlayer dielectric layer 216 and the second oxide layer 203 on the surface of the bit line region II to form a groove (not shown in the figure), and the groove (not shown in the figure) exposes the surface of the channel structure 202; forming a bit line lead-out structure 217 in the groove, and the bit line lead-out structure 217 is located on one side of the word line gate 215, and the bit line lead-out structure 217 is connected to the bit line region II through an ohmic contact.
[0087] Please refer to Figure 9 , forming a first conductive plug 218 respectively located on the top surface of the word line gate 215 and the top surface of the erase gate 214, and a second conductive plug 219 located on the top surface of the control gate in the interlayer dielectric layer.
[0088] The method for forming the first conductive plug 218 includes: etching the interlayer dielectric layer 216 to form a first groove (not shown in the figure) that exposes the top surface of the word line gate 215 and the top surface of the erase gate 214 respectively; forming the first conductive plug 218 in the first groove.
[0089] The method for forming the second conductive plug 219 includes: etching the covering layer 207 to form a second groove (not shown in the figure) that exposes the top surface of the control gate layer 206; forming the second conductive plug 219 in the second groove, and the second conductive plug 219 is located on the top surface of the control gate layer 206.
[0090] In this embodiment, the materials of the first conductive plug 218 and the second conductive plug 219 include aluminum and copper.
[0091] In this embodiment, the method for forming the first groove and the second groove includes one or a combination of both of the wet etching process and the dry etching process.
[0092] The wet etching process parameters include: the etching solution includes at least two of ammonia water, hydrogen peroxide, acetic acid, and ammonium fluoride, and the mass concentration range of each solution is from 0 wt% to 30 wt%, and the reaction temperature range is from 0 degrees Celsius to 80 degrees Celsius.
[0093] The process parameters of the dry etching process include: the etching gas includes at least three of fluorine gas, hydrogen gas, nitrogen gas, argon gas, and ammonia gas, and the flow rate range of each gas is from 0 mL / min to 2000 mL / min, the reaction pressure range is from 0 mT to 3000 mT, the reaction temperature range is from 0 degrees Celsius to 250 degrees Celsius, and the etching power range is from 0 W to 1000 W.
[0094] The following will be combined with Figure 9 to illustrate the writing process of the memory structure:
[0095] Apply a positive voltage to the control gate structure and the word line gate 215 simultaneously, so that the channel formed by the channel structure 202 is opened, and then an electron channel is formed. Apply a voltage or a constant current source to the bit line and the source line respectively, so that electrons flow from the bit line into the source line. At this time, due to the hot carrier effect in the electron channel of the substrate 200, electrons will enter the floating gate 211, realizing the writing process.
[0096] The following will be combined with Figure 9 to illustrate the erasing process of the memory structure:
[0097] Apply a high voltage to the erase gate 214. The floating gate 211 has a protruding extension structure, which increases the critical electric field at the sharp corner position, forming a potential difference on the erase gate 214, which is sufficient to pull the electrons written in the floating gate 211 to the erase gate 214 through the tunneling mechanism, and then empty the electrons stored in the erase gate 214.
[0098] The following will describe the read process of the memory structure in conjunction with Figure 9 :
[0099] Apply a high voltage or a low voltage to the word line gate 215 and the source line to generate a voltage difference. Apply a positive voltage to the word line gate 215 to ensure that the channel structure 202 under the word line gate 215 is opened. Apply a positive voltage to the control gate structure. When there are electrons inside the floating gate 211 and the voltage applied to the control gate structure is not sufficient to ensure that the channel structure 202 under the floating gate 211 is opened, that is, the channel structure 202 between the bit line and the source line is not conducting, and the data read at this time is "0"; when there are no electrons inside the floating gate and the voltage applied to the control gate structure is sufficient to ensure that the channel structure 202 under the floating gate 211 is opened, that is, the channel structure 202 between the bit line and the source line is conducting, and the data read at this time is "1".
[0100] Correspondingly, please continue to refer to Figure 9 , the technical solution of the present invention also provides a memory structure, including: a substrate 200; a channel structure 202 located on the substrate 200, the channel structure 202 includes a bit line region II and a source line region I, and the material of the channel structure 202 includes transition metal sulfide; an erase gate 214 located on the source line region I, a floating gate 211 located on the source line region I, a control gate structure located on the floating gate 211, a word line gate 215 located on the source line region I, the floating gate 211 is located between the erase gate 214 and the word line gate 215, and the material of the floating gate 211 includes graphene material; a bit line located on the bit line region II.
[0101] In this embodiment, the transition metal sulfide includes a single-layer structure or a multi-layer structure; the thickness range of the channel structure 202 is 1 nanometer to 50 nanometers.
[0102] In this embodiment, the graphene material includes a single-layer structure or a multi-layer structure; the thickness range of the floating gate 211 is 0.3 nanometer to 30 nanometers.
[0103] In this embodiment, the memory structure further includes: a source line lead-out structure located on the surface of the source line region I, and the source line lead-out structure is connected to the source line region I through an ohmic contact.
[0104] In this embodiment, the memory structure further includes: a bit line lead-out structure 217 located on the surface of the bit line region II, the bit line lead-out structure 217 is located on one side of the word line gate 215, and the bit line lead-out structure 217 is connected to the bit line region II through an ohmic contact.
[0105] In this embodiment, the memory structure further includes: a first oxide layer 201 located between the substrate 200 and the channel structure 202, and a second oxide layer 203 located on the surface of the channel structure 202. The floating gate 211, the word line gate 215, and the erase gate 214 are located on the surface of the second oxide layer 203.
[0106] In this embodiment, the memory structure further includes: an interlayer dielectric layer 216 located on the substrate 200, and the interlayer dielectric layer 216 is located on the surfaces of the erase gate 214, the floating gate 211, the control gate structure, and the word line gate 215.
[0107] In this embodiment, the control gate structure includes: a control gate dielectric layer 205 located on the top surface of the floating gate 211, a control gate layer 206 located on the surface of the control gate dielectric layer 205, and a control gate sidewall located on the sidewall surface of the control gate layer 206.
[0108] In this embodiment, the control gate dielectric layer 205 and the control gate sidewall include a third dielectric layer located on the sidewall surface and the bottom surface of the control gate layer 206, a first dielectric layer located on the surface of the third dielectric layer, and a second dielectric layer located between the first dielectric layer and the third dielectric layer. The material of the second dielectric layer is different from that of the first dielectric layer and the third dielectric layer.
[0109] In this embodiment, the memory structure further includes: a capping layer 207 located on the top surface of the control gate layer 206.
[0110] In this embodiment, the memory structure further includes: a first conductive plug 218 located on the top surface of the word line gate 215 and the top surface of the erase gate 214 respectively; a second conductive plug 219 passing through the capping layer 207, and the second conductive plug 219 is located on the top surface of the control gate layer 206.
[0111] In this embodiment, the sidewall of the floating gate 211 protrudes compared to the sidewall of the control gate layer 206; the bottom surface of the erase gate 214 is recessed towards the top of the erase gate 214, and the included angle between the bottom surface and the sidewall surface of the erase gate 214 is an acute angle.
[0112] In the above memory structure, transition metal sulfide is used as the channel material, which reduces the short-channel effect caused by the shortening of the channel length and the leakage problem between the channel and the floating gate 211, improves the performance of the memory structure and reduces the storage area; on this basis, graphene material is used as the floating gate 211. Due to the unique Dirac cone energy band structure of the graphene material, the electrons written into the floating gate 211 are at an energy level lower than the conduction band energy level of the transition metal sulfide in the floating gate 211. Thus, a natural potential barrier is generated between the floating gate 211 and the channel structure 202, which hinders the risk of electrons leaking from the floating gate 211 to the channel structure 202 and improves the reliability of the memory structure.
[0113] Although the present invention has been disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.
Claims
1. A memory structure, characterized in that, Comprising: A substrate; A channel structure located on the substrate, the channel structure including a bit line region and a source line region, and the material of the channel structure including transition metal sulfide; An erase gate located on the source line region, a floating gate located on the source line region, a control gate structure located on the floating gate, and a word line gate located on the source line region, the floating gate being located between the erase gate and the word line gate, and the material of the floating gate including graphene material; A bit line located on the bit line region.
2. The memory structure according to claim 1, wherein The transition metal sulfide includes a single-layer structure or a multi-layer structure; the thickness range of the channel structure is from 1 nanometer to 50 nanometers.
3. The memory structure according to claim 1, characterized in that, The graphene material includes a single-layer structure or a multi-layer structure; the thickness range of the floating gate is from 0.3 nanometer to 30 nanometers.
4. The memory structure according to claim 1, wherein Further comprising: A source line lead-out structure located on the surface of the source line region, the source line lead-out structure being connected to the source line region through an ohmic contact.
5. The memory structure according to claim 1, characterized in that, Further comprising: A bit line lead-out structure located on the surface of the bit line region, the bit line lead-out structure being located on one side of the word line gate, and the bit line lead-out structure being connected to the bit line region through an ohmic contact.
6. The memory structure according to claim 1, wherein Further comprising: A first oxide layer located between the substrate and the channel structure, and a second oxide layer located on the surface of the channel structure, the floating gate, the word line gate, and the erase gate being located on the surface of the second oxide layer.
7. The memory structure according to claim 1, wherein Further comprising: An interlayer dielectric layer located on the substrate, the interlayer dielectric layer being located on the surfaces of the erase gate, the floating gate, the control gate structure, and the word line gate.
8. The memory structure according to claim 1, wherein, The control gate structure includes: a control gate dielectric layer located on the top surface of the floating gate, a control gate layer located on the surface of the control gate dielectric layer, and a control gate sidewall located on the sidewall surface of the control gate layer.
9. The memory structure according to claim 8, wherein, The control gate dielectric layer and the control gate sidewall include a third dielectric layer located on the sidewall surface and the bottom surface of the control gate layer, a first dielectric layer located on the surface of the third dielectric layer, and a second dielectric layer located between the first dielectric layer and the third dielectric layer, and the material of the second dielectric layer is different from the materials of the first dielectric layer and the third dielectric layer.
10. The memory structure according to claim 9, wherein, Further comprising: A covering layer located on the top surface of the control gate layer.
11. The memory structure according to claim 10, wherein Further comprising: First conductive plugs respectively located on the top surfaces of the word line gate and the erase gate; A second conductive plug penetrating through the covering layer, the second conductive plug being located on the top surface of the control gate layer.
12. The memory structure according to claim 1, characterized in that, The sidewall of the floating gate protrudes compared to the sidewall of the control gate layer; the bottom surface of the erase gate is recessed towards the top of the erase gate, and the angle formed by the bottom surface and the sidewall surface of the erase gate is an acute angle.
13. A method for forming a memory structure, characterized in that Comprising: Providing a substrate; Forming a channel structure on the substrate, the channel structure including a bit line region and a source line region, and the material of the channel structure including transition metal sulfide; Forming a floating gate on the source line region, the material of the floating gate including graphene material; Forming a control gate structure on the floating gate; Forming a word line gate and an erase gate on the source line region, the floating gate being located between the erase gate and the word line gate; Forming a bit line on the bit line region.
14. The method for forming the memory structure according to claim 13, wherein, After forming the channel structure, further comprising: forming a source line lead-out structure on the surface of the source line region, the source line lead-out structure being connected to the source line region through an ohmic contact.
15. The method for forming the memory structure according to claim 14, wherein After forming the channel structure, the method further includes: forming a bit line lead-out structure on the surface of the bit line region, the bit line lead-out structure being located on one side of the word line gate, and the bit line lead-out structure being connected to the bit line region through an ohmic contact.
16. The method for forming the memory structure according to claim 15, wherein Before forming the channel structure, the method further includes: forming a first oxide layer between the substrate and the channel structure, and forming a second oxide layer on the surface of the channel structure, with the floating gate, word line gate, and erase gate located on the surface of the second oxide layer.
17. The method for forming a memory structure according to claim 13, wherein After forming the erase gate, floating gate, control gate structure, and word line gate, the method further includes: forming an interlayer dielectric layer on the substrate, the interlayer dielectric layer being located on the surfaces of the erase gate, floating gate, control gate structure, and word line gate.
18. The method for forming the memory structure according to claim 13, wherein, The control gate structure includes: a control gate dielectric layer on the top surface of the floating gate, a control gate layer on the surface of the control gate dielectric layer, a capping layer on the top surface of the control gate layer, and a control gate sidewall on the sidewall surfaces of the control gate layer, the capping layer, and the control gate dielectric layer sidewall.
19. The method for forming the memory structure according to claim 18, wherein, The method of forming the floating gate and control gate structure includes: forming a floating gate layer on the channel structure; forming a control gate dielectric material layer on the top surface of the floating gate layer; forming an initial control gate layer on the surface of the control gate dielectric material layer; forming a capping layer on the top surface of the initial control gate layer; etching the initial control gate layer and the control gate dielectric material layer using the capping layer as a mask to form a control gate, the control gate including a control gate layer and a control gate dielectric layer; forming a control gate sidewall on the sidewall surface of the control gate; etching the floating gate layer using the control gate sidewall and the control gate as a mask to form a floating gate on the channel structure.
20. The method for forming the memory structure according to claim 17, wherein, After forming the interlayer dielectric layer, the method further includes: etching the interlayer dielectric layer until the top surfaces of the word line gate and the erase gate are exposed to form a first groove; forming a first conductive plug in the first groove; etching the interlayer dielectric layer and the capping layer until the top surface of the control gate layer is exposed to form a second groove; forming a second conductive plug in the second groove, the second conductive plug being located on the top surface of the control gate layer.