FPGA-based real-time monitoring and fault intelligent processing system for high-voltage power systems

Abstract

The present invention relates to the field of power system monitoring and protection technology, and discloses an FPGA-based real-time monitoring fault intelligent processing system for a strong power system, the system comprising: a pulse encoding module for converting the monitored voltage or current signal into a time-domain pulse sequence; a hardware pulse neural network module for processing the pulse sequence to generate a local warning state vector; a distributed consensus engine module for combining the local vectors of multiple nodes to generate a global warning state vector through consensus; a parameter adaptive adjustment module for adjusting the response characteristics of the neural network according to global vector feedback; a collaborative decision-making and intelligent control module for executing a collaborative strategy to handle potential faults when the global warning reaches a threshold. The present invention can detect weak fault precursors with extremely low latency and high sensitivity, and through distributed collaboration, improves the global reliability and intelligent processing capabilities for coping with systemic risks.

Description

Technical Field

[0001] The present invention relates to the technical field of power system monitoring and protection, and in particular to an FPGA-based strong power system real-time monitoring fault intelligent processing system. Background Art

[0002] The safety and stability of power grids are crucial. Early warning signs of faults in the power grid, such as those caused by aging equipment, are weak and fleeting. If not captured and accurately identified in real time, they can easily lead to cascading failures.

[0003] Existing technology solutions generally use architectures based on digital signal processors (DSPs) or general-purpose processors (CPUs), relying on high-speed sampling and software algorithms for feature analysis and fault diagnosis. In some advanced applications, data from multiple monitoring points is uploaded to a central server for comprehensive analysis.

[0004] However, this technical approach has inherent flaws. Its software-based serial processing mode introduces significant latency, making it difficult to meet the real-time response requirements for microsecond-level transient disturbances. Furthermore, its analysis method focuses on signal amplitude and is not sensitive enough to the complex temporal dynamic information that better characterizes the fault evolution process. More critically, existing devices are mostly centralized or deployed in isolation, lacking efficient real-time information sharing and consensus mechanisms between monitoring points. This makes it difficult to correlate and analyze multi-point anomalies from a global perspective, and difficult to make rapid and coordinated judgments and controls on global risks.

[0005] Compared with existing technologies:

[0006] A search revealed that Chinese patent application CN118377644B discloses an FPGA-based method and system for rapidly improving CPU fault diagnosis. This technology utilizes an FPGA as an external monitoring unit, monitoring the CPU's watchdog signal interval, temperature, utilization, and core dump logs received via the UART port in real time to determine whether the CPU is stuck or faulty. When a fault is detected, the FPGA transfers detailed log information from internal BRAM to external SPI flash for permanent storage. The FPGA then controls the watchdog chip to safely reset the CPU and provide the CPU with a fault log for analysis after a reboot.

[0007] The technical comparison between the above application and this application is as follows:

[0008] This application discloses an FPGA-based method and system for rapidly improving CPU fault diagnosis, applied in the field of computer hardware and system diagnostics. Its core approach is to use the FPGA as an external monitoring unit for the CPU, addressing the problem of effectively preserving on-site logs and performing a safe restart after the CPU freezes or crashes. This technology focuses on the CPU's operating status, processing digital logic signals such as dog feed signals and system logs. Its technical approach is based on state machine logic and log caching and transfer.

[0009] This application is a fault prevention and intelligent processing system applied to high-voltage power systems. Its core is to use the parallel computing capability of FPGA and pulse neural network module technology to solve the problem that weak, transient early fault precursor signals in the power grid are difficult to capture in real time and accurately identify. This application focuses on physical analog signals such as voltage and current in the power grid, and uses pulse coding and hardware pulse neural networks to perform complex timing pattern recognition. More importantly, this application proposes a distributed consensus mechanism, which aims to integrate information from multiple monitoring points to form a global judgment and perform predictive collaborative control, which falls into the category of active prevention and system-level collaboration.

[0010] While both utilize FPGAs, they differ fundamentally in their application areas, technical problems addressed, core technical approaches, and system objectives. The previous application focused on passive, reactive fault diagnosis for a single computing unit, while this application addresses a predictive, proactive fault precursor analysis and collaborative processing system for the entire power grid.

[0011] A search revealed that Chinese patent application CN114610551A discloses a method for implementing a dual-machine hot standby system based on FPGA fault detection. This technology integrates FPGA modules on both the master and slave computers, enabling millisecond-level rapid detection of hardware status (such as voltage, temperature, and power-up timing) and software status (such as operating system interrupt responses and critical processes). When a master computer fails, its FPGA or the slave computer's FPGA can quickly detect the fault and trigger an IP address migration, allowing the slave computer to take over. This achieves faster system hot standby switching than traditional software heartbeat solutions.

[0012] The technical comparison between the above application and this application is as follows:

[0013] This application discloses a dual-machine hot standby solution for fault detection. Its core technology utilizes an FPGA as a hardware monitoring unit to rapidly switch to a backup server after a hardware or software crash on the primary server in a computer system. By monitoring deterministic signals such as interrupt responses and hardware sensor values, this solution achieves millisecond-level fault detection and service takeover, ensuring service continuity.

[0014] This application is a fault precursor monitoring and intelligent processing system applied to high-voltage power systems. Its technical core is to use FPGA to implement a pulse neural network module to conduct in-depth analysis of complex analog waveforms such as voltage and current in the power grid, aiming to identify weak and non-deterministic precursor features before a fault occurs. This application is not concerned with backup switching after equipment failure, but with the prediction and location of potential power grid faults through collaborative analysis and consensus judgment of distributed monitoring points. It is a proactive and predictive safety assurance technology.

[0015] Therefore, there are essential differences between the two in terms of application scenarios, technical contradictions resolved, and core implementation mechanisms. The previous application is aimed at high availability of information systems and is a rapid response mechanism after a failure occurs; the present application is aimed at power physical systems and is a precursor warning and coordinated prevention mechanism before a failure occurs.

[0016] After searching, the invention patent with Chinese publication number CN112101517B discloses an FPGA implementation method based on a piecewise linear spiking neural network. The core of this technology is to solve the problem of how to maintain low hardware resource consumption and high computational efficiency when hardware-based general spiking neural networks while minimizing the loss of the biodynamic characteristics of the neuron model. To this end, it proposes the use of a two-dimensional piecewise linear spiking neuron model and, through discretization processing and the design of pipeline arithmetic logic, elaborates on the specific circuit implementation scheme for mapping this specific neuron model and its network topology onto the FPGA. In essence, it is a fundamental method for the hardwareization of neural networks.

[0017] The technical solution of this application is a fault precursor monitoring and intelligent processing system applied to high-voltage power systems. Its technical core is to use a pulse neural network implemented by FPGA to conduct in-depth analysis and feature recognition of complex analog waveforms such as voltage and current in the power system. The focus of this application is not the implementation method of the neural network itself, but to build a collaborative monitoring system composed of distributed monitoring points. Through data analysis and consensus judgment of each monitoring point, it can predict and locate the weak and non-deterministic precursor characteristics before the occurrence of potential power grid faults. It is a predictive safety assurance technology.

[0018] Therefore, there are essential differences between the two in terms of technology and the problems they solve. This application belongs to the field of neural network hardware implementation, which is committed to providing a more efficient and realistic general-purpose pulse neural network hardware building block, focusing on the model-to-circuit mapping method. This application is a specific engineering application system that uses pulse neural networks as a core analysis tool and applies it to the specific scenario of power physical system safety monitoring. Its innovation lies in the overall architecture of the system and the application mode of using pulse neural networks for fault precursor analysis.

[0019] Therefore, the present invention proposes a FPGA-based high-voltage system real-time monitoring fault intelligent processing system to address the deficiencies of the prior art. Summary of the Invention

[0020] In response to the shortcomings of the existing technology, the present invention provides an FPGA-based real-time monitoring and intelligent fault processing system for high-voltage power systems, which solves the problems of high processing delay, insufficient feature extraction and insufficient multi-node collaborative decision-making capabilities in the existing FPGA-based high-voltage power system monitoring when facing nonlinear and transient complex fault precursors.

[0021] To achieve the above objectives, the present invention is implemented through the following technical solutions:

[0022] The first aspect of the present invention provides an FPGA-based high-voltage system real-time monitoring fault intelligent processing system, which includes:

[0023] Pulse coding module, hardware pulse neural network module, distributed consensus engine module, parameter adaptive adjustment module and collaborative decision-making and intelligent control module;

[0024] The pulse encoding module serves as the signal input stage, and its output is connected to the hardware pulse neural network module. The output of the hardware pulse neural network module is connected to the distributed consensus engine module. The output of the distributed consensus engine module is divided into two paths, connected to the parameter adaptive adjustment module and the collaborative decision-making and intelligent control module respectively. The output of the parameter adaptive adjustment module is fed back to the hardware pulse neural network module to form a closed-loop regulation circuit.

[0025] The pulse encoding module is used to monitor the high-voltage system in real time and receive the monitored voltage or current signal, and then convert it into a time-domain pulse sequence that represents the dynamic changes of the signal;

[0026] a hardware pulse neural network module for processing the time-domain pulse sequence in real time to identify a preset fault precursor pattern and generate a local warning state vector accordingly;

[0027] A distributed consensus engine module is configured to receive a local warning state vector generated by the hardware pulse neural network module and generate a global warning state vector through a consensus protocol in combination with the local warning state vector received from at least one other node;

[0028] a parameter adaptive adjustment module, receiving the global warning state vector and dynamically adjusting internal parameters of the hardware pulse neural network module according to the global warning state vector, thereby adjusting the response characteristics of the hardware pulse neural network module to the corresponding time domain pulse sequence;

[0029] The collaborative decision-making and intelligent control module is used to execute a preset collaborative control strategy to intelligently handle potential faults when the global warning state vector reaches a preset control execution threshold.

[0030] In an optional embodiment, the pulse coding module adopts a time contrast coding mechanism. When the change amount of the received signal at adjacent sampling moments is Exceeds the preset encoding sensitivity threshold When , pulses are emitted, where ;

[0031] Where, Indicates that at the current discrete sampling moment The sampled value of the voltage or current signal obtained; Indicates that at the previous discrete sampling moment The sampled value of the voltage or current signal is obtained; Represents the sampling point index of discrete time; Represents absolute value operation.

[0032] In an optional embodiment, the hardware spiking neural network module is composed of a plurality of leaky integration and release neurons, specifically configured to:

[0033] receiving the time-domain pulse train and weighting the received pulses based on preset synaptic weights to accumulate a membrane potential within the leaky integrate-and-send neuron, wherein the preset synaptic weights are determined by offline training on sample data including known prefault patterns;

[0034] When the membrane potential of any neuron in the leaky integral firing neurons reaches a preset firing threshold, the neuron fires an output pulse, and the firing behavior of the corresponding output neuron in the hardware pulse neural network module represents the recognition of a preset fault precursor pattern;

[0035] The initial value of the preset release threshold is determined based on the offline training;

[0036] The preset fault precursor mode is at least one of the following:

[0037] Partial discharge patterns associated with insulation aging in power equipment;

[0038] transient disturbance modes associated with mechanical loosening of electrical connection points;

[0039] Ultra-high frequency noise patterns associated with switching anomalies in power electronics devices.

[0040] In an optional embodiment, the membrane potential of the leaky integrated firing neuron The dynamic changes satisfy the following relationship:

[0041] ;

[0042] in, is the membrane time constant; is the instantaneous rate of change of membrane potential; is the resting potential; is the membrane resistance; Indicates that at consecutive time points , indexed by The total synaptic input current received by the neuron.

[0043] In an optional embodiment, the distributed consensus engine module is specifically used to:

[0044] Receiving the local warning state vector generated by the hardware pulse neural network module;

[0045] receiving a local warning state vector of the at least one other node by communicating with the at least one other node;

[0046] Based on receiving the local warning state vector generated by the hardware pulse neural network module and the local warning state vector of the at least one other node, a deterministic consensus protocol is executed to reach a consistent judgment on the warning state among all participating nodes, thereby generating the global warning state vector.

[0047] In an optional embodiment, the distributed consensus engine module communicates with the other nodes via a high-speed optical fiber network to receive local warning status vectors from the other nodes.

[0048] In an optional embodiment, the parameter adaptive adjustment module is specifically configured to:

[0049] Receiving the global warning state vector;

[0050] Determining a parameter adjustment strategy based on the received global warning state vector, and generating an adjustment instruction for adjusting internal parameters of the hardware spiking neural network module accordingly, wherein the adjustment instruction is specifically a modulation matrix for adjusting synaptic weights, or an adjustment value for adjusting a neuron firing threshold;

[0051] The generated adjustment instruction is applied to the hardware pulse neural network module, and the synaptic weight is updated by performing matrix multiplication or matrix addition operation on the original synaptic weight matrix and the modulation matrix, or the firing threshold is updated by applying the adjustment value to the original firing threshold, thereby adjusting the response characteristics of the hardware pulse neural network module to the corresponding time domain pulse sequence.

[0052] A second aspect of the present invention provides an FPGA-based method for intelligently processing faults in a real-time monitoring system of a strong electric power system, comprising the following steps:

[0053] Monitor the power system in real time and receive the monitored voltage or current signal, and then convert it into a time domain pulse sequence that represents the dynamic changes of the signal;

[0054] Processing the time domain pulse sequence in real time to identify a preset fault precursor pattern and generating a local warning state vector accordingly;

[0055] Receive a local warning state vector generated by the hardware pulse neural network module, and combine it with the local warning state vector received from at least one other node to generate a global warning state vector through a consensus protocol;

[0056] Receiving the global warning state vector, and dynamically adjusting internal parameters of the hardware pulse neural network module according to the global warning state vector, thereby adjusting the response characteristics of the hardware pulse neural network module to the corresponding time domain pulse sequence;

[0057] When the global warning state vector reaches a preset control execution threshold, a preset collaborative control strategy is executed to intelligently handle potential faults.

[0058] The present invention provides an FPGA-based high-voltage system real-time monitoring fault intelligent processing system. It has the following beneficial effects:

[0059] 1. This invention implements pipelined processing of high-voltage network signals by integrating functional units such as the pulse encoding module, hardware pulse neural network module, and collaborative decision-making and intelligent control module into the FPGA's hardware logic, leveraging its inherent parallel processing capabilities. This hardware-based architecture avoids the overhead of instruction execution and task scheduling in software processing. Combined with the event-driven nature of the hardware pulse neural network, it significantly reduces data processing latency and ensures real-time monitoring of fault precursors.

[0060] 2. By directly analyzing time-domain pulse sequences using a hardware pulse neural network, the present invention effectively captures the temporal dynamic information contained in transient disturbance signals associated with equipment insulation aging or mechanical loosening in high-voltage power networks, enabling accurate identification of fault precursor patterns. Furthermore, by incorporating an adaptive parameter adjustment module, the internal parameters of the neural network can be dynamically adjusted based on the global warning status, enabling the monitoring device to adaptively adjust its response characteristics. This significantly enhances the intelligent processing capabilities of fault identification in complex electromagnetic environments.

[0061] 3. By implementing a distributed consensus engine module, the present invention allows multiple monitoring nodes deployed in different locations to fuse their individually generated local warning state vectors. By executing a consensus protocol, a more reliable and comprehensive global warning state vector is generated. This method effectively avoids misjudgments caused by information deviations from individual nodes. Based on this global state, the collaborative decision-making and intelligent control modules can implement collaborative control strategies, achieving a transition from single-point response to multi-point collaborative intelligent processing, thereby more effectively addressing and suppressing potential cascading failures. BRIEF DESCRIPTION OF THE DRAWINGS

[0062] Figure 1 This is the architecture diagram of the FPGA-based high-voltage system real-time monitoring fault intelligent processing system of the present invention;

[0063] Figure 2 Schematic diagram of the structure of the pulse coding module of the present invention;

[0064] Figure 3 This is a schematic diagram of the hardware pulse neural network module structure of the present invention;

[0065] Figure 4 This is a schematic diagram of the distributed consensus engine module structure of the present invention;

[0066] Figure 5 Schematic diagram of the structure of the parameter adaptive adjustment module of the present invention;

[0067] Figure 6 This is a schematic diagram of the structure of the collaborative decision-making and intelligent control module of the present invention;

[0068] Figure 7 This is a flow chart of the FPGA-based high-voltage system real-time monitoring fault intelligent processing method of the present invention.

[0069] Among them, 10. Pulse coding module; 20. Hardware pulse neural network module; 30. Distributed consensus engine module; 40. Parameter adaptive adjustment module; 50. Collaborative decision-making and intelligent control module. DETAILED DESCRIPTION

[0070] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the drawings in the present specification. Obviously, the embodiments described are only part of the embodiments of the present invention, not all of the embodiments. All other embodiments obtained by ordinary technicians in this field based on the embodiments of the present invention without making any creative efforts shall fall within the scope of protection of the present invention.

[0071] Refer to the attached Figure 1 , Figure 1The following is an architecture diagram of an FPGA-based system for real-time monitoring and intelligent fault processing of a high-voltage power system, according to one embodiment of the present invention. The present invention provides an FPGA-based system for real-time monitoring and intelligent fault processing of a high-voltage power system. The system may include: a pulse encoding module 10, a hardware pulse neural network module 20, a distributed consensus engine module 30, a parameter adaptive adjustment module 40, and a collaborative decision-making and intelligent control module 50. In one embodiment, all of the above modules are implemented using FPGA hardware logic.

[0072] A complete data processing and feedback path is formed between the modules of the system. The pulse encoding module 10 serves as the signal input stage, and its output is connected to the hardware pulse neural network module 20. The output of the hardware pulse neural network module 20 is connected to the distributed consensus engine module 30. The output of the distributed consensus engine module 30 is divided into two paths, connected to the parameter adaptive adjustment module 40 and the collaborative decision-making and intelligent control module 50 respectively. Among them, the output of the parameter adaptive adjustment module 40 is fed back to the hardware pulse neural network module 20, forming a closed-loop regulation circuit.

[0073] The overall workflow of the system is as follows: First, the monitored high-voltage system signal is converted into a pulse sequence by the pulse encoding module 10. Then, the hardware pulse neural network module 20 processes this sequence to generate local warning information. Next, the distributed consensus engine module 30 integrates the warning information of multiple nodes to form a global state judgment. Finally, based on this global state, the collaborative decision-making and intelligent control module 50 performs external control, while the parameter adaptive adjustment module 40 performs internal optimization on the hardware pulse neural network module 20.

[0074] Refer to the attached Figure 2 , Figure 2 Figure 1 is a schematic diagram of the structure of a pulse encoding module according to one embodiment of the present invention. This pulse encoding module 10 serves as the data input and preprocessing unit for the entire FPGA-based high-voltage system real-time fault monitoring and intelligent processing system. Its core function is to receive a sequence of discrete sampled values ​​representing the voltage or current of the high-voltage system from an external ADC (analog-to-digital converter) and convert them into a time-domain pulse sequence that reduces data volume and better characterizes the dynamic changes in the signal.

[0075] In one specific embodiment, the pulse encoding module 10 employs a time-contrast encoding mechanism. This mechanism operates by assuming a valid event has occurred and issuing a pulse only when the change between the current sampled value of the monitored signal and the previous sampled value is sufficiently large. This event-driven encoding approach provides highly sparse input data for subsequent intelligent fault processing, significantly reducing the computational load of subsequent modules.

[0076] The pulse encoding module 10 calculates the absolute value of the signal sampling value at adjacent sampling moments and compare it with the encoding sensitivity threshold Comparison is made to determine whether to issue a pulse. The calculation process is determined by the following relationship:

[0077] ;

[0078] Where, Indicates that at the current discrete sampling moment The sampled value of the voltage or current signal is obtained; Indicates that at the previous discrete sampling moment The sampled value of the voltage or current signal is obtained; Represents the sampling point index of discrete time, which is a positive integer; Represents absolute value operation.

[0079] Encoding sensitivity threshold Is a key parameter, and its value is used to define the significance of signal changes. The setting of this threshold enables the module to effectively ignore low-amplitude, non-information-valued signal fluctuations such as background noise of the power system, and only respond to drastic signal changes such as partial discharge and transient disturbances that may indicate potential faults. In one embodiment, the threshold The value of can be determined based on a statistical analysis of the background noise signal under historical normal operating conditions (for example, calculating three times or five times its standard deviation) and can be configured in a dedicated parameter register.

[0080] At the FPGA hardware logic implementation level, the pulse encoding module 10 can be composed of the following units:

[0081] Input data interface, used to receive sample values ​​from ADC ; Data register, used to latch the current sampling value after each clock cycle , so that the next clock cycle can be used as the sampling value of the previous moment Use; fixed-point subtractor for calculation ; a logic judgment unit for obtaining the absolute value of the difference; and a digital comparator for converting the calculated with the threshold value stored in the parameter register When the comparison result is When , the output of this module generates a time domain pulse train with a width of one clock cycle.

[0082] Refer to the attached Figure 3 , Figure 3Figure 2 is a schematic diagram of the hardware pulse neural network module structure according to one embodiment of the present invention. This hardware pulse neural network module 20 performs the core pattern recognition function in the FPGA-based high-voltage system real-time monitoring and fault intelligent processing system. Its input receives the time-domain pulse sequence from the pulse encoding module 10, processes this sequence in real time through internal parallel computing to identify preset fault precursor patterns, and ultimately generates a local warning state vector at its output.

[0083] In one embodiment, the hardware spiking neural network module 20 is composed of multiple leaky integrate-and-fire (LIF) neurons, which are organized into a feedforward network structure within the FPGA, for example, including an input layer, one or more hidden layers, and an output layer. The connections between neurons are defined by a preset synaptic weight matrix. When a pulse from a previous neuron or the pulse encoding module 10 reaches a neuron, the pulse is weighted based on the corresponding synaptic weight and used to update the membrane potential within the neuron.

[0084] The initial values ​​of the synaptic weights and the firing thresholds of the neurons are not randomly set, but are determined through offline training of sample data including known fault precursor patterns. These sample data may include: local discharge patterns related to insulation aging of power equipment; transient disturbance patterns related to mechanical looseness of electrical connection points; and ultra-high frequency noise patterns related to abnormal switching of power electronic devices. Through this training process, the network learns to map specific input time domain pulse sequence patterns to the firing behavior of specific output neurons. Therefore, the firing of specific output neurons in the hardware pulse neural network module 20 represents the successful recognition of a preset fault precursor pattern.

[0085] At the physical model level, the membrane potential of each leaky integrated neuron The dynamic change process satisfies the following relationship:

[0086] ;

[0087] in, is the membrane time constant, which determines the rate at which the membrane potential leaks toward the resting potential; is the instantaneous rate of change of membrane potential; is the resting potential, which is the stable membrane potential value of the neuron when there is no input; is the membrane resistance, which represents the magnitude of the effect of synaptic input current on membrane potential; Indicates that at consecutive time points , indexed by The total synaptic input current received by the neuron.

[0088] This formula describes two core processes: leakage of the membrane potential (given by the term Reflection) and points accumulated through the points process reach the preset issuance threshold , the neuron fires an output pulse, and then its membrane potential is reset to the reset potential (e.g., ), and enter the next integration cycle. This mechanism enables neurons to respond not only to the presence or absence of input, but also to the temporal dynamics of the input pulse, thus providing a basis for accurately identifying transient fault precursors in high-voltage power systems.

[0089] To implement it in the discrete-time digital logic of the FPGA, the continuous-time differential equations are discretized using numerical methods such as the Euler method. Inside the FPGA, each LIF neuron can be implemented by a dedicated computational unit that includes: , resting potential and issuance threshold Registers for storing synaptic weights (e.g., BRAMs); fixed-point arithmetic logic units (such as adders and multipliers) for computing discretized equations; and digital comparators for comparing membrane potential with thresholds. Thanks to the parallel nature of FPGAs, membrane potential updates, threshold comparisons, and spike firing for all neurons in the network can be completed synchronously within each clock cycle. This ensures extremely low-latency processing of input spike trains, which is key to achieving real-time fault monitoring and intelligent processing.

[0090] Refer to the attached Figure 4 , Figure 4 Figure 3 is a schematic diagram of the distributed consensus engine module structure according to one embodiment of the present invention. This distributed consensus engine module 30 is a key unit for achieving multi-node information fusion and global situational awareness within the FPGA-based high-voltage system real-time monitoring and fault intelligent processing system. Its function is to elevate localized warning information generated by a single node into a global status assessment that is agreed upon by all participating nodes.

[0091] In a specific embodiment, the module's input receives the local warning state vector generated by the hardware pulse neural network module 20 within the system. At the same time, the module integrates a high-speed communication interface. In a preferred embodiment, this interface communicates with the distributed consensus engine module of at least one other identically configured monitoring node deployed elsewhere in the power system via a high-speed fiber optic network to receive the other party's local warning state vector. The use of a high-speed fiber optic network for inter-node communication ensures high bandwidth and low latency for vector data transmission, which is the basis for achieving rapid consensus and ensuring the real-time performance of the system.

[0092] The core function of the distributed consensus engine module 30 is to execute a deterministic consensus protocol. This protocol aims to achieve a consistent judgment of the grid warning status across all participating nodes based on the local warning status vector of the node and the received local warning status vectors of all other nodes. This eliminates misjudgments or missed judgments that could be caused by sensor noise, local electromagnetic interference, or model bias at a single node.

[0093] The consensus protocol is implemented within the FPGA using a dedicated state machine and computational unit. Its workflow includes the following steps: First, after receiving the local warning state vector from its own node, the module broadcasts this vector to all other participating nodes via a high-speed fiber optic network. Simultaneously, it continuously listens for and receives vectors from other nodes, storing them in an internal buffer memory.

[0094] Secondly, after the local warning state vectors of all participating nodes are collected within a preset synchronization time window, the consensus protocol is triggered. In one embodiment, this deterministic protocol can be an element-by-element deterministic calculation of all received state vectors (including the vector of the local node). For example, for each element in the vector (which corresponds to the alarm level of a specific prefault pattern), the arithmetic mean or maximum value of all nodes on that element is calculated to generate the value of the corresponding element in the global warning state vector. Because all nodes execute the same input collection and calculation logic, it is guaranteed that all nodes will generate the same global warning state vector within the same time window.

[0095] Ultimately, the module generates a unique global warning state vector, which, compared to any single local warning state vector, more comprehensively and accurately reflects the macroscopic safety status of the entire power system.

[0096] Refer to the attached Figure 5 , Figure 5 Figure 4 is a schematic diagram of the structure of a parameter adaptive adjustment module according to one embodiment of the present invention. This parameter adaptive adjustment module 40 constitutes a critical feedback loop within the entire FPGA-based high-voltage system real-time monitoring and intelligent fault processing system. Its core function is to dynamically adjust the internal parameters of the hardware pulse neural network module 20 based on the system's current global warning state, thereby adjusting its response characteristics to specific time-domain pulse sequences, enabling the system to adapt and improving the intelligent processing level of fault identification.

[0097] In one specific embodiment, the input of the adaptive parameter adjustment module 40 receives a global warning state vector generated by the distributed consensus engine module 30. This module internally includes a parameter adjustment strategy determination unit and an adjustment instruction generation unit. The parameter adjustment strategy determination unit monitors the input global warning state vector in real time. When certain elements or combinations of these elements meet preset trigger conditions (for example, the warning level of a specific fault mode increases for multiple consecutive cycles), the unit determines a corresponding parameter adjustment strategy based on a preset mapping relationship.

[0098] According to the determined parameter adjustment strategy, the adjustment instruction generation unit then generates an adjustment instruction for adjusting the internal parameters of the hardware pulse neural network module 20. In one embodiment, the adjustment instruction is specifically expressed in one of the following two forms: one is a modulation matrix for adjusting the synaptic weight ; The other is the adjustment value used to adjust the neuron firing threshold .

[0099] The adjustment instruction is output to the parameter control terminal of the hardware pulse neural network module 20 to update its internal parameters in an online manner. The update process is as follows:

[0100] When the adjustment instruction is the modulation matrix When the original synaptic weight matrix in the hardware pulse neural network module 20 is With the modulation matrix Perform matrix multiplication or matrix addition to generate the updated synaptic weight matrix The process can be expressed by the following relationship:

[0101] or ;

[0102] Where, is the updated synaptic weight matrix; is the original synaptic weight matrix before updating; The modulation matrix generated by the parameter adaptive adjustment module; Represents the Hadamard product (element-wise multiplication) of matrices.

[0103] When the adjustment instruction is the adjustment value By applying this adjustment value to the original release threshold To update the firing threshold. For example, for a group or all neurons, the updated firing threshold It can be determined by the following relationship:

[0104] ;

[0105] Where, The threshold for the updated neuron firing; is the firing threshold of the original neuron before updating; The parameter adaptive adjustment module generates the adjustment value. In the FPGA hardware implementation, the parameter adaptive adjustment module 40 can be composed of a control logic unit, a lookup table (LUT) or block memory (BRAM) for storing the preset adjustment strategy, and a fixed-point arithmetic operation unit. The control logic unit queries the LUT to obtain the corresponding modulation matrix according to the value of the input global warning state vector. or adjust the value , and then the arithmetic operation unit performs the above-mentioned matrix or scalar operation, and writes the result to the corresponding register or memory storing weights and thresholds in the hardware pulse neural network module 20 through a dedicated data bus to complete the real-time update of the parameters.

[0106] Refer to the attached Figure 6 , Figure 6 Figure 5 is a schematic diagram of the collaborative decision-making and intelligent control module structure according to one embodiment of the present invention. This collaborative decision-making and intelligent control module 50 is the final execution output unit of the entire FPGA-based high-voltage system real-time monitoring and intelligent fault handling system. Its function is to execute a preset collaborative control strategy when the system's global warning status reaches a critical condition, proactively intervening in and intelligently handling potential faults.

[0107] In a specific embodiment, the input end of the module receives a global warning state vector generated by the distributed consensus engine module 30. The module monitors the global warning state vector in real time and continuously compares it with a preset control execution threshold. The control execution threshold here is not an empirical value, but is determined based on the safety and stability margin analysis of the monitored high-voltage power network. It numerically represents the upper limit of the warning state before the system evolves into an unstable state. The threshold is pre-calculated and stored in a dedicated register or memory inside the module.

[0108] When the value of the global warning state vector reaches the preset control execution threshold, indicating that one or more key indicators of the system are approaching their safety boundaries, the collaborative decision-making and intelligent control module 50 is immediately triggered and generates and outputs specific control instructions according to the preset collaborative control strategy. The collaborative control strategy is pre-designed to respond to different fault precursors. In one embodiment, the strategy is at least one of the following:

[0109] Predictive power flow reconstruction: This module executes this strategy when the global warning state vector indicates a potential line overload or voltage overlimit risk. It generates a set of control instructions and sends them to switchgear (such as circuit breakers and disconnectors) in the power grid. By changing the grid's operating topology, it shifts power flows from high-risk lines to others with greater margins, proactively mitigating failures.

[0110] Active Damping Injection: This module executes this strategy when the global warning state vector indicates a precursor to stability issues, such as low-frequency oscillations, in the system. It generates control instructions and sends them to the Flexible AC Transmission System (FACTS) or energy storage system in the system, instructing them to inject or absorb power of a specific phase and amplitude into the grid to generate a damping torque in the opposite direction of the system oscillations, thereby quickly suppressing the oscillations and improving the system's dynamic stability.

[0111] Online Protection Setting Adjustment: This module implements this strategy when the global warning status vector clearly identifies a specific type of fault precursor (such as partial discharge associated with insulation aging). It generates new protection setting parameters and sends them to the digital protection relays in the relevant line or equipment area via the communication network. These relays then adjust their protection settings (such as the pickup threshold or delay) online, making the protection system more sensitive and accurate in responding to specific impending fault types, ensuring rapid and selective fault clearance when they occur.

[0112] At the FPGA hardware implementation level, the collaborative decision-making and intelligent control module 50 consists of a digital comparator array, a control logic state machine (FSM), and a block RAM (BRAM) for storing the collaborative control strategy instruction set. The digital comparator array continuously compares the input global warning state vector with the stored control execution threshold. Once the comparison condition is met, the FSM is triggered and reads the corresponding preset control instruction sequence from the BRAM based on the specific content of the global vector. It then sends this sequence to the external control execution unit through the module's output interface.

[0113] Refer to the attached Figure 7 , Figure 7 This is a flow chart of an FPGA-based intelligent fault processing method for real-time monitoring of a high-voltage power system according to one embodiment of the present invention. This method aims to provide a complete processing flow from signal acquisition to intelligent control, implemented on FPGA hardware. The method specifically includes the following steps:

[0114] S1. Monitor the high-voltage system in real time and receive the monitored voltage or current signal, and then convert it into a time-domain pulse sequence that represents the dynamic change of the signal;

[0115] In one embodiment, this step is performed by the aforementioned pulse encoding module 10. This module performs time-contrast encoding on consecutive signal samples and generates a pulse only when the signal change amplitude exceeds a preset encoding sensitivity threshold, thereby converting the original dense data stream into a sparse, event-driven pulse sequence.

[0116] S2. Processing the time domain pulse sequence in real time to identify a preset fault precursor pattern and generating a local warning state vector accordingly;

[0117] In one embodiment, this step is performed by the aforementioned hardware spiking neural network module 20. This module utilizes an internal leaky integration firing neural network to weight and integrate the input pulse train. The firing behavior of specific output neurons in the network characterizes the recognition of a specific fault precursor pattern, and the combined firing state of these neurons constitutes the local warning state vector.

[0118] S3, receiving a local warning state vector generated by the hardware pulse neural network module, and combining it with the local warning state vector received from at least one other node to generate a global warning state vector through a consensus protocol;

[0119] In one embodiment, this step is performed by the aforementioned distributed consensus engine module 30. This module exchanges local warning state vectors with other nodes via a high-speed communication network and executes a deterministic consensus protocol to calculate a global warning state vector that is completely consistent among all participating nodes, thereby obtaining a unified judgment on the status of the entire system.

[0120] After generating the global warning state vector, the method performs the following two steps, S4 and S5, in parallel:

[0121] S4. Receive the global warning state vector, and dynamically adjust internal parameters of the hardware pulse neural network module according to the global warning state vector, thereby adjusting the response characteristics of the hardware pulse neural network module to a specific time-domain pulse sequence;

[0122] In one embodiment, this step is performed by the aforementioned parameter adaptive adjustment module 40. This module generates adjustment instructions, such as a modulation matrix or adjustment values, based on the global warning state vector and a preset adjustment strategy. These instructions are used to online update the synaptic weights or neuron firing thresholds of the hardware spiking neural network module, thereby forming a closed-loop feedback loop that enables the system's recognition performance to adapt to changes in the grid's operating state.

[0123] S5. When the global warning state vector reaches a preset control execution threshold, a preset collaborative control strategy is executed to intelligently handle potential faults.

[0124] In one embodiment, this step is performed by the aforementioned collaborative decision-making and intelligent control module 50. This module compares the global warning state vector with a control execution threshold determined based on safety and stability margin analysis. Once the threshold is reached, collaborative control strategies such as predictive power flow reconstruction, active damping injection, or online adjustment of protection settings are immediately triggered and executed, outputting control instructions to external execution units to proactively intervene in potential faults.

[0125] While embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that various changes, modifications, substitutions, and variations may be made to these embodiments without departing from the principles and spirit of the invention, and that the scope of the invention is defined by the appended claims and their equivalents.

Claims

1. FPGA-based strong power system real-time monitoring fault intelligent processing system, characterized by: include: Pulse coding module, hardware pulse neural network module, distributed consensus engine module, parameter adaptive adjustment module and collaborative decision-making and intelligent control module; The pulse encoding module serves as the signal input stage, and its output is connected to the hardware pulse neural network module. The output of the hardware pulse neural network module is connected to the distributed consensus engine module. The output of the distributed consensus engine module is divided into two paths, connected to the parameter adaptive adjustment module and the collaborative decision-making and intelligent control module respectively. The output of the parameter adaptive adjustment module is fed back to the hardware pulse neural network module to form a closed-loop regulation circuit. The pulse encoding module is used to monitor the high-voltage system in real time and receive the monitored voltage or current signal, and then convert it into a time-domain pulse sequence that represents the dynamic changes of the signal; a hardware pulse neural network module for processing the time-domain pulse sequence in real time to identify a preset fault precursor pattern and generate a local warning state vector accordingly; A distributed consensus engine module is configured to receive a local warning state vector generated by the hardware pulse neural network module and generate a global warning state vector through a consensus protocol in combination with the local warning state vector received from at least one other node; a parameter adaptive adjustment module, receiving the global warning state vector and dynamically adjusting internal parameters of the hardware pulse neural network module according to the global warning state vector, thereby adjusting the response characteristics of the hardware pulse neural network module to the corresponding time domain pulse sequence; A collaborative decision-making and intelligent control module, configured to execute a preset collaborative control strategy to intelligently handle potential faults when the global warning state vector reaches a preset control execution threshold; The pulse coding module adopts the time contrast coding mechanism. When the received signal changes at adjacent sampling moments, Exceeds the preset encoding sensitivity threshold When , pulses are emitted, where ; Where, Indicates that at the current discrete sampling moment The sampled value of the voltage or current signal obtained; Indicates that at the previous discrete sampling moment The sampled value of the voltage or current signal obtained; Represents the sampling point index of discrete time; Indicates absolute value operation; The hardware pulse neural network module is composed of multiple leaky integration and release neurons, which are specifically used to: receiving the time-domain pulse train and weighting the received pulses based on preset synaptic weights to accumulate a membrane potential within the leaky integrate-and-send neuron, wherein the preset synaptic weights are determined by offline training on sample data including known prefault patterns; When the membrane potential of any neuron in the leaky integral firing neurons reaches a preset firing threshold, the neuron fires an output pulse, and the firing behavior of the corresponding output neuron in the hardware pulse neural network module represents the recognition of a preset fault precursor pattern; The initial value of the preset release threshold is determined based on the offline training; The preset fault precursor mode is at least one of the following: Partial discharge patterns associated with insulation aging in power equipment; transient disturbance modes associated with mechanical loosening of electrical connection points; Ultra-high frequency noise patterns associated with switching anomalies in power electronics devices; The membrane potential of the leaky integrated neuron The dynamic changes satisfy the following relationship: ； in, is the membrane time constant; is the instantaneous rate of change of membrane potential; is the resting potential; is the membrane resistance; Indicates that at consecutive time points , indexed by The total synaptic input current received by the neuron.

2. The FPGA-based strong power system real-time monitoring fault intelligent processing system according to claim 1 is characterized in that: The distributed consensus engine module is specifically used to: Receiving the local warning state vector generated by the hardware pulse neural network module; receiving, by communicating with at least one other node, a local warning state vector of the at least one other node; Based on receiving the local warning state vector generated by the hardware pulse neural network module and the local warning state vector of the at least one other node, a deterministic consensus protocol is executed to reach a consistent judgment on the warning state among all participating nodes, thereby generating the global warning state vector.

3. The FPGA-based strong power system real-time monitoring fault intelligent processing system according to claim 2 is characterized in that: The distributed consensus engine module communicates with the other nodes through a high-speed optical fiber network to receive local warning status vectors from the other nodes.

4. The FPGA-based strong power system real-time monitoring fault intelligent processing system according to claim 1 is characterized in that: The parameter adaptive adjustment module is specifically used for: Receiving the global warning state vector; Determining a parameter adjustment strategy based on the received global warning state vector, and generating an adjustment instruction for adjusting internal parameters of the hardware spiking neural network module accordingly, wherein the adjustment instruction is specifically a modulation matrix for adjusting synaptic weights, or an adjustment value for adjusting a neuron firing threshold; The generated adjustment instruction is applied to the hardware pulse neural network module, and the synaptic weight is updated by performing matrix multiplication or matrix addition operation on the original synaptic weight matrix and the modulation matrix, or the firing threshold is updated by applying the adjustment value to the original firing threshold, thereby adjusting the response characteristics of the hardware pulse neural network module to the corresponding time domain pulse sequence.

5. The FPGA-based strong power system real-time monitoring fault intelligent processing system according to claim 1 is characterized in that: The collaborative decision-making and intelligent control module is specifically used to: monitoring the global warning status vector in real time; Comparing the global warning state vector with a preset control execution threshold, wherein the control execution threshold is a value representing the upper limit of the warning state determined based on the safety and stability margin analysis of the strong power network; When the global warning state vector reaches the preset control execution threshold, a preset collaborative control strategy is executed, and the collaborative control strategy is at least one of the following: Predictive trend reconstruction; Active damping injection; Protection setting value online adjustment.

6. A method for intelligently processing faults in a real-time monitoring system of a strong electric power system based on FPGA, applied to the intelligent processing system for real-time monitoring faults of a strong electric power system based on FPGA as claimed in any one of claims 1 to 5, characterized in that: The following steps are involved: Monitor the power system in real time and receive the monitored voltage or current signal, and then convert it into a time domain pulse sequence that represents the dynamic changes of the signal; Processing the time domain pulse sequence in real time to identify a preset fault precursor pattern and generating a local warning state vector accordingly; Receive a local warning state vector generated by the hardware pulse neural network module, and combine it with the local warning state vector received from at least one other node to generate a global warning state vector through a consensus protocol; Receiving the global warning state vector, and dynamically adjusting internal parameters of the hardware pulse neural network module according to the global warning state vector, thereby adjusting the response characteristics of the hardware pulse neural network module to the corresponding time domain pulse sequence; When the global warning state vector reaches a preset control execution threshold, a preset collaborative control strategy is executed to intelligently handle potential faults.

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