Total variation analog-to-digital conversion device for electroencephalogram acquisition

Abstract

The invention provides a total variation analog-to-digital conversion device for electroencephalogram acquisition. Firstly, a total variation operator is adopted to calculate a second-order increment code, so that the electroencephalogram signal sparsity can be more effectively utilized, and the electroencephalogram signal compression ratio is remarkably improved; and secondly, a fixed double-buffer module is designed, so that a second-order increment coding value can be generated in a simple and efficient manner. And finally, a serialized bit stream generator is designed, the second-order incremental data acquired by a plurality of parallel channels can be subjected to serialized packaging, the expandability is very high, the method can be suitable for multi-channel acquisition, and the method can be reliably connected with a subsequent synchronous clock wireless transmission system. The overhead and delay of synchronous-asynchronous interface coordination are avoided, and the signal acquisition efficiency is further improved.

Description

Technical Field

[0001] The present invention belongs to the field of brain-computer interfaces, and in particular relates to a total variation analog-to-digital conversion device for electroencephalogram acquisition. Background Art

[0002] Brain-Computer Interface (BCI), as a cutting-edge technology connecting the brain with external electronic devices, is leading a revolution in the fields of neurotherapy, neuroscience research, and human-computer interaction. By real-time monitoring and analyzing brain activities, BCI can offer hope for severely disabled patients (such as those with paralysis, locked-in syndrome, etc.) to regain some functions. With the help of BCI technology, patients can control external devices through their thoughts, thus improving their quality of life. In addition, BCI also plays an important role in neuroscience research. It not only helps researchers deeply explore the neural dynamics of the brain but also promotes the understanding of nervous system diseases and the development of treatment methods. The wide application of BCI has promoted innovations in many aspects from basic neuroscience to clinical treatment.

[0003] Among various sensing technologies of BCI, Electroencephalogram (EEG) has become the most commonly used signal acquisition method due to its advantages of non-invasiveness, convenience, high temporal and spatial resolution, etc. EEG can reflect the electrical activities of cortical neuron populations in real time and is widely used in clinical and research fields. However, with the continuous increase in the number of EEG channels, the acquisition and transmission of EEG signals are facing unprecedented challenges. For each additional acquisition channel, the amount of data to be transmitted increases sharply, thus posing higher requirements for the system's transmission bandwidth, energy consumption, processing capacity, etc.

[0004] Modern BCI systems generally adopt wireless data transmission methods to ensure the free movement of users without affecting their daily lives. However, with the sharp increase in data volume, the bandwidth of wireless transmission has become a bottleneck. How to reduce the amount of transmitted data while ensuring data integrity has become the key to solving this problem. Traditional EEG acquisition systems usually adopt an architecture combining an analog front-end sensor (including a pre-amplification stage) and a Nyquist analog-to-digital converter (ADC), converting analog signals into digital signals before subsequent processing and analysis. However, such traditional architectures have serious energy efficiency problems, especially in scenarios where BCI needs to be used for a long time and transmit data frequently, and energy efficiency is particularly important.

[0005] With the limitations of wireless data transmission and battery capacity, the traditional Nyquist ADC architecture has not been effectively optimized in terms of energy consumption, resulting in high power consumption and transmission latency. Due to the traditional analog-to-digital conversion method being based on the Nyquist sampling theorem, its sampling rate must be high enough to accurately capture the frequency information of electroencephalogram (EEG) signals. Since the spectrum of EEG signals is relatively limited, especially the relatively weak high-frequency part, the traditional Nyquist sampling method often generates a large amount of redundant data, which not only increases the transmission burden but also wastes a large amount of power resources. Furthermore, the sparse characteristics of EEG signals are not fully utilized.

[0006] EEG signals have significant sparsity in temporal variation, that is, the signal changes little most of the time and only has large fluctuations at a few moments. To address this redundancy problem, researchers have proposed the design of analog-to-digital converters based on signal increment coding (such as Delta-ADC), attempting to reduce the data transmission burden through compressive sampling and improve the energy efficiency of the system. Delta-ADC can effectively avoid unnecessary data acquisition during the signal silent period by only sampling the increment information when the input signal crosses a preset threshold, thus saving energy while still being able to efficiently recover the signal.

[0007] However, although Delta-ADC can significantly improve the acquisition efficiency in theory, the existing implementations still face several key problems. First, the increment coding method adopted by Delta-ADC is not always superior to the traditional Nyquist sampling-based analog-to-digital converter. In some application scenarios, especially when the signal changes frequently or complexly, the performance of Delta-ADC may be inferior to that of the traditional successive approximation analog-to-digital converter. In addition, the existing Delta-ADCs generally use first-order difference calculation to generate first-order increment coding. However, the first-order increment coding does not fully utilize the sparsity of EEG signals, resulting in limited compression effect and insufficient improvement in acquisition efficiency. Finally, most of the existing Delta-ADC systems adopt asynchronous sampling mode, while wireless brain-computer interface systems usually adopt synchronous digital processing methods. This leads to a large overhead and latency in the coordination between system interfaces, further affecting the overall performance and energy efficiency.

[0008] Therefore, to meet the requirements of modern brain-computer interfaces for efficient acquisition, low-power consumption transmission, and high-quality signal recovery, it is crucial to design a new type of analog-to-digital conversion device that can effectively compress EEG signals, improve the acquisition efficiency, and adapt to the requirements of wireless transmission. This design not only needs to fully explore the sparse characteristics of EEG signals but also consider the power consumption, sampling efficiency of the system, and compatibility with subsequent processing modules. Summary of the Invention

[0009] To overcome the problem of low efficiency in electroencephalogram (EEG) signal acquisition in the prior art, the present invention provides a total variation analog-to-digital converter (TV-ADC) for EEG acquisition, which comprehensively improves the signal acquisition efficiency while maintaining the simplicity of the circuit topology. First, a total variation operator is designed to calculate the second-order delta encoding, which can make more effective use of the sparsity of EEG signals compared with the existing first-order delta encoding, significantly improving the compression ratio of EEG signals. Second, a fixed dual-buffer module is designed to avoid the circuit complexity caused by the need for mutual switching in the existing dual-buffer module, and can generate the second-order delta encoding values in a simple and efficient manner. Finally, a serialized bitstream generator is designed to serialize and package the second-order delta data collected from multiple parallel channels. It not only has high scalability and can be applied to multi-channel acquisition, but also can be reliably docked with the subsequent synchronous clock wireless transmission system, avoiding the overhead and delay of synchronous-asynchronous interface coordination, and further improving the signal acquisition efficiency.

[0010] The total variation analog-to-digital converter for EEG acquisition involved in the present invention is composed of a multiplexer, a fixed dual-buffer module, a DAC controller, a DAC, a comparator, an increment counter, and a serialized bitstream generator. Among them, the multiplexer is controlled by the global clock CLK of the TV-ADC ADC to switch the acquisition channel in each clock cycle and stabilize the current EEG acquisition signal to support multi-channel parallel acquisition.

[0011] Furthermore, the fixed dual-buffer module is controlled by the global clock CLK of the TV-ADC ADC to store and output the previous acquisition value of each channel to support the calculation of the second-order delta encoding, while avoiding the complexity of the traditional dual-buffer structure.

[0012] Even further, the DAC controller is used to read the previous acquisition value of the fixed dual-buffer module and generate a DAC control code in combination with the output of the increment counter.

[0013] Even further, the DAC reads the DAC control code output by the DAC controller, converts it into an EEG signal to be compared, and after multiple comparisons, stores the final DAC output as the current acquisition value of the current channel in the fixed dual-buffer module.

[0014] Even further, the comparator is used to compare the EEG signal to be acquired output by the multiplexer and the EEG signal to be compared output by the DAC, and inputs the comparison result into the increment counter for increment counting.

[0015] Furthermore, the increment counter is controlled by the global clock CLK of the TV-ADC. In each clock cycle, the output result of the comparator is read in, the second-order increment of the currently acquired electroencephalogram (EEG) signal and the previous acquisition value is calculated, and the increment is transmitted to the DAC controller and the serialized bitstream generator. ADC Furthermore, the serialized bitstream generator is controlled by the global clock CLK of the TV-ADC. In each clock cycle, the signal increment output by the increment counter is stored and converted into a bitstream, data compression is achieved, and serialization and packaging are performed to ensure the synchronization of data transmission, generating the final bitstream output by the TV-ADC.

[0016] The present invention uses the total variation operator to calculate the second-order increment coding. Compared with the existing first-order increment coding, it can make more effective use of the sparsity of the EEG signal and significantly improve the compression ratio of the EEG signal. Secondly, a fixed dual-buffer module is adopted, which avoids the circuit complexity caused by the need for mutual switching in the existing dual-buffer module and can generate the second-order increment coding value in a simple and efficient manner. Finally, a serialized bitstream generator is designed, which can serialize and package the second-order increment data collected by multiple parallel channels. It not only has high scalability and can be applied to multi-channel acquisition, but also can be reliably docked with the subsequent synchronous clock wireless transmission system, avoiding the overhead and delay of synchronous-asynchronous interface coordination and further improving the signal acquisition efficiency. ADC

[0017] BRIEF DESCRIPTION OF THE DRAWINGS

[0018] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following will briefly introduce the drawings required for use in the embodiments or the description of the prior art. Obviously, the following-described drawings are only some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on these drawings.

[0019] Figure 1

[0020] Figure 2

[0021] Figure 3

[0022] Figure 4

[0023] Figure 5

[0024] Figure 6

[0023] Figure 5

[0024] Figure 6 Figure 6Schematic diagram of the working principle of the incremental counter;

[0025] Figure 7 Example timing diagram of the incremental counter;

[0026] Figure 8 Schematic diagram of the working principle of the serialization bit stream generator;

[0027] Figure 9 Data results collected by two ADCs;

[0028] Figure 10 Results of normalizing the data collected by two ADCs;

[0029] Figure 11 Results of converting the data collected by two ADCs into a bit stream;

[0030] Figure 12 To count the number of 0s and 1s in the bit stream and the total number of binary values. Detailed implementation

[0031] In the following description, for the purpose of illustration rather than limitation, specific details such as specific system structures and technologies are presented to thoroughly understand the embodiments of the present invention. However, those skilled in the art should clearly understand that the present invention can also be implemented in other embodiments without these specific details. In other cases, detailed descriptions of well-known systems, devices, circuits, and methods are omitted to avoid unnecessary details from interfering with the description of the present invention.

[0032] For an N-point electroencephalogram time series signal X = [x1, x2, …, x N T , its total variation increment and total variation operator are defined as:

[0033]

[0034] where D = [d1, d2, …, d N T is the total variation increment, is the total variation operator. For each data acquisition point x t , its total variation increment is d t = x t - (2x t-1 - x t-2 ). It can be seen that when calculating the total variation increment of the current data acquisition point, the values of the previous two data acquisition points need to be obtained. Therefore, the total variation increment is a second-order increment, and the total variation operator is a second-order difference operator.

[0035] ​​To achieve second-order incremental acquisition, the present invention proposes a total variation analog-to-digital conversion device for electroencephalogram acquisition, and the overall architecture is as Figure 1 shown. The device consists of a multiplexer, a fixed dual-buffer module, a DAC controller, a DAC, a comparator, an incremental counter, and a serialized bitstream generator.

[0036] The multiplexer is controlled by the global clock CLK of the TV-ADC ADC to switch the acquisition channels every clock cycle and stabilize the current acquisition signal after the channel switch, thus supporting multi-channel parallel acquisition. The multiplexer in this circuit adopts a standard time-division multiplexing structure, allowing the signals of L channels to share a physical channel for transmission and occupying this channel sequentially in different CLK ADC cycles to achieve efficient data acquisition.

[0037] In the present invention, the time-division multiplexing structure is implemented through a multiplexer circuit, and the switch position is switched once every clock cycle to select different acquisition channels. After the multiplexer, the signal enters the sample-and-hold circuit, where a switched-capacitor circuit is used to physically hold the signal to ensure the stability of the signal during the acquisition process and guarantee the accuracy and reliability of subsequent acquisitions.

[0038] As Figure 2 shown, the fixed dual-buffer module is controlled by the global clock CLK of the TV-ADC ADC to store and output the previous acquisition value of each channel to support the calculation of second-order incremental coding and avoid the complexity of the traditional dual-buffer structure.

[0039] Specifically, the module contains two first-in-first-out queues (FIFOs) of the same length, and the queue length is related to the number of channels to be acquired. Taking L channels to be acquired as an example, each FIFO needs to store at least L data. To prevent queue overflow, a certain margin must be reserved. Therefore, in the present invention, the length of the FIFO is set to 1.5L. The two FIFOs are arranged side by side, and each FIFO can read data independently. The input of FIFO1 can only obtain data from the output of FIFO2 and cannot receive external input data; the input of FIFO2 can directly receive external input. It can be seen that the fixed dual-buffer module forms a single-input dual-output structure. The design of this structure is intended to cooperate with the subsequent DAC controller to read data in a fixed form, thus avoiding increasing the circuit complexity and power consumption due to frequent switching of the readout port.

[0040] As Figure 3 shown, the DAC controller is used to read the previous acquisition value of the fixed dual-buffer module and generate a DAC control code in combination with the output of the incremental counter.

[0041] Specifically, the global clock CLK ADC Under the control of , TV-ADC will collect data from L channels in sequence, collecting data from one channel in each clock cycle. First, collect the data from the first channel and get the collected value. The DAC controller workflow is as follows:

[0042] Assume that the data stored in the current fixed double buffer module are:

[0043]

[0044] Step 1: Take out the last two acquisition values of the first channel from FIFO1 and FIFO2 in the fixed double buffer module respectively and The former is inverted in the inverting module The latter is input into the doubling module and doubled to obtain Add the two together to get the initial comparison value The inversion module is implemented using an inverter circuit to invert the sign bit of the input data and output it. The doubling module is implemented using a shift register circuit to shift the input data left by 1 bit, thereby achieving a doubling effect.

[0045] Step 2: The incremental counter inputs the incremental value kΔ and adds it to the initial comparison value to obtain the value to be compared. Where Δ is the minimum quantization unit of TV-ADC, and the initial value of the increment is 0Δ.

[0046] Step 3: Set the value to be compared As the DAC control code, it is input into the DAC and converted into the corresponding signal to be compared.

[0047] Step 4: Input the signal to be compared into the comparator and compare it with the signal to be collected. If the signal to be collected is greater than the signal to be compared, the incremental counter increases by 1Δ, and the increment value becomes (k+1)Δ. Otherwise, the incremental counter decreases by 1Δ, and the increment value becomes (k-1)Δ.

[0048] Step 5: Loop through steps 2 to 4 until the difference between the signal to be collected and the signal to be compared is less than 1Δ. Stop the loop at this point and use the DAC output as the collected value.

[0049] Step 6: Input FIFO1, Input FIFO2, the data stored in the fixed double buffer module are:

[0050]

[0051]

[0052] Subsequently, the acquisition of the 2nd to the Lth channels can be continued according to the above process. After the acquisition of the Lth channel is completed, the acquisition of the 1st channel is then resumed.

[0053] As Figure 4 shown, the DAC reads the DAC control code output by the DAC controller, converts it into a signal to be compared. After multiple comparisons, the final DAC output is stored as the acquisition value of the current channel for this time in the fixed dual-buffer module.

[0054] Specifically, the DAC adopts an 8-bit capacitive voltage division structure, consisting of an array of 8 weighted capacitors. The sizes of the 8 capacitors are C, 2C, 4C, 8C, C, 2C, 4C, and 8C respectively. Before the start of the conversion, the Reset switch is closed, and the upper plates of all capacitors are grounded to discharge the capacitor array. During the conversion stage, the Reset switch is opened, and the lower plates of the 8 binary weighted capacitors are connected to V ref or ground according to the control code. In addition, a 1.067C attenuation capacitor is connected to divide the capacitor array into two parts, thereby reducing the types of capacitors. The rightmost side of the DAC forms a voltage follower structure through an operational amplifier with negative feedback to isolate the capacitor array from the DAC output, so as to reduce the output impedance and enhance the load-carrying capacity.

[0055] As Figure 5 shown, the comparator is used to compare the signal to be acquired output by the multiplexer with the signal to be compared output by the DAC, and the comparison result is input into the delta counter for increment counting. To reduce power consumption, a dynamic comparator is adopted in the TV-ADC. The signal to be acquired is input from the V inp terminal, the signal to be compared is input from the V inn terminal, and the comparison result is output from the V out terminal.

[0056] As Figure 6 shown, the delta counter is controlled by the global clock CLK ADC of the TV-ADC. In each clock cycle, it reads the output result of the comparator, calculates the second-order increment of the currently acquired electroencephalogram signal and the previous acquisition value, and transmits the increment to the DAC controller and the serialized bitstream generator.

[0057] Specifically, the delta counter contains two modules. Among them, the sign register is composed of a 1-bit register circuit and is used to store the sign of the increment value. The 8-bit binary counter is composed of 8 D flip-flops and is used to store the magnitude of the increment value.

[0058] The increment counter works as follows: The initial value of the increment is 0Δ. When the output of the comparator is positive, it is determined that the EEG signal to be collected is greater than the EEG signal to be compared, then the increment counter is incremented by 1Δ, the sign register is a positive sign, and the increment value becomes (0 + 1)Δ. When the output of the comparator is negative, it is determined that the EEG signal to be collected is less than the EEG signal to be compared, then the increment counter is decremented by 1Δ, the sign register is a negative sign, and the increment value becomes (0 - 1)Δ. After each judgment, the increment value is output to the DAC controller to generate the DAC control code. The above judgment steps are looped until the difference between the EEG signal to be collected and the EEG signal to be compared is less than 1Δ. At this time, the loop stops, and the sign in the sign register and the value in the 8-bit binary counter are concatenated to obtain the final second-order increment value.

[0059] As Figure 7 shown, it is an example timing diagram of the increment counter. In each period of the global clock CLK ADC , one channel is collected respectively. In each clock period, the output of the multiplexer remains stable for the increment counter to perform analog-to-digital conversion.

[0060] In the first period, the increment counter performs analog-to-digital conversion on the CH1 channel. During the low level of CLK ADC , both the EEG signal to be collected and the DAC output signal remain stable. At this time, the DAC output signal is the EEG signal to be compared of the CH1 channel. During the high level of CLK ADC , the increment counter starts to perform analog-to-digital conversion. The first comparison finds that the EEG signal to be compared is less than the EEG signal to be collected. Therefore, after incrementing by 1Δ, the comparison continues. After incrementing by 1Δ six times, the difference between the EEG signal to be compared and the EEG signal to be collected is less than 1Δ, and the conversion is completed at this time. At the beginning of the next CLK ADC period, the increment counter outputs the increment value of the CH1 channel, which is +6Δ.

[0061] In the second period, the increment counter performs analog-to-digital conversion on the CH2 channel. During the low level of CLK ADC , both the EEG signal to be collected and the DAC output signal remain stable. At this time, the DAC output signal is the EEG signal to be compared of the CH2 channel. During the high level of CLK ADC , the increment counter starts to perform analog-to-digital conversion. The first comparison finds that the difference between the EEG signal to be compared and the EEG signal to be collected is less than 1Δ, and the conversion is completed at this time. At the beginning of the next CLK ADC period, the increment counter outputs the increment value of the CH2 channel, which is 0Δ. At this time, it is considered that there is no increment between this acquisition and the previous acquisition of the CH2 channel.

[0062] During the 3rd period, the increment counter performs analog-to-digital conversion on the CH3 channel. During the low level of CLK ADC , both the electroencephalogram (EEG) signal to be acquired and the DAC output signal remain stable. At this time, the DAC output signal is the EEG signal to be compared for the CH3 channel. During the high level of CLK ADC , the increment counter starts the analog-to-digital conversion. The first comparison reveals that the EEG signal to be compared is greater than the EEG signal to be acquired. Therefore, after decrementing by 1Δ, the comparison continues. After 4 decrements of 1Δ, the difference between the EEG signal to be compared and the EEG signal to be acquired is less than 1Δ, and at this point, the conversion is complete. At the start of the next CLK ADC period, the increment counter outputs the increment value for the CH3 channel, which is -4Δ.

[0063] For other channels, the analog-to-digital conversion is performed cycle by cycle according to the above conversion rules.

[0064] As Figure 8 shown, the serialized bitstream generator is controlled by the global clock CLK ADC of the TV-ADC. It stores and converts the signal increments output by the increment counter into a bitstream within each clock cycle, achieving data compression, and performs serialization and packaging to ensure the synchronization of data transmission, generating the final bitstream output by the TV-ADC.

[0065] Specifically, at the rising edge of each global clock CLK ADC , the event discriminator reads the increment value from the increment counter and determines whether this increment value forms a second-order increment event. When the increment value is not 0Δ, it indicates that the currently acquired EEG signal is different from the EEG signal to be compared, and thus it can be determined as a second-order increment event. At this time, the increment value is stored in the event register.

[0066] Each second-order increment event requires 9 + log2L bits of storage space, where log2L bits are used for the numbers of L channels, 1 bit is used for the sign of the increment value, and 8 bits are used for storing the magnitude of the increment value. In addition, the system is also equipped with a 9 + log2L-bit copy memory for parallel data caching and processing to improve data throughput efficiency.

[0067] After all L channels complete one acquisition, a complete data acquisition frame is formed. For each completed acquisition frame, the finite state machine generates an enable signal ENA and inputs it to the bitstream clock generator. This clock generator has a built-in ring oscillator, which is specifically used to provide the clock CLK BIT for bitstream packaging.

[0068] Subsequently, the finite state machine scans the data in the event register and performs bitstream packaging based on the CLK BIT clock, finally generating the TV-ADC data bitstream.

[0069] The TV-ADC proposed by the present invention is compared with the current state-of-the-art Nyquist ADC. The experimental setup is as follows: The subject wears an EEG cap and sits quietly in front of a computer. Two electrode channels are led out from the EEG cap. Among them, the 1st channel is collected using a Nyquist ADC, and the 2nd channel is collected using a TV-ADC. The collected data is transmitted to the computer by wire for analysis.

[0070] The data collected by the two ADCs is as Figure 9 shown. It can be seen that the data collected by the Nyquist ADC has greater fluctuations and larger amplitudes, while the data collected by the TV-ADC has smaller fluctuations, and the vast majority of the collected values are very close to 0, and only a few collected values are relatively large, showing a high sparsity.

[0071] After arranging the data collected by the two ADCs in descending order and normalizing it, the data is as Figure 10 shown. It can be seen that the sparsity of the data collected by the TV-ADC is significantly higher than that of the data collected by the Nyquist ADC.

[0072] The data collected by the two ADCs is converted into bitstreams, as Figure 11 shown. It can be seen that the bitstream of the TV-ADC is sparser than that of the Nyquist ADC.

[0073] The data collected by the two ADCs is converted into bitstreams, and the number of 0s and 1s and the total number of binary values in the bitstreams are counted, as Figure 12 shown. It can be concluded that the data volume of the TV-ADC bitstream is 39.7% of the data volume of the Nyquist ADC bitstream.

[0074] The above shows that the amount of data required to be transmitted by the TV-ADC is significantly lower than that required to be transmitted by the Nyquist ADC, thus having higher energy efficiency.

[0075] It should be understood that the magnitudes of the sequence numbers of the steps in the above embodiments do not mean the order of execution. The order of execution of each process should be determined by its function and internal logic, and should not constitute any limitation to the implementation process of the embodiments of the present invention.

[0076] Those skilled in the art can clearly understand that, for the convenience and conciseness of description, only the above division of each functional unit and module is used as an example. In practical applications, the above functions can be allocated to different functional units and modules according to needs, that is, the internal structure of the device can be divided into different functional units or modules to complete all or part of the functions described above. Each functional unit and module in the embodiments can be integrated into a processing unit, or each unit can exist physically alone, or two or more units can be integrated into one unit. The above integrated unit can be implemented in the form of hardware or in the form of a software functional unit. In addition, the specific names of each functional unit and module are only for the convenience of mutual distinction and do not limit the protection scope of this application. The specific working processes of the units and modules in the above system can refer to the corresponding processes in the foregoing method embodiments and will not be repeated here.

[0077] In the above embodiments, the descriptions of the respective embodiments have their own emphases. For parts not detailed or recorded in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0078] Those of ordinary skill in the art can realize that the units and algorithm steps of each example described in combination with the embodiments disclosed herein can be implemented by electronic hardware, or by a combination of computer software and electronic hardware. Whether these functions are executed in the form of hardware or software depends on the specific application and design constraints of the technical solution. A professional technician can use different methods to implement the described functions for each specific application, but such implementation should not be considered to exceed the scope of the present invention.

[0079] In the embodiments provided by the present invention, it should be understood that the disclosed device / terminal device and method can be implemented in other ways. For example, the device / terminal device embodiments described above are only illustrative. For example, the division of the module or unit is only a logical function division. In actual implementation, there may be other division methods. For example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the displayed or discussed coupling or direct coupling or communication connection to each other can be through some interfaces. The indirect coupling or communication connection of the device or unit can be in an electrical, mechanical or other form.

[0080] The unit described as a separate component may or may not be physically separated. The component displayed as a unit may or may not be a physical unit, that is, it can be located in one place or distributed to multiple network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0081] In addition, in each embodiment of the present invention, each functional unit can be integrated into one processing unit, or each unit can exist physically alone, or two or more units can be integrated into one unit. The above integrated unit can be implemented in the form of hardware or in the form of a software functional unit.

[0082] If the integrated module / unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on such an understanding, to implement all or part of the processes in the above-described embodiment methods of the present invention, it can also be completed by a computer program instructing relevant hardware. The computer program can be stored in a computer-readable storage medium. When the computer program is executed by a processor, the steps of the above-described various method embodiments can be implemented. Among them, the computer program includes computer program code, and the computer program code can be in the form of source code, object code, executable file, or some intermediate form, etc. The computer-readable medium can include: any entity or device capable of carrying the computer program code, recording medium, USB flash drive, mobile hard disk, magnetic disk, optical disc, computer memory, read-only memory (ROM), random access memory (RAM), electrical carrier signal, telecommunication signal, and software distribution medium, etc. It should be noted that the content included in the computer-readable medium can be appropriately increased or decreased according to the requirements of legislation and patent practice in the jurisdiction. For example, in some jurisdictions, according to legislation and patent practice, the computer-readable medium does not include electrical carrier signals and telecommunication signals.

[0083] The above-described embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that: they can still modify the technical solutions recorded in the foregoing embodiments, or perform equivalent replacements on some of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the various embodiments of the present invention, and should all be included in the protection scope of the present invention.

Claims

1. A Total Variation Analog-to-Digital Converter (TV-ADC) for electroencephalogram acquisition, characterized in that: The full variational analog-to-digital conversion device consists of a multiplexer, a fixed dual-buffer module, a DAC controller, a DAC, a comparator, an increment counter, and a serialized bitstream generator, and is used to collect electroencephalogram signals; The multiplexer, the fixed dual-buffer module, the increment counter, and the serialized bitstream generator are all controlled by the global clock CLK of the TV-ADC ADC Control; The multiplexer switches the acquisition channels in each clock cycle and stabilizes the current electroencephalogram acquisition signal to support multi-channel parallel acquisition; The fixed dual-buffer module is responsible for storing and outputting the previous acquisition value of each channel to support the calculation of second-order delta encoding; The DAC controller is used to read the previous acquisition value of the fixed dual-buffer module and generate a DAC control code in combination with the output of the increment counter; The DAC reads the DAC control code output by the DAC controller, converts it into an electroencephalogram signal to be compared. After multiple comparisons, the final DAC output is stored as the current acquisition value of the current channel in the fixed dual-buffer module; The comparator is used to compare the electroencephalogram signal to be acquired output by the multiplexer with the electroencephalogram signal to be compared output by the DAC, and inputs the comparison result into the increment counter for increment counting; In each clock cycle, the increment counter reads the output result of the comparator, calculates the second-order increment of the current electroencephalogram acquisition signal and the previous acquisition value, and transmits the increment to the DAC controller and the serialized bitstream generator; The serialized bitstream generator stores and converts the signal increment output by the increment counter into a bitstream in each clock cycle, generating the final bitstream output by the TV-ADC.

2. A full variational analog-to-digital conversion device according to claim 1, wherein the multiplexer adopts a standard time-division multiplexing structure, and the time-division multiplexing structure is implemented by a multiplexer circuit, and the switch position is switched once in each clock cycle to select different acquisition channels.

3. A full variational analog-to-digital conversion device according to claim 1, wherein the DAC controller consists of an inversion module and a doubling module; the inversion module is implemented by an inverter circuit, which inverts the sign bit of the input data and outputs it; the doubling module is implemented by a shift register circuit, which shifts the input data left by 1 bit to achieve the doubling effect.

4. A full variational analog-to-digital conversion device according to claim 3, wherein the working process of the DAC controller is as follows: Assume that the data stored in the current fixed dual-buffer module are respectively: Step 1: Take out the previous two acquisition values of the first channel from FIFO1 and FIFO2 in the fixed double-buffer module respectively and The former is input into the inversion module to obtain an inverted value The latter is input into the doubling module to be doubled Add the two to obtain the initial comparison value Step 2: The increment counter inputs the increment value kΔ, adds it to the initial comparison value, and obtains the value to be compared where Δ is the minimum quantization unit of the TV-ADC; where the initial value of the increment value is 0Δ; Step 3: Use the value to be compared as the DAC control code and input it into the DAC to convert it into the corresponding signal to be compared; Step 4: Input the signal to be compared into the comparator and compare it with the signal to be acquired; if the signal to be acquired is greater than the signal to be compared, the increment counter is incremented by 1Δ, and the increment value becomes (k + 1)Δ, otherwise it is decremented by 1Δ, and the increment value becomes (k - 1)Δ; Step 5: Loop through Steps 2 to 4 until the difference between the signal to be acquired and the signal to be compared is less than 1Δ. At this point, stop the loop and use the output of the DAC at this time as the acquired value Step 6: Input into FIFO1, and input into FIFO2. At this time, the data stored in the fixed double-buffer module are respectively:

5. A full variational analog-to-digital conversion device according to claim 1, wherein the DAC is implemented by an 8-bit capacitive voltage division structure; the comparator adopts a dynamic comparator.

6. A full variational analog-to-digital conversion device according to claim 1, wherein the increment counter includes two modules: a sign register and an 8-bit binary counter; the sign register is composed of a 1-bit register circuit and is used to store the sign of the increment value, and the 8-bit binary counter is composed of 8 D flip-flops and is used to store the magnitude of the increment value.

7. A total variation analog-to-digital conversion device according to claim 6, wherein the operation of the increment counter is as follows: the initial value of the increment value is 0Δ; when the output of the comparator is positive, it is determined that the electroencephalogram signal to be collected is greater than the electroencephalogram signal to be compared, then the increment counter is incremented by 1Δ, the sign register is a positive sign, and the increment value becomes (0 + 1)Δ; when the output of the comparator is negative, it is determined that the electroencephalogram signal to be collected is less than the electroencephalogram signal to be compared, then the increment counter is decremented by 1Δ, the sign register is a negative sign, and the increment value becomes (0 - 1)Δ; after each judgment, the increment value is output to the DAC controller to generate a DAC control code; the above judgment steps are cycled until the difference between the electroencephalogram signal to be collected and the electroencephalogram signal to be compared is less than 1Δ, at which point the loop is stopped, and the sign in the sign register and the value in the 8-bit binary counter are concatenated to obtain the final second-order increment value.

8. A total variation analog-to-digital conversion device according to claim 1, wherein the serialized bitstream generator consists of an event judge, an event register, a finite state machine, a bitstream clock generator, and a bitstream packager.

9. An all-variation analog-to-digital conversion device according to claim 8, wherein the serialization bitstream generator reads the increment value from the increment counter at the rising edge of each global clock CLK ADC and the event discriminator determines whether the increment value forms a second-order increment event; When the increment value is not 0Δ, it is determined as a second-order increment event, and the increment value is stored in the event register; After all L channels have completed one acquisition, a complete data acquisition frame is formed; Upon completion of each acquisition frame, the finite state machine generates an enable signal ENA and inputs it to the bitstream clock generator; the clock generator incorporates a ring oscillator dedicated to providing the clock CLK for bitstream packaging BIT ; The finite state machine scans the data in the event register and performs bitstream packing based on the CLK BIT clock to finally generate the TV-ADC data bitstream.

10. A total variation analog-to-digital conversion device according to claim 9, in the serialized bitstream generator, each second-order increment event requires 9 + log2L bits of storage space, where log2L bits are used for the numbers of L channels, 1 bit is used for the sign of the increment value, and 8 bits are used for storing the amplitude of the increment value.

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