Transmitting circuit and transmitter

Abstract

The invention provides a transmitting circuit and a transmitter, and relates to the technical field of communication, and the transmitting circuit comprises N first switches, N QPSK modulation branches and a first synthesizer. The QPSK modulation branches are in one-to-one correspondence with the first switches, and the input ends of the QPSK modulation branches are connected with the corresponding first switches; the QPSK modulation branch is used for generating a QPSK signal; the amplitudes of the QPSK signals correspondingly generated by the QPSK modulation branches are different from one another; the first synthesizer is connected with the output ends of the QPSK modulation branches and used for combining the QPSK signals output by the QPSK modulation branches into first radio frequency (RF) signals. According to the technical scheme, the system power consumption can be reduced.

Description

Technical Field

[0001] This application relates to the field of communication technologies, and in particular, to a transmitting circuit and a transmitter. Background Art

[0002] With the rapid development of communication technologies, the demand for wireless communication transmission speed in terminal applications is increasing day by day. To achieve high-speed transmission, current transmitters are facing some problems that need to be solved urgently in modulation technologies.

[0003] Traditional low-order modulation schemes, such as binary phase shift keying (BPSK) modulation and on-off keying (OOK) modulation, etc., since the amount of information carried by each symbol is limited, in order to achieve high-speed transmission, a higher symbol rate must be adopted, which means that a larger bandwidth needs to be occupied, and the current available spectrum resources are difficult to meet the large bandwidth requirements.

[0004] To solve the bandwidth problem brought by low-order modulation, adopting high-order modulation technologies becomes a possible solution. For example, high-order modulation technologies such as 64-quadrature amplitude modulation (QAM) and 256QAM can transmit more information within the same bandwidth, greatly improving the spectral efficiency. However, current high-order modulation technologies usually implement high-order modulation in the digital domain, thus requiring high-speed data converters, resulting in a relatively high overall power consumption of the system. Summary of the Invention

[0005] This application provides a transmitting circuit and a transmitter for reducing the power consumption of the system.

[0006] In a first aspect, a transmitting circuit is provided, including: N first switches, N quadrature phase shift keying (QPSK) modulation branches, and a first synthesizer. The QPSK modulation branches correspond to the first switches one by one, and the input end of each QPSK modulation branch is connected to the corresponding first switch; the QPSK modulation branches are used to generate QPSK signals; the amplitudes of the QPSK signals generated by each QPSK modulation branch are different from each other; the first synthesizer is connected to the output ends of each QPSK modulation branch and is used to combine the QPSK signals output by each QPSK modulation branch into a first radio frequency (RF) signal. Wherein, N is a positive integer greater than 1.

[0007] In this solution, multiple QPSK branches can generate multiple QPSK signals with different amplitudes. By superimposing the multiple QPSK signals through the first synthesizer, a high-order modulation signal can be generated, realizing high-order modulation in the analog domain without a high-speed data converter. Therefore, this solution can reduce the system power consumption. Moreover, in this solution, the QPSK modulation branch to be turned on can be controlled by the first switch, so that the modulation order can be flexibly adjusted according to the system requirements.

[0008] In a possible implementation manner of the first aspect, the QPSK modulation branch includes a QPSK modulation circuit and a gain amplifier; the QPSK modulation circuit is used to generate a modulation signal; the gain amplifier is connected to the output end of the QPSK modulation circuit and is used to amplify the modulation signal to obtain a QPSK signal; the gains of the gain amplifiers corresponding to the respective QPSK modulation branches are different from each other.

[0009] In the above implementation manner, the amplitude adjustment of each QPSK signal is realized by using a gain amplifier, which can reduce the cost and power consumption.

[0010] In a possible implementation manner of the first aspect, the gains of the gain amplifiers corresponding to the 1st to Nth QPSK modulation branches decrease in sequence, and the gains of the gain amplifiers corresponding to adjacent QPSK modulation branches differ by 6 dB.

[0011] Through the above implementation manner, each path of QPSK signal can obtain a more reasonable amplitude difference. Correspondingly, the constellation points in the constellation diagram can be distributed more evenly and reasonably, which can reduce the requirement for the transmit power, improve the anti-noise performance and spectral efficiency of the system, and also reduce the demodulation complexity.

[0012] In a possible implementation manner of the first aspect, the QPSK modulation circuit includes a symbol mapping module and an IQ modulator connected in series; the symbol mapping module is used to perform symbol mapping on the input bit stream to obtain a baseband signal; the IQ modulator is used to modulate the carrier signal according to the baseband signal to generate a modulation signal.

[0013] In a possible implementation manner of the first aspect, the transmitting circuit further includes a first demultiplexer, a power amplifier, and an antenna; the first demultiplexer is respectively connected to the input ends of the respective first switches; the input end of the power amplifier is connected to the output end of the first synthesizer, and the output end of the power amplifier is connected to the antenna; the carrier signals adopted by the respective QPSK modulation branches are the same.

[0014] In one possible implementation of the first aspect, the transmitting circuit includes M second switches, M modulation units, and a second combiner, where each modulation unit includes N first switches, N QPSK modulation branches, and a first combiner; M is a positive integer greater than 1. The second switches correspond one-to-one to the modulation units and are connected to the N first switches of the corresponding modulation unit via a first demultiplexer. The second combiner is connected to the output of each modulation unit and is configured to combine the first RF signals output by each modulation unit into a target RF signal.

[0015] The above embodiment aggregates the first RF signals generated by multiple modulation units to achieve a target RF signal with a large bandwidth. This solution reduces the bandwidth requirements for each modulation unit, thereby lowering the requirements for RF components and further reducing the difficulty of hardware implementation. Furthermore, the second switch controls the number of modulation units to be turned on, allowing for flexible bandwidth adjustment based on system requirements.

[0016] In a possible implementation of the first aspect, frequencies of carrier signals used by the modulation units are different from each other.

[0017] This implementation has a low structural complexity, can save space and reduce system costs.

[0018] In a possible implementation of the first aspect, each modulation unit is connected to the second synthesizer via a mixer, and the mixer is used to up-convert the first RF signal output by the connected modulation unit and output it to the second synthesizer; the carrier signal used by each modulation unit is the same, and the frequency of the up-converted first RF signal output by each mixer is different.

[0019] The above implementation can reduce the requirements on radio frequency devices and improve system stability.

[0020] In a possible implementation of the first aspect, the transmitting circuit further includes a second demultiplexer, a power amplifier, and an antenna; the second demultiplexer is respectively connected to the input end of each second switch; the input end of the power amplifier is connected to the output end of the second synthesizer, and the output end of the power amplifier is connected to the antenna.

[0021] In a second aspect, a transmitter is provided, comprising the transmitting circuit described in the first aspect or any embodiment of the first aspect.

[0022] It can be understood that the beneficial effects of the second aspect can be found in the relevant description of the first aspect above, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 A schematic diagram of the structure of the transmitting circuit provided in an embodiment of the present application;

[0024] Figure 2 Schematic diagram of a transmission circuit architecture provided by an embodiment of the present application;

[0025] Figure 3 Schematic diagram of a zero-IF architecture provided by an embodiment of the present application;

[0026] Figure 4 Schematic diagram of a second up-conversion architecture provided by an embodiment of the present application. Specific implementation manners

[0027] The embodiments of the present application will be described below in conjunction with the accompanying drawings in the embodiments of the present application. The terms used in the implementation manner part of the embodiments of the present application are only used to explain the specific embodiments of the present application, and are not intended to limit the present application. These several specific embodiments can be combined with each other, and the same or similar concepts or processes may not be repeated in some embodiments.

[0028] To facilitate the understanding of the technical solutions in the embodiments of the present application, some terms involved in this solution will be briefly introduced below:

[0029] QPSK (quadrature phase shift keying): Quadrature Phase Shift Keying, a phase modulation method that uses four different phases of a carrier signal to represent binary data. Among them, each phase represents two bits of binary data, that is, each symbol can transmit two bits of data, and the corresponding modulation order is 2.

[0030] 16QAM: 16-QAM (16-Quadrature Amplitude Modulation), a combined amplitude and phase modulation method that uses 16 different amplitude and phase combinations of a carrier signal to represent binary data. Among them, each symbol can transmit 4 bits of data, and the corresponding modulation order is 4.

[0031] 64QAM: 64-QAM (64-Quadrature Amplitude Modulation), also a combined amplitude and phase modulation method that uses 64 different amplitude and phase combinations of a carrier signal to represent binary data. Among them, each symbol can transmit 6 bits of data, and the corresponding modulation order is 6.

[0032] 256QAM: 256-QAM (256-Quadrature Amplitude Modulation), which further increases the number of amplitude and phase changes and uses 256 different amplitude and phase combinations of a carrier signal to represent binary data. Among them, each symbol can transmit 8 bits of data, and the corresponding modulation order is 8.

[0033] High-order digital domain modulation techniques (such as 64QAM and 256QAM) can transmit more data within a limited spectral bandwidth by carrying more bits in each symbol. In high-order digital domain modulation techniques, the transmitter needs a digital-to-analog converter (DAC) to complete the conversion from digital signals to analog signals. High-order modulation requires a higher symbol rate and a more complex signal waveform, which means that the DAC needs a relatively high conversion rate and resolution. That is, high-order digital domain modulation requires a high-speed DAC to implement. The DAC is one of the main sources of power consumption in the system. The higher its conversion rate and resolution, the greater the power consumption. Therefore, the overall power consumption of the high-order digital domain modulation system is relatively high.

[0034] Based on this, an embodiment of the present application provides a transmitting circuit, which can reduce the system power consumption by implementing high-order modulation in the analog domain.

[0035] The transmitting circuit provided by the embodiment of the present application can be applied to devices such as mobile phones, tablets, and laptop computers.

[0036] Figure 1 is a schematic structural diagram of the transmitting circuit provided by the embodiment of the present application. As Figure 1 shown, the transmitting circuit provided by the embodiment of the present application may include: N first switches 11, N QPSK modulation branches 12, and a first synthesizer 13, where N is a positive integer greater than 1. The QPSK modulation branches 12 correspond to the first switches 11 one by one. The input end of the QPSK modulation branch 12 is connected to the corresponding first switch 11. The QPSK modulation branch 12 is used to generate QPSK signals, and the amplitudes of the QPSK signals generated by each QPSK modulation branch 12 are different from each other; the first synthesizer 13 is connected to the output ends of each QPSK modulation branch 12 and is used to combine the QPSK signals output by each QPSK modulation branch 12 into a single radio frequency (RF) signal (hereinafter referred to as the first RF signal).

[0037] In this transmitting circuit, each QPSK modulation branch 12 can generate a QPSK signal, and each QPSK signal includes four phases with different amplitudes. By superimposing the QPSK signals of multiple branches through the first synthesizer 13, a high-order QAM modulation signal (i.e., the first RF signal) can be generated, and 2N-order modulation can be implemented in the analog domain. For example, superimposing two QPSK signals can generate a 16QAM modulation signal and achieve 4-order modulation; superimposing three QPSK signals can generate a 64QAM modulation signal and achieve 6-order modulation. This high-order modulation scheme realizes high-order modulation in the RF domain (i.e., the analog domain) without the need for high-speed DAC devices, so the system power consumption can be reduced.

[0038] Among them, the number N of the QPSK modulation branches 12 can be, for example, 4 or 5, etc. The specific size can be set according to actual needs, and this embodiment does not make special limitations on this.

[0039] The first switch 11 can control the corresponding QPSK modulation branch 12 to be turned on or off. That is, when the first switch 11 corresponding to the QPSK modulation branch 12 is turned on, this branch is turned on, and a QPSK signal can be generated; when the first switch 11 corresponding to the QPSK modulation branch 12 is turned off, this branch is turned off, and no QPSK signal is generated. Through the first switch 11, the QPSK modulation branch 12 that needs to be turned on can be controlled, that is, the number of superimposed QPSK signals can be controlled, so that the modulation order can be flexibly adjusted according to system requirements.

[0040] For example, X QPSK modulation branches 12 can be turned on through the first switch 11 to achieve 2X-order modulation, where X ≤ N.

[0041] Among them, each first switch 11 can be an independent device or integrated together.

[0042] The first synthesizer 13 can combine the QPSK signals output by each QPSK modulation branch 12 into one RF signal (i.e., the first RF signal), and it can specifically be a power synthesizer.

[0043] The amplitudes of the QPSK signals corresponding to each QPSK modulation branch 12 are different. In specific implementation, the amplitude adjustment of the QPSK signal can be achieved through a gain amplifier.

[0044] As Figure 2 shown, the QPSK modulation branch 12 can include a QPSK modulation circuit and a gain amplifier. Here, by way of example, the gain amplifier is specifically a variable gain amplifier (VGA). The switch SW1 in the figure represents the first switch 11, and the synthesizer 1 is the first synthesizer 13.

[0045] The QPSK modulation circuit can generate a modulation signal, which can include: a symbol mapping module and an IQ modulator. Among them, the symbol mapping module can perform symbol mapping on the input bit stream to obtain a baseband signal; the IO modulator can modulate the carrier signal according to the baseband signal to generate a modulation signal. The VGA can perform gain on the modulation signal to obtain a gain-modulated signal, that is, a QPSK signal. The gains of each VGA are different from each other, and correspondingly, the amplitudes of each QPSK signal are different from each other.

[0046] The N QPSK signals corresponding to the N QPSK modulation branches 12 can start from the first one and decrease in amplitude. That is, the gains of the VGAs corresponding to the first to the Nth QPSK modulation branches decrease in sequence.

[0047] It can be understood that assuming that N QPSK modulation branches 12 are arranged in the up-down direction in the actual circuit, then the order corresponding to the 1st to the Nth can be the arrangement order from top to bottom or the arrangement order from bottom to top, that is, the 1st QPSK modulation branch 12 can be the QPSK modulation branch 12 at the uppermost position. Correspondingly, the Nth QPSK modulation branch 12 is the QPSK modulation branch 12 at the lowermost position; the 1st QPSK modulation branch 12 can also be the QPSK modulation branch 12 at the lowermost position. Correspondingly, the Nth QPSK modulation branch 12 is the QPSK modulation branch 12 at the uppermost position; or, the order corresponding to the 1st to the Nth can also be other arrangement orders. The embodiments of the present application do not particularly limit the arrangement order of the QPSK modulation branches 12 corresponding to the order of the 1st to the Nth in the actual circuit.

[0048] In some implementation manners, the gains of the VGAs corresponding to adjacent QPSK modulation branches 12 differ by 6 dB. The amplitudes of the modulation signals input to each VGA can be the same, and the gains of adjacent VGAs differ by 6 dB. Correspondingly, the amplitudes of the output signals of the adjacent VGAs differ by approximately twice, that is, among the two paths of QPSK signals output by the adjacent VGAs, the amplitude of one path of QPSK signal is approximately twice that of the other path.

[0049] That is to say, the amplitude of the (n - 1)th path of QPSK signal (i.e., the QPSK signal corresponding to the (n - 1)th QPSK modulation branch 12) is twice the amplitude of the nth path of QPSK signal (i.e., the QPSK signal corresponding to the nth QPSK modulation branch 12), where n ∈ [2, N].

[0050] Based on the above implementation manners, the amplitude differences of each path of QPSK signals can be made more reasonable. Correspondingly, the distribution of constellation points in the constellation diagram can be made more uniform and reasonable, which can reduce the requirement for the transmit power, improve the anti-noise performance and spectral efficiency of the system, and also reduce the demodulation complexity.

[0051] In the above example, the gain amplifier of the QPSK modulation branch 12 is a VGA, which is convenient for adjusting the amplitude of the QPSK signal. In some examples, a fixed gain amplifier can also be used. In other examples, other methods can also be used to implement the amplitude adjustment of the QPSK signal. For example, each IQ modulator can implement the amplitude adjustment of the QPSK signal by using carrier signals with different amplitudes.

[0052] As described above, the QPSK modulation circuit may include a symbol mapping module and an IQ modulator. The symbol mapping module can perform symbol mapping on the input bit stream to obtain a baseband signal.

[0053] In specific implementation, the symbol mapping module may take every two bits as a bit group and map a bit group to a symbol, which is a complex symbol including an in-phase (I) component and a quadrature (Q) component. For example, the bit group "00" can be mapped to the symbol (+1, +1), and the bit group "11" can be mapped to the symbol (-1, -1). Other mapping methods can also be adopted. These symbols corresponding to the bit stream form a baseband signal, and the I component and Q component in the baseband signal can also be referred to as the I signal and Q signal.

[0054] The symbol mapping module can be implemented by devices such as a digital signal processor (DSP) or a field programmable gate array (FPGA). The output I component and Q component can be represented by level signals. For example, a high-level signal represents "+1", and a low-level signal represents "-1".

[0055] The IO modulator can adopt a direct conversion IQ modulator to directly modulate the digital baseband signal onto a carrier signal to generate a modulated signal. Among them, the carrier signal can include an in-phase carrier signal and a quadrature carrier signal. The IO modulator can multiply the I component in the baseband signal by the in-phase carrier signal to obtain an I-channel modulated signal; multiply the Q component by the quadrature carrier signal to obtain a Q-channel modulated signal; and then combine the I-channel modulated signal and the Q-channel modulated signal to form the final modulated signal. The modulated signal can be expressed as:

[0056] s(t) = I(t)·cos(wt) - Q(t)·sin(wt)

[0057] where s(t) represents the modulated signal, I(t) represents the I component, Q(t) represents the Q component, cos(wt) represents the in-phase carrier signal, and -sin(wt) represents the quadrature carrier signal.

[0058] As Figure 2 shown, each IO modulator can input a local oscillator (LO) signal (abbreviation: local oscillator signal), and the LO signal can be cos(wt), which can be used as the in-phase carrier signal. The IQ modulator can phase-shift the LO signal by 90° to obtain the quadrature carrier signal -sin(wt). It can be understood that the LO signal can also be a sine signal, which can be used as the quadrature carrier signal. For the convenience of description, the LO signal is taken as cos(wt) as an example for illustrative description in the embodiments of this application.

[0059] The I and Q components output by the symbol mapping module can be used as control signals to control the IQ modulator to modulate the carrier signal. For example, the values of both the I and Q components can include "+1" and "-1". If the I component received by the IQ modulator is "+1", then cos(wt) can be used as the I-channel modulation signal; if it is "-1", then -cos(wt) can be used as the I-channel modulation signal. Similarly, if the Q component received by the IQ modulator is "+1", then -sin(wt) can be used as the Q-channel modulation signal; if it is "-1", then sin(wt) can be used as the Q-channel modulation signal.

[0060] Among them, the IQ modulator can phase-shift the LO signal by 180° to obtain -cos(wt), and phase-shift the LO signal by -90 degrees to obtain sin(wt).

[0061] It can be understood that the above is only an exemplary description of the QPSK modulation process. In some other examples, other implementation methods can also be adopted, and this embodiment does not make special limitations on this.

[0062] In some embodiments, as Figure 2 shown, the transmitting circuit may include a local oscillator LO for generating the above LO signal.

[0063] In some implementation manners, the output end of the LO can be connected to a power splitter to divide the LO signal output by the LO into N paths and output them to the corresponding IQ modulators respectively. In some implementation manners, the LO can adopt a frequency synthesizer with multiple output ports, and the LO can generate N paths of LO signals and output them to the corresponding IQ modulators respectively. For the convenience of description, subsequent descriptions will be made by taking the LO directly generating N paths of LO signals as an example.

[0064] The above is an exemplary description by taking the IQ modulator obtaining the in-phase carrier signal and the quadrature carrier signal based on the LO signal and phase-shift processing as an example. In some other examples, the process of generating the in-phase carrier signal and the quadrature carrier signal can also be implemented outside the IO modulator, and this embodiment does not make special limitations on this.

[0065] As described above, in the modulation signal generated by the QPSK modulation circuit of each branch, each symbol can carry two bits of data. Correspondingly, for the QPSK signal generated by each QPSK modulation branch 12, each symbol can carry two bits of data. For each additional QPSK signal superimposed, each symbol in the RF signal correspondingly output by the first synthesizer 13 can carry two more bits of data; when N paths of QPSK signals are superimposed, each symbol in the RF signal can correspondingly carry 2N bits of data, realizing 2N-order modulation.

[0066] In some embodiments, as Figure 2As shown, the input end of each switch SW1 (i.e., the first switch 11) can be connected to the first de-multiplexer (DeMux), i.e., DeMux1, which can decompose the input bit stream into multiple sub-bit streams. As Figure 2 shown in it, DeMux1 can adopt a 1:N DeMux, that is, DeMux1 can decompose the input bit stream into N sub-bit streams.

[0067] During specific operation, DeMux1 can decompose the input bit stream into X sub-bit streams according to the conduction number X of the first switch 11, and correspondingly output them to the conducting QPSK modulation branches 12.

[0068] In some embodiments, the transmitting circuit may also include a bit stream generating module (not shown), which is connected to the input end of DeMux1 and is used to convert the signal to be transmitted into a bit stream and then output it to DeMux1.

[0069] In some embodiments, as Figure 2 shown, the output end of the synthesizer 1 can be sequentially connected to a power amplifier (PA) and an antenna. Among them, the PA can amplify the RF signal output by the synthesizer 1 to sufficient power and then transmit it through the antenna.

[0070] In some examples, the antenna can adopt a single antenna unit to reduce the structural complexity and power consumption. In other examples, the antenna can also adopt multiple antenna units, such as a phased array, to improve the signal quality.

[0071] The above Figure 1 The circuit that can implement 2N-order modulation can be called a modulation unit U. That is, each modulation unit U can include the above-mentioned N first switches 11, N QPSK modulation branches 12 and a synthesizer 13.

[0072] In some embodiments, as described above Figure 1 and Figure 2 shown, the transmitting circuit can include a modulation unit U, that is, the transmitting circuit adopts a single modulation unit U.

[0073] In other embodiments, the transmitting circuit may also include multiple modulation units U. That is, multiple modulation units U can be aggregated in the transmitting circuit to better meet the large bandwidth requirements. Two possible aggregation architectures are provided below.

[0074] Zero-IF architecture

[0075] In this architecture, each modulation unit U uses a different carrier frequency, and directly aggregates the first RF signals generated by each modulation unit U in the RF domain to generate a large-bandwidth signal (i.e., the target RF signal).

[0076] As Figure 3 shown, in this architecture, the transmitting circuit may include M switches SW2 (also referred to as the second switches), M modulation units (U1 to UM), and a synthesizer 2 (also referred to as the second synthesizer). M is a positive integer greater than 1.

[0077] The switches SW2 are in one-to-one correspondence with the modulation units. The switch SW2 is connected to the N switches SW1 of the corresponding modulation unit through DeMux1; the synthesizer 2 is respectively connected to the output ends of the modulation units, and is used to combine the first RF signals (denoted as RF1 in the figure) output by each modulation unit into a target RF signal.

[0078] The frequencies of the carrier signals adopted by each modulation unit (i.e., the carrier frequencies) are different from each other. It can be understood that the carrier frequency described in the embodiments of the present application refers to the center frequency of the carrier signal, and the frequencies of the LO signal and the RF signal described hereinafter also refer to the center frequency.

[0079] In some examples, assuming that the bandwidth of each modulation unit is B Hertz (Hz), the carrier frequencies of the first to the Mth modulation units may increase in sequence, and the carrier frequencies of adjacent modulation units may differ by B Hz. That is, the center frequencies of the first RF signals output by each modulation unit differ by B Hz. In this way, after the first RF signals are aggregated by the synthesizer 2, a target RF signal with a bandwidth of M×B Hz can be generated; moreover, the spectra of adjacent first RF signals have no overlap and no gap, so that the interference between signals can be reduced and the spectral efficiency can be improved.

[0080] Among them, the number M of modulation units may be 3 or 4, etc., and the specific size can be set according to actual needs, and this embodiment does not make special limitations on this. Similar to the aforementioned N QPSK modulation branches 12, in the embodiments of the present application, the arrangement order of the modulation units corresponding to the first to the Mth in the actual circuit is not particularly limited.

[0081] The switch SW2 can control the corresponding modulation unit to be turned on or off. That is, when the switch SW2 corresponding to the modulation unit is turned on, the modulation unit is turned on and a first RF signal can be generated; when the switch SW2 corresponding to the modulation unit is turned off, the modulation unit is turned off and no first RF signal is generated. Through the switch SW2, the number of modulation units to be turned on can be controlled, that is, the number of first RF signals to be aggregated can be controlled, so that the bandwidth can be flexibly adjusted according to system requirements.

[0082] For example, Y modulation units can be turned on by switch SW2 to form a target RF signal with a bandwidth of Y×B Hz, where Y≤M.

[0083] Each switch SW2 can be an independent device or integrated together.

[0084] Synthesizer 2 is similar to Synthesizer 1 and can combine the first RF signals output by each modulation unit into one RF signal (i.e., the target RF signal), which can specifically be a power synthesizer.

[0085] The carrier frequency of the modulation unit is the frequency of the LO signal (hereinafter referred to as the target LO signal) used by this modulation unit. In some embodiments, as Figure 3 shown, the target LO signals of each modulation unit can be generated by LO and a frequency multiplier (FM). Among them, the output end of LO can be respectively connected to M FMs, and the FMs can perform frequency multiplication processing on the input LO signal to generate corresponding target LO signals.

[0086] Among them, the center frequency of the LO signal generated by LO can be B Hz, the center frequency of the target LO signal output by the first FM can be Z×B Hz, the center frequency of the target LO signal output by the second FM can be (Z + 1)×B Hz, and so on. The center frequency of the target LO signal output by the Mth FM can be (Z + M - 1)×B Hz. That is, the center frequencies of the target LO signals used by the 1st to Mth modulation units increase in sequence, and the center frequencies of the target LO signals corresponding to adjacent modulation units differ by B Hz.

[0087] The magnitude of the multiplication factor Z of the first FM can be set according to actual needs, and this embodiment does not make special limitations on this.

[0088] In some embodiments, as Figure 3 shown, the input ends of each switch SW2 can be connected to DeMux2 (which can also be called the second demultiplexer), and this DeMux2 can decompose the input bit stream into multiple sub-bit streams. As Figure 3 shown in, DeMux2 can adopt a 1:M DeMux, that is, DeMux2 can decompose the input bit stream into M sub-bit streams. For each sub-bit stream decomposed by DeMux2, DeMux1 can further decompose it into multiple sub-bit streams and output them to the corresponding QPSK modulation branch 12.

[0089] During specific operation, DeMux2 can decompose the input bit stream into Y sub-bit streams according to the conduction quantity Y of switch SW2 and output them to the turned-on modulation units correspondingly.

[0090] In some embodiments, the transmitting circuit may also include a bitstream generation module (not shown), which is connected to the input end of DeMux2 and is used to convert the signal to be transmitted into a bitstream and then output it to DeMux2.

[0091] In some embodiments, such as Figure 3 shown, the output end of synthesizer 2 may be sequentially connected to the PA and the antenna. Among them, the PA can amplify the target RF signal output by synthesizer 2 to sufficient power and then transmit it through the antenna.

[0092] The above introduced the zero-IF architecture. Next, another aggregation architecture (the second up-conversion architecture) will be described.

[0093] Second up-conversion architecture

[0094] In this architecture, each modulation unit can generate a first RF signal using a carrier signal of the same frequency. The first RF signal is an intermediate frequency (IF) signal; then, after up-converting each first RF signal with carrier signals of different frequencies, they can be aggregated into a target RF signal.

[0095] Such as Figure 4 shown, the difference between this architecture and the above Figure 3 shown zero-IF architecture mainly lies in that each modulation unit is connected to synthesizer 2 through a mixer. The mixer is used to perform up-conversion processing on the first RF signal output by the connected modulation unit and then output it to synthesizer 2; among them, the carrier signals adopted by each modulation unit are the same, and the frequencies of the up-converted first RF signals (hereinafter referred to as the second RF signals, represented by RF2 in the figure) output by each mixer are different.

[0096] Similar to the zero-IF architecture, the bandwidth of each modulation unit is B Hz. The center frequencies of the LO signals (i.e., carrier signals) adopted by the 1st to the Mth mixers can increase sequentially, and the center frequencies of the LO signals adopted by adjacent mixers can differ by B Hz. That is, the center frequencies of the second RF signals output by each mixer differ by B Hz. In this way, after the second RF signals are aggregated by synthesizer 2, a target RF signal with a bandwidth of M×B Hz can be generated; moreover, the spectra of adjacent second RF signals have no overlap and no gap, so the interference between signals can be reduced and the spectral efficiency can be improved.

[0097] In some embodiments, such as Figure 4As shown, the transmitting circuit may further include LO1, LO2, and M FMs. LO1 is connected to the IQ modulators of each modulation unit and is used to output a first LO signal to each modulation unit. Each modulation unit may generate a corresponding first RF signal based on the first LO signal. LO2 is connected to the M FMs and is used to output a second LO signal to each FM. The FMs are in one-to-one correspondence with the mixers and are used to perform frequency doubling processing on the input second LO signal and then output it to the corresponding mixer.

[0098] Among them, the relevant introduction of LO1 can be referred to the relevant description of LO in the foregoing Figure 2 shown embodiment. The relevant introduction of LO2 and FM can be referred to the relevant description in the foregoing Figure 3 shown embodiment and will not be elaborated here.

[0099] The above aggregation architecture can achieve the target RF signal with large bandwidth by aggregating the first RF signals generated by multiple modulation units, which can reduce the bandwidth requirements for each modulation unit, thus reducing the requirements for radio frequency devices and further reducing the hardware implementation difficulty. Moreover, the number of modulation units that need to be turned on can be controlled through the switch SW2, so that the bandwidth can be flexibly adjusted according to system requirements.

[0100] Among them, the zero-IF architecture has relatively low structural complexity; the second up-conversion architecture can reduce the requirements for radio frequency devices and improve system stability. In specific implementation, it can be selected according to needs.

[0101] It can be understood that the structure schematically shown in the embodiments of the present application does not constitute a specific limitation on the transmitting circuit. In other embodiments of the present application, the modulation unit may include more or fewer components than shown in the figure, or combine certain components, or split certain components, or arrange different components. For example, in some examples, filters and the like may also be included in the transmitting circuit or the modulation unit. The functional characteristics of the components shown in the figure can be implemented in the form of hardware, or in the form of software, or in the form of a combination of software and hardware.

[0102] The transmitting circuit provided by the embodiments of the present application does not require a high-speed DAC device, so it can reduce the system power consumption, and it can be used in application scenarios such as display-computation separation, high-speed file transmission between devices, and high-speed transmission between chips.

[0103] The transmitting circuit has reconfigurable characteristics and can adjust the modulation order and total bandwidth according to different requirements in practical applications. For example, different transmission speeds and power consumptions can be achieved for different applications. Specifically, for applications with a large amount of transmitted data or high transmission speed requirements, a higher modulation order and / or a larger bandwidth can be adopted to achieve high-speed transmission; for applications with a small amount of transmitted data or low transmission speed requirements, a lower modulation order and / or a smaller bandwidth can be adopted to reduce power consumption. Among them, the modulation order can be controlled by controlling the number of turned-on first switches, and the bandwidth size can be controlled by controlling the number of turned-on second switches.

[0104] Also, for the same application, the modulation order and bandwidth can be adjusted in real time according to its traffic demand to reduce resource waste. Specifically, when the traffic demand is large, a higher modulation order and / or a larger bandwidth can be adopted to increase the transmission speed; when the traffic demand is small, a lower modulation order and / or a smaller bandwidth can be adopted to save processing resources and reduce power consumption.

[0105] In addition, in practical applications, the modulation order and total bandwidth can also be flexibly adjusted according to the bandwidth resources and hardware capabilities of different frequency bands. For example, in high-frequency scenarios, the bandwidth resources are rich, but high-frequency signals have high requirements for radio frequency devices. In the case where radio frequency devices are difficult to balance high-order modulation, multiple modulation units can be turned on to generate large-bandwidth signals, and each modulation unit uses low-order modulation to balance the transmission speed and signal quality. In low-frequency scenarios, the bandwidth resources are insufficient, but low-frequency signals have low requirements for radio frequency devices, and radio frequency devices have sufficient capabilities to implement high-order modulation. Then, fewer modulation units can be turned on, and the modulation units use high-order modulation to meet the bandwidth requirements while increasing the transmission speed.

[0106] Based on the same inventive concept, the embodiment of the present application also provides a transmitter, which includes the transmitting circuit described in the above embodiment.

[0107] In some examples, the transmitter may further include a controller for controlling related devices in the transmitting circuit, such as controlling the on / off of each first switch and second switch.

[0108] In some examples, the transmitter may further include other devices, and the specific structure of the transmitter is not particularly limited in the embodiment of the present application.

[0109] Among them, the relevant description of the transmitting circuit in the transmitter can be referred to the foregoing embodiment, and will not be elaborated here.

[0110] In the above embodiments, the descriptions of each embodiment have their own emphases. For parts not detailed or recorded in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0111] In the embodiments provided in this application, it should be understood that the disclosed device / equipment can be implemented in other ways. For example, the device / equipment embodiments described above are merely illustrative. For example, the division of the modules or units is only a logical function division. In actual implementation, there may be other division methods. For example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the displayed or discussed coupling or direct coupling or communication connection to each other can be through some interfaces. The indirect coupling or communication connection of the device or unit can be in electrical, mechanical or other forms.

[0112] It should be understood that in the description of this application's specification and the appended claims, the terms "include", "comprise", "have" and any variations thereof are intended to cover non-exclusive inclusion, all meaning "including but not limited to", unless otherwise specifically emphasized in other ways. For example, a process, method, system, product or equipment that includes a series of steps or modules does not have to be limited to those steps or modules clearly listed, but may include other steps or modules not clearly listed or inherent to these processes, methods, products or equipment.

[0113] In the description of this application, unless otherwise specified, " / " means that the objects associated before and after are in an "or" relationship. For example, A / B can mean A or B; the "and / or" in this application is used to describe the association relationship of associated objects, indicating that there can be three relationships. For example, A and / or B can mean: A exists alone, A and B exist simultaneously, and B exists alone. These three situations, where A and B can be singular or plural.

[0114] Moreover, in the description of this application, unless otherwise specified, "a plurality of" means two or more than two. "At least one of the following" or its similar expressions refer to any combination of these items, including any combination of single items or plural items. For example, at least one of a, b, or c can mean: a, b, c, a - b, a - c, b - c, or a - b - c, where a, b, c can be single or multiple.

[0115] In addition, in the description of this application's specification and the appended claims, the terms "first", "second", etc. are used to distinguish similar objects and do not have to be used to describe a specific order or sequence, nor can they be understood as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. It should be understood that such data can be interchanged under appropriate circumstances so that the embodiments described here can be implemented in an order other than that illustrated or described here; the features defined with "first" and "second" can explicitly or implicitly include at least one of such features.

[0116] In addition, in this application, unless otherwise clearly specified and defined, terms such as "connection" and "being connected" shall be understood in a broad sense. For example, it may be a direct connection or an indirect connection through an intermediate medium, and it may be the internal connection of two components or the interaction relationship between two components. Unless otherwise clearly defined, those of ordinary skill in the art can understand the specific meanings of the above terms in this application according to specific circumstances.

[0117] In the embodiments of this application, words such as "exemplarily" or "for example" are used to represent examples, illustrations or explanations. Any embodiment or design solution described as "exemplarily" or "for example" in the embodiments of this application should not be construed as being more preferred or having more advantages than other embodiments or design solutions. Exactly speaking, using words such as "exemplarily" or "for example" aims to present relevant concepts in a specific way.

[0118] The reference to "one embodiment" or "some embodiments" etc. described in the specification of this application means that a specific feature, structure or characteristic described in connection with the embodiment is included in one or more embodiments of this application. Thus, statements such as "in one embodiment", "in some embodiments", "in other some embodiments", "in still other embodiments" etc. that appear in different places in this specification do not necessarily refer to the same embodiment, but mean "one or more but not all embodiments", unless otherwise specifically emphasized in other ways.

[0119] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application, rather than to limit them; although this application has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still modify the technical solutions recorded in the foregoing embodiments, or perform equivalent replacements on some or all of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. A transmitting circuit, characterized in that, Comprising: N first switches; N is a positive integer greater than 1; N quadrature phase shift keying (QPSK) modulation branches, the QPSK modulation branches corresponding one-to-one with the first switches, and the input ends of the QPSK modulation branches being connected to the corresponding first switches; The QPSK modulation branches are used to generate QPSK signals; the amplitudes of the QPSK signals respectively generated by the QPSK modulation branches are different from each other; A first synthesizer, connected to the output ends of the QPSK modulation branches, for combining the QPSK signals output by the QPSK modulation branches into a first radio frequency (RF) signal.

2. The transmitting circuit according to claim 1, wherein The QPSK modulation branch includes a QPSK modulation circuit and a gain amplifier; the QPSK modulation circuit is used to generate a modulation signal; the gain amplifier is connected to the output end of the QPSK modulation circuit, for amplifying the modulation signal to obtain the QPSK signal; The gains of the gain amplifiers corresponding to the QPSK modulation branches are different from each other.

3. The transmitting circuit according to claim 2, wherein The gains of the gain amplifiers corresponding to the 1st to Nth QPSK modulation branches decrease in sequence, and the gains of the gain amplifiers corresponding to adjacent QPSK modulation branches differ by 6 dB.

4. The transmitting circuit according to claim 2 or 3, characterized in that, The QPSK modulation circuit includes a symbol mapping module and an IQ modulator connected in series; the symbol mapping module is used to perform symbol mapping on the input bit stream to obtain a baseband signal; the IQ modulator is used to modulate a carrier signal according to the baseband signal to generate the modulation signal.

5. The transmitting circuit according to any one of claims 1-4, characterized in that, The transmitting circuit further includes a first demultiplexer, a power amplifier, and an antenna; The first demultiplexer is respectively connected to the input ends of the first switches; the input end of the power amplifier is connected to the output end of the first synthesizer, and the output end of the power amplifier is connected to the antenna; The carrier signals adopted by the QPSK modulation branches are the same.

6. The transmitting circuit according to any one of claims 1-4, characterized in that, The transmitting circuit includes M second switches, M modulation units, and a second synthesizer, and each modulation unit includes the N first switches, the N QPSK modulation branches, and the first synthesizer; M is a positive integer greater than 1; The second switches correspond one-to-one with the modulation units, and the second switches are connected to the N first switches of the corresponding modulation units through a first demultiplexer; The second synthesizer is respectively connected to the output ends of the modulation units, for combining the first RF signals output by the modulation units into a target RF signal.

7. The transmitting circuit according to claim 6, wherein The frequencies of the carrier signals adopted by the modulation units are different from each other.

8. The transmitting circuit according to claim 6, wherein Each modulation unit is connected to the second synthesizer through a mixer, and the mixer is used to perform up-conversion processing on the first RF signal output by the connected modulation unit and then output it to the second synthesizer; The carrier signals adopted by the modulation units are the same, and the frequencies of the up-converted first RF signals output by the mixers are different.

9. The transmitting circuit according to any one of claims 6-8, characterized in that, The transmitting circuit further includes a second demultiplexer, a power amplifier, and an antenna; The second demultiplexer is respectively connected to the input ends of the second switches; the input end of the power amplifier is connected to the output end of the second synthesizer, and the output end of the power amplifier is connected to the antenna.

10. A transmitter, characterized in that, Comprising a transmitting circuit as described in any one of claims 1-9.

Images