Static time sequence analysis method and device, server and storage medium

Abstract

The invention provides a static time sequence analysis method and device, a server and a storage medium, and is applied to the technical field of computers. The method comprises the following steps: obtaining an average voltage drop value corresponding to each polarity overturning event of each logic unit in an integrated circuit in a target time interval; determining the actual voltage value of each logic unit in each clock period, determining the actual unit delay corresponding to the actual voltage value of each logic unit, and finally determining the establishment time margin and the retention time margin of the time sequence path according to the actual unit delay of each logic unit. According to the method, the actual voltage value of the corresponding logic unit is determined based on the difference between the nominal voltage and the average voltage drop value, the influence of voltage fluctuation in the power supply network on the actual working voltage of the logic unit is considered, and the actual unit delay determined based on the actual voltage value is reversely marked; and the reliability of the retention time margin and the establishment time margin obtained through calculation is ensured, so that the accuracy of a static time sequence analysis result is improved.

Description

Technical Field

[0001] The present application relates to the field of computer technology, and in particular to a static timing analysis method, device, server, and storage medium. Background Art

[0002] After the integrated circuit (or chip) design is completed, static timing analysis (STA) is required to confirm whether the integrated circuit has timing errors. Traditional STA analysis is based on the assumption of an idealized power network, which assumes that all logic cells can always obtain a stable nominal voltage during operation.

[0003] However, during actual testing, when integrated circuits are in high-load or high-flip rate scenarios, such as the Design For Test (DFT) test mode, the parasitic resistance, parasitic capacitance, and parasitic inductance of the power supply network will cause instantaneous voltage fluctuations in local areas. This voltage fluctuation may significantly change the transmission delay characteristics of the logic unit, causing normally functioning integrated circuits to be misjudged as defective in high-flip rate scenarios such as DFT testing, thereby reducing the screening yield of the integrated circuits, low test result accuracy, and even affecting the design cycle of the integrated circuits. Summary of the Invention

[0004] In view of this, the present application is dedicated to providing a static timing analysis method, device, server and storage medium to solve the problem in the prior art that the low accuracy of static timing analysis results leads to low yield of integrated circuit screening and affects the design cycle.

[0005] In a first aspect, the present application provides a static timing analysis method, comprising:

[0006] Obtaining an average voltage drop value corresponding to each polarity reversal event of each logic unit in the integrated circuit within a target time interval, wherein the target time interval includes multiple clock cycles;

[0007] Determine an actual voltage value of each logic unit in each clock cycle, where the actual voltage is the difference between the nominal voltage corresponding to the logic unit and the corresponding average voltage drop value;

[0008] determining an actual cell delay corresponding to an actual voltage value of each logic cell;

[0009] The setup time margin and the hold time margin of the corresponding timing path are determined according to the actual unit delay of each logic unit.

[0010] In an optional embodiment, obtaining an average voltage drop value corresponding to each polarity reversal event of each logic unit in the integrated circuit within a target time interval includes:

[0011] Obtaining a waveform file, wherein the waveform file records a waveform output by the integrated circuit in response to a test stimulus within a preset time length;

[0012] Dividing the preset duration into a plurality of time intervals, and respectively calculating the power consumption of the integrated circuit in each of the time intervals according to the waveform file;

[0013] Determine the time interval with the largest power consumption among the time intervals as the target time interval;

[0014] An average voltage drop value corresponding to each polarity reversal event within the target time interval is determined for each logic unit of the integrated circuit.

[0015] In an optional implementation, determining the actual voltage value of each logic unit in each clock cycle includes:

[0016] Analyze the output polarity of each logic unit in each timing path of the integrated circuit step by step;

[0017] Determining a polarity reversal event corresponding to each logic unit and an average voltage drop value corresponding to the polarity reversal event according to the output polarity change;

[0018] Based on the corresponding relationship between the polarity reversal event and the clock cycle, the actual voltage value of each logic unit in each clock cycle is determined.

[0019] In an optional embodiment, the logic unit includes a clock unit, a timing unit and a data unit;

[0020] Determining the actual voltage value of each logic unit in each clock cycle includes:

[0021] Determine an actual voltage value of each clock unit, sequential unit, and data unit in a first clock cycle, and an actual voltage value of each clock unit and sequential unit in a second clock cycle;

[0022] The first clock cycle is any clock cycle in the target time interval, and the second clock cycle is a clock cycle next to the first clock cycle.

[0023] In an optional embodiment, the timing path of the integrated circuit includes a transmission path, a data path, and a capture path;

[0024] The determining of the actual voltage value of each clock unit, timing unit, and data unit in the first clock cycle, and the actual voltage value of each clock unit and timing unit in the second clock cycle, includes:

[0025] Determine an actual voltage value of each clock unit in the transmit path and the capture path and each timing unit and data unit in the data path in a first clock cycle;

[0026] And, determining the actual voltage value of each clock unit and timing unit in the capture path in the second clock cycle.

[0027] In an optional embodiment, the timing path of the integrated circuit includes a clock path and a data path;

[0028] The step-by-step analysis of the output polarity of each logic unit of each timing path in the integrated circuit includes:

[0029] Starting from the clock origin of the clock path, analyze the output polarity of each clock unit in the clock path step by step;

[0030] Starting from the output end of the sequential unit of the data path, the output polarity of each sequential unit and data unit in the data path is analyzed step by step.

[0031] In an optional implementation, the process of determining the actual unit delay corresponding to the actual voltage value of any logic unit includes:

[0032] Acquire a preset mapping relationship, where the preset mapping relationship includes a correspondence between a voltage value of a logic unit and a unit delay;

[0033] According to the preset mapping relationship, an actual unit delay corresponding to the actual voltage value of the logic unit is determined.

[0034] In an optional implementation, the process of determining the actual unit delay corresponding to the actual voltage value of any logic unit includes:

[0035] Obtaining a standard cell timing library file, wherein the standard cell timing library file records cell delays of different logic cells at different nominal voltages;

[0036] Extracting the target nominal voltage of the logic unit and the target cell delay corresponding to the target nominal voltage recorded in the standard cell timing library file;

[0037] An interpolation calculation is performed based on the target nominal voltage, the target unit delay, and the actual voltage value of the logic unit to obtain the actual unit delay of the logic unit.

[0038] In an optional implementation manner, determining the setup time margin and the hold time margin of the corresponding timing path according to the actual unit delay of each logic unit includes:

[0039] Determine setup time margins of timing paths to which the clock unit, the sequential unit, and the data unit belong based on actual unit delays of the clock unit, the sequential unit, and the data unit in the first clock cycle and actual unit delays of the clock unit and the sequential unit in the second clock cycle;

[0040] According to actual unit delays of the clock unit, the timing unit, and the data unit in the first clock cycle, hold time margins of timing paths to which the clock unit, the timing unit, and the data unit belong are determined.

[0041] In an optional implementation, the method further includes: performing timing repair on a timing path having a setup time violation and / or a hold time violation in the integrated circuit.

[0042] In a second aspect, the present application provides a static timing analysis device, comprising:

[0043] an acquisition unit, configured to acquire an average voltage drop value corresponding to each polarity reversal event of each logic unit in the integrated circuit within a target time interval, wherein the target time interval includes a plurality of clock cycles;

[0044] A first determining unit is configured to determine an actual voltage value of each logic unit in each clock cycle, where the actual voltage is the difference between a nominal voltage corresponding to the logic unit and a corresponding average voltage drop value;

[0045] a second determining unit, configured to determine an actual unit delay corresponding to an actual voltage value of each logic unit;

[0046] The analysis unit is used to determine the setup time margin and the hold time margin of the corresponding timing path according to the actual unit delay of each logic unit.

[0047] In a third aspect, the present application provides a server comprising a memory, a processor, and a computer program stored in the memory and executed by the processor. When the processor executes the computer program, the steps of the static timing analysis method as described in any one of the first aspects of the present application are implemented.

[0048] In a fourth aspect, the present application provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the steps of the static timing analysis method as described in any one of the first aspects of the present application.

[0049] Based on the above content, through the static timing analysis method provided by the present application, after obtaining the average voltage drop value corresponding to each polarity reversal event of each logic unit in the integrated circuit within the target time interval, the actual voltage value of each logic unit in each clock cycle is determined, and the actual unit delay corresponding to the actual voltage value of each logic unit is determined. Finally, the setup time margin and the hold time margin of the corresponding timing path are determined according to the actual unit delay of each logic unit. It can be seen that this method determines the actual voltage value of the corresponding logic unit based on the difference between the nominal voltage and the average voltage drop value, considers the impact of voltage fluctuations in the power supply network on the actual working voltage of the logic unit during the actual test process, and further reverses the actual unit delay determined based on the actual voltage value to ensure the reliability of the calculated hold time margin and setup time margin, thereby improving the accuracy of the static timing analysis results, reducing the impact of high reversal rate scenarios such as DFT testing on the analysis results, and thereby reducing the possibility of misjudgment of integrated circuits, which helps to improve the yield of integrated circuit screening. BRIEF DESCRIPTION OF THE DRAWINGS

[0050] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0051] Figure 1 This is a flow chart of a static timing analysis method provided by this application.

[0052] Figure 2 It is a structural diagram of a timing path in an integrated circuit.

[0053] Figure 3 It is a schematic diagram of the average voltage drop of the logic unit under different clock cycles.

[0054] Figure 4 It is a structural diagram of another timing path in an integrated circuit.

[0055] Figure 5 It is a waveform diagram showing the relationship between the output polarity of the logic unit in the integrated circuit and the clock period.

[0056] Figure 6 This is a structural block diagram of a static timing analysis device provided by this application.

[0057] Figure 7 This is a structural diagram of a server provided by this application. DETAILED DESCRIPTION

[0058] The following will be combined with the drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are only part of the embodiments of this application, not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0059] In current integrated circuit (or chip) design specifications, static timing analysis is a critical step in IC design signoff. Only after static timing analysis has been completed and confirmed to be free of timing violations can subsequent design work proceed. Traditional STA analysis assumes an idealized power supply network, assuming that all logic cells always receive a stable nominal voltage during operation.

[0060] However, during the actual testing process, when the integrated circuit is in high-load or high-toggle rate scenarios, such as the DFT test mode, the parasitic resistance, parasitic capacitance, and parasitic inductance of the power supply network will cause instantaneous voltage fluctuations in the local area. This voltage fluctuation is usually referred to as power supply noise in the industry. Power supply noise may significantly change the actual operating voltage of the logic unit, thereby affecting the transmission delay characteristics of the logic unit. As a result, in high-toggle rate scenarios such as DFT testing, the timing violations caused by the DFT circuit are attributed to the timing violations in the implementation of the integrated circuit's logic function, and the normally functioning integrated circuit is misjudged as a defective product, reducing the screening yield of the integrated circuit, low test result accuracy, and even affecting the design cycle of the integrated circuit.

[0061] To solve the above problems, the present application provides a static timing analysis method, which determines the actual voltage value of the corresponding logic unit based on the difference between the nominal voltage and the average voltage drop value, takes into account the impact of voltage fluctuations in the power supply network on the actual operating voltage of the logic unit during actual testing, and further back-labels the actual unit delay determined based on the actual voltage value to ensure the reliability of the calculated hold time margin and setup time margin, thereby improving the accuracy of the static timing analysis results, reducing the impact of high reversal rate scenarios such as DFT testing on the analysis results, and thus reducing the possibility of misjudgment of integrated circuits, which helps to improve the yield of integrated circuit screening.

[0062] The static timing analysis method provided by this application is applied to electronic devices, which may be laptops, personal computers (PCs), tablet computers, and other electronic devices that can run the application corresponding to the physical design method provided by this application. These are not listed here one by one. Of course, in some cases, it can also be applied to servers on the network side. Figure 1 As shown, the static timing analysis method provided by this application includes the following steps.

[0063] S100 , obtaining an average voltage drop value corresponding to each polarity reversal event of each logic unit in the integrated circuit within a target time interval.

[0064] In the related art, based on their functions, various sub-circuits in integrated circuits can be divided into two types: combinational logic circuits and sequential logic circuits (i.e., sequential circuits). Combinational logic circuits have outputs that depend solely on their current inputs and lack memory. Sequential circuits, in addition to basic logic gate units, also contain storage elements such as registers to store past information. Their steady-state output depends not only on their current inputs but also on the state formed by past inputs. Furthermore, each sequential circuit corresponds to a sequential path. Furthermore, integrated circuits are constructed by interconnecting a large number of logic units according to a pre-set connection relationship. Logic units can be roughly divided into three categories: data units, sequential units, and clock units. Data units are used to transmit data, such as AND gates and OR gates. Sequential units are unit modules that store data and rely on clock signals to control state updates, such as flip-flops and latches. Clock units are primarily used to transmit clock signals, such as buffers. Other types of logic units are also included, which are not discussed in detail here.

[0065] Based on the above, see Figure 2 , Figure 2 The following is a schematic diagram of the typical sequential circuit structure in an integrated circuit. When performing static timing analysis on the sequential path, the sequential path is divided into three parts, namely the launch path, the data path, and the capture path. Figure 2 As shown, the transmit path and the capture path are built based on several clock units. Accordingly, the clock unit in the transmit path can be defined as a transmit clock unit, and the clock unit in the capture path can be defined as a capture clock unit. There may be multiple data units and timing units in the data path, such as Figure 2 The register FF1, register FF2, NAND gate g1 and AND gate gx are shown, where x is an integer greater than 1. Of course, the functions of the data paths are different, and the types of data units contained therein will also be different, so they are not listed here one by one.

[0066] In order to accurately simulate the power supply noise of the integrated circuit during actual operation, the waveform file mentioned in this application can be obtained by applying a test stimulus.

[0067] In an optional implementation, the ATPG (Auto Pattern Generator) tool used in the DFT testing process can be used to apply test stimulus to the integrated circuit. ATPG uses an algorithm to describe the integrated circuit and automatically generates test stimulus (which can be viewed as high and low levels with flip-flop timing information) capable of detecting all faults in the integrated circuit. During the actual testing process, the ATPG tool applies the test stimulus to the integrated circuit for a preset duration. In response to the test stimulus, the integrated circuit generates different waveform changes. By recording the waveform changes, a waveform file is generated. In other words, the waveform file records the changes and duration of "0" and "1" at each circuit output node within the integrated circuit.

[0068] Based on the obtained waveform file, a dynamic voltage drop analysis is performed on the integrated circuit. Specifically, the preset duration of applying the test stimulus to the integrated circuit is divided into multiple time intervals, each time interval includes multiple clock cycles. Assuming that the preset duration is 100ns, it is divided into 10 time intervals, each time interval corresponds to a duration of 10ns. If the clock cycle is 1ns, each time interval includes 10 clock cycles. Further, the power consumption corresponding to the integrated circuit in each time interval is calculated based on the waveform file. For example, the average power consumption of the integrated circuit in each clock cycle in the time interval can be calculated, and the sum of the average power consumption of each clock cycle is the power consumption corresponding to the corresponding time interval. As for the specific calculation method of the average power consumption of the integrated circuit in any clock cycle, it can be implemented with reference to relevant technologies, and this application does not limit this. After obtaining the power consumption of the integrated circuit in each time interval, this application takes the time interval with the largest power consumption in each time interval as the target time interval.

[0069] After selecting the target time interval, the average voltage drop corresponding to each polarity reversal event of each logic unit in the integrated circuit within the target time interval is further determined. As previously described, in response to the test stimulus, the output level of the internal logic unit of the integrated circuit will change, for example, from 0 to 1, that is, from a low level to a high level, and correspondingly, from 1 to 0, that is, from a high level to a low level. Based on this, when the output level of any logic unit flips from a low level to a high level, a rising edge flip event occurs, and correspondingly, when the output level of any logic unit flips from a high level to a low level, a falling edge flip event occurs.

[0070] Based on the definition of polarity reversal events, it is necessary to further analyze the current consumed by each logic unit when a polarity reversal event occurs. At the same time, combined with the equivalent impedance of the power supply network in the integrated circuit, the average voltage drop value corresponding to each polarity reversal event occurring in each logic unit within the target time interval can be calculated. As for the specific calculation process, it can be implemented by referring to the dynamic voltage drop analysis method in the relevant technology, which will not be described in detail here. Figure 3 As shown in Figure 1, the propagation of the logic unit output level (i.e., the transmitted signal) changes as the clock cycle changes. Figure 3 In the above code, input represents the input of the logic unit, output represents the output of the logic unit, cycle represents the clock cycle, V C1 is the average voltage drop of the logic unit during the duration of the polarity reversal event in the first clock cycle, V C2 is the average voltage drop of the logic unit during the duration of the polarity reversal event in the second clock cycle; d C1 and d C2 These correspond to the actual unit delays of the logic unit in the first clock cycle and the second clock cycle respectively. The actual unit delays of the logic unit will be expanded in subsequent content and will not be described in detail here.

[0071] According to the above and Figure 3 As shown, the final output of this step is the average voltage drop corresponding to each polarity reversal event occurring in each logic cell within the target time interval. Furthermore, because the timing of polarity reversal events in each logic cell during the dynamic voltage drop analysis process generally aligns with the actual operating scenario of the integrated circuit, the impact of power supply noise on the actual operating voltage of each logic cell in actual integrated circuit applications can be accurately simulated, providing more reliable analysis results.

[0072] S110 , determining an actual voltage value of each logic unit in each clock cycle.

[0073] During the integrated circuit design process, each logic unit in the integrated circuit corresponds to a nominal voltage that meets its normal operating requirements. Due to the influence of power supply noise, the voltage provided by the power supply network to the logic unit will attenuate to varying degrees, that is, a voltage drop will occur, causing the actual voltage applied to the logic unit to be lower than the nominal voltage. Based on the basic principles of circuits, it can be known that the actual voltage drop of each logic unit is equal to the difference between the nominal voltage of the logic unit and its corresponding average voltage drop value.

[0074] As mentioned above, when a polarity reversal event occurs in any logic unit, it means that its output polarity changes, such as from a low level to a high level, or from a high level to a low level. Based on the working principle of the logic unit, it can be seen that the output polarity of the logic unit changes with the clock cycle, which means that the output polarity change of the logic unit is uniquely corresponding to the clock cycle, that is, the polarity reversal event of the logic unit is uniquely corresponding to the clock cycle. However, the average voltage drop values corresponding to different clock cycles, that is, different polarity reversal events of the logic unit are not the same (because the influence of power supply noise is not stable). Therefore, it is necessary to determine the average voltage drop of each logic unit in the integrated circuit in each clock cycle based on the above steps, and then determine the actual voltage value corresponding to each logic unit in each clock cycle.

[0075] To achieve the above purpose, it is first necessary to analyze the output polarity of each logic unit in each timing path in the integrated circuit step by step. As mentioned above, any timing path in the integrated circuit can be divided into a clock path and a data path. Based on this, for the clock path, starting from the clock origin of the clock path, the output polarity of each clock unit in the clock path can be analyzed step by step according to the extension direction of the clock path. For example, if an inverter is provided in the clock path, the output polarity of the inverter will change compared with the previous stage; for the data path, starting from the output end of the timing unit of the data path, the output polarity of each timing unit and data unit in the data path is analyzed step by step. For example, the AND gate unit will only output a high level when all input ends are high.

[0076] based on Figure 2 The timing circuit diagram shown in the figure can be obtained as follows Figure 4 A specific timing path shown, combined with Figure 4 As shown, the timing path includes a clock unit BUF1, clock units INV1-INV6, timing units including registers FF1 and FF2, and data units g1-g3. Figure 4 The timing paths shown are shown in Figure 5 As shown in the waveform diagram, the horizontal axis T represents the clock cycle, t0 is the starting time of the target time interval, t1 is the first rising edge flip time of the clock signal, t2 is the first falling edge flip time of the clock signal, t3 is the second rising edge flip time of the clock signal, and t4 is the second falling edge flip time of the clock signal. Further, combined with Figure 4 As shown, BUF1, INV1 and INV2 are the clock units of the transmit path, INV3-INV6 are the clock units of the capture path, FF1 is a register, and g1-g3 are the data units on the data path. Figure 5 It can be seen that the output polarity and polarity changes of each logic unit in different clock cycles.

[0077] After determining the output polarity of each logic unit in each timing path, the output polarity change of each logic unit can be determined. Furthermore, the polarity reversal event corresponding to each logic unit can be determined based on the obtained output polarity change. For example, based on the output polarity identification result of register A, it is determined that the output polarity of register A switches from a low level to a high level. Then, it can be determined that a rising edge reversal event has occurred in register A. Since there is a unique correspondence between the polarity reversal event and the average voltage drop value, the average voltage drop value corresponding to the polarity reversal event can be further determined. By analogy, the average voltage drop value corresponding to each polarity reversal event of each logic unit in the integrated circuit can be obtained. Furthermore, based on the correspondence between the polarity reversal event and the clock cycle, the average voltage drop value of each logic unit in each clock cycle can be ultimately determined. Based on this, the difference between the nominal voltage of the logic unit and the average voltage drop in each clock cycle is calculated, that is, the actual voltage value corresponding to the logic unit in each clock cycle is obtained.

[0078] As mentioned above, the target time interval includes multiple clock cycles. When performing static timing analysis on an integrated circuit, it is necessary to perform analysis on each of the clock cycles. Based on this, as an optional implementation method, this application takes any clock cycle in the target time interval as the first clock cycle. It can be understood that in order to ensure that all clock cycles can be traversed, it is preferred to take each clock cycle as the first clock cycle in the order of the clock cycles in the target time interval, and accordingly, take the next clock cycle of the first clock cycle as the second clock cycle. Further, according to the above ideas, the actual voltage value of each clock unit, timing unit and data unit in the first clock cycle, as well as the actual voltage value of each clock unit and timing unit in the second clock cycle are determined. The reason for this operation is related to the calculation method of establishing the time margin and maintaining the time margin in the subsequent steps, which will not be described in detail here.

[0079] Furthermore, as previously described, the timing path of the integrated circuit can be divided into a transmit path, a data path, and a capture path. Based on this, the actual voltage value of each clock cell in the transmit path and the capture path, and each timing cell and data cell in the data path, can be determined for a first clock cycle, and the actual voltage value of each clock cell and timing cell in the capture path can be determined for a second clock cycle. The specific process for determining the actual voltage can be referenced above and will not be repeated here.

[0080] According to the above method, the actual voltage values corresponding to each logic unit in the integrated circuit at different clock cycles can be finally obtained. Taking the first clock cycle and the second clock cycle as an example, the structured data shown in Table 1 can be obtained. It can be understood that all the structural data can be obtained by traversing all the clock cycles in the target time interval, which will not be described in detail here.

[0081] Table 1

[0082]

[0083] S120 , determining an actual unit delay corresponding to an actual voltage value of each logic unit.

[0084] According to the operating principle of logic cells, the cell delay of a logic cell is directly related to the actual voltage value obtained by the logic cell. Similarly, the lower the actual voltage value of the logic cell, the longer the cell delay of the logic cell. For example, the cell delay of the same logic cell at 0.95V is longer than the cell delay at 1V. Based on this, after determining the actual voltage value of each logic cell, it is necessary to further determine the actual cell delay of each logic cell when operating at the corresponding actual voltage value, that is, to perform back-annotation of the actual cell delay.

[0085] In an optional embodiment, the present application provides a preset mapping relationship, which records the correspondence between the voltage value and the unit delay of each logic unit. For each logic unit in the integrated circuit, by querying the preset mapping relationship, the unit delay corresponding to each actual voltage value can be determined, that is, the actual unit delay corresponding to each actual voltage value of each logic unit.

[0086] It is understandable that there are a large number of logic units in an integrated circuit, and the actual voltage value of each logic unit is difficult to estimate. The establishment of the above-mentioned preset mapping relationship requires a large amount of data support and a lot of manpower and material resources. For this reason, this application provides another method for determining the actual unit delay.

[0087] Specifically, in actual applications, process manufacturers will provide standard cell timing library files for logic cells. These timing library files record the cell delays of various logic cells at different nominal voltages. Based on this, the target nominal voltage of the logic cell and the target cell delay corresponding to the target nominal voltage recorded in the standard cell timing library files are extracted. Based on the obtained target nominal voltage, target cell delay, and the actual voltage value corresponding to the logic cell, an interpolation operation is performed to obtain the actual cell delay of the logic cell at the actual voltage value. The actual cell delay corresponding to the actual voltage value of each logic cell at each clock cycle can be determined according to the above content.

[0088] Based on the interpolation calculation process, two of the aforementioned target nominal voltages need to be selected, namely the first target nominal voltage and the second target nominal voltage. As mentioned above, the standard power timing library file records multiple nominal voltages of the logic unit. Based on this, as a preferred implementation, the two nominal voltages closest to the actual voltage value of the logic unit among the multiple nominal voltages can be used as the target nominal voltages.

[0089] For example, the actual voltage value of register FF1 is 0.93V. The nominal voltages closest to this actual voltage value recorded in the standard timing library file are 0.90V and 0.95V. The target cell delay corresponding to the nominal voltage of 0.90V is 0.12ns, and the target cell delay corresponding to the nominal voltage of 0.95V is 0.10ns. The actual cell delay t of the logic cell when the actual voltage value is 0.93V can be obtained by interpolation calculation according to the following formula:

[0090]

[0091] The actual unit delay corresponding to the actual voltage value of any logic unit can be calculated according to the above method, which will not be described in detail here.

[0092] S130 , determining a setup time margin and a hold time margin of a corresponding timing path according to an actual unit delay of each logic unit.

[0093] In existing applications, data transmission in integrated circuits is based on clock signals. Each logic unit in the integrated circuit outputs different logic levels in response to changes in the clock signal, thereby achieving switching of different output polarities. Any logic unit may correspond to different output polarities in different clock cycles. Therefore, when performing static timing analysis on the integrated circuit, it is preferably performed according to the changes in the clock cycle, that is, the setup time margin and hold time margin of the integrated circuit in each clock cycle are calculated in chronological order, and finally a complete static timing analysis result is obtained.

[0094] Based on the above content, the setup time margin and hold time margin of the timing path to which each logic unit belongs can be calculated based on the actual voltage value and actual unit delay of each logic unit in the integrated circuit in the first clock cycle and the second clock cycle obtained by the above steps. Specifically, according to the definition of setup time margin and hold time margin in the relevant art, the setup time margin of the timing path to which the clock unit, timing unit and data unit belong can be determined based on the actual unit delay of the clock unit, timing unit and data unit in the first clock cycle and the actual unit delay of the clock unit and timing unit in the second clock cycle. Correspondingly, the hold time margin of the timing path to which the clock unit and data unit belong can be determined based on the actual unit delay of the clock unit, timing unit and data unit in the first clock cycle.

[0095] Combine Figure 4 As an example of the timing path shown in the figure, the transmission path in the timing path includes clock units BUF1, INV1 and INV2, the data path includes the timing unit register FF1, the clock unit NAND gate g1, AND gate g2 and AND gate g3, and the capture path includes clock units INV3-INV6. c1-x represents the actual unit delay of each corresponding logic unit determined through the above steps, where x=1-11.

[0096] Furthermore, according to the definition of setup time margin, setup time margin = data requirement time - data arrival time, for Figure 4 The timing path shown in the figure can be expressed as follows:

[0097] S1=s1+d C2_1 +d C2_8 +d C2_9 +d C2_10 +d C2_11

[0098] -(d C1_1 +d C1_2 +d C1_3 +d C1_4 +d C1_5 +d C1_6 +d C1_7 )-d C2_setup

[0099] Among them, d C2_setup s1 represents the setup time of register FF2, and s2 represents the clock cycle. It's understandable that the setup time check for register FF2 occurs on the rising edge of the clock immediately following the rising edge of the clock corresponding to the data captured by register FF1. Therefore, the capture path must include one clock cycle. Clock unit BUF1 is part of both the transmit and capture paths, and its delay varies due to voltage drops at different cycles, which must be accounted for. However, for the hold time check for register FF2, since both the transmit and capture clocks are in the same clock cycle, clock unit BUF1, acting as a common clock path, cancels out its delay in the calculation.

[0100] After the above steps, assuming that the data required time is 0.05ns and the data arrival time is 0.369ns, the setup time margin = 0.05-0.369 = -0.319ns. The setup time margin is negative, indicating that the data arrives later than the required time, and there is a setup time violation.

[0101] Accordingly, according to the definition of hold time margin, hold time margin = data arrival time - data requirement time, for Figure 4 For the timing path shown, its hold time margin can be expressed as follows:

[0102] S2=d C1_2 +d C1_3 +d C1_4 +d C1_5 +d C1_6 +d C1_7 -d C1_hold -(d C1_8 +d C1_9 +d C1_10 +d C1_11 )

[0103] Among them, d C1_hold Indicates the hold time value of register FF2.

[0104] After the above steps, assuming that the data arrival time is 0.369ns and the data required time is 0.09ns, the hold time margin = 0.369-0.09 = 0.279ns. The hold time margin is a positive value, indicating that the data arrival time meets the requirements and there is no hold time violation.

[0105] As for the static timing analysis process of other clock cycles in the target time area, it can be implemented by referring to the above content and will not be repeated here.

[0106] In summary, this method determines the actual voltage value of the corresponding logic unit based on the difference between the nominal voltage and the average voltage drop value, takes into account the impact of voltage fluctuations in the power supply network on the actual working voltage of the logic unit during the actual test process, and further back-annotates the actual unit delay determined based on the actual voltage value to ensure the reliability of the calculated hold time margin and setup time margin, thereby improving the accuracy of the static timing analysis results, reducing the impact of high reversal rate scenarios such as DFT testing on the analysis results, and thus reducing the possibility of misjudgment of integrated circuits, which helps to improve the yield of integrated circuit screening.

[0107] Furthermore, if, under any clock cycle, the aforementioned steps determine that at least one timing path in the integrated circuit has a timing violation, that is, there is at least one of a setup time violation and a hold time violation, timing repair can be performed on the timing path. As for the specific process of timing repair, reference can be made to relevant technologies and will not be described in detail here.

[0108] The following describes the static timing analysis method and apparatus provided by the present invention. The static timing analysis method and apparatus provided by the present invention are based on the same concept as the static timing analysis method provided in the embodiments of this application. They can execute the static timing analysis method provided in any embodiment of this application and possess the corresponding functional modules and beneficial effects of executing the static timing analysis method. For technical details not fully described in this embodiment, please refer to the static timing analysis method provided in the embodiments of this application and will not be further elaborated here.

[0109] See also Figure 6 , the static timing analysis device provided by this application specifically includes:

[0110] an acquisition unit, configured to acquire an average voltage drop value corresponding to each polarity reversal event of each logic unit in the integrated circuit within a target time interval, where the target time interval includes a plurality of clock cycles;

[0111] A first determining unit is used to determine an actual voltage value of each logic unit in each clock cycle, where the actual voltage is the difference between the nominal voltage corresponding to the logic unit and the corresponding average voltage drop value;

[0112] a second determining unit, configured to determine an actual unit delay corresponding to an actual voltage value of each logic unit;

[0113] The analysis unit is used to determine the setup time margin and the hold time margin of the corresponding timing path according to the actual unit delay of each logic unit.

[0114] Below, reference Figure 7 To describe the server provided by an embodiment of the present invention, the server provided by this embodiment may include: at least one processor 100, at least one communication interface 200, at least one memory 300 and at least one communication bus 400;

[0115] In the embodiment of the present invention, the number of the processor 100, the communication interface 200, the memory 300, and the communication bus 400 is at least one, and the processor 100, the communication interface 200, and the memory 300 communicate with each other through the communication bus 400; obviously, Figure 7 The communication connections shown for the processor 100, communication interface 200, memory 300, and communication bus 400 are merely optional;

[0116] Optionally, the communication interface 200 may be an interface of a communication module, such as an interface of a GSM module; the processor 100 may be a central processing unit (CPU), or an application specific integrated circuit (ASIC), or one or more integrated circuits configured to implement an embodiment of the present invention.

[0117] The memory 300 may include a high-speed RAM memory, and may also include a non-volatile memory (non-volatile memory), such as at least one disk memory.

[0118] The processor 100 is specifically configured to execute an application program in the memory to implement the steps of the static timing analysis method described above.

[0119] In some embodiments, this embodiment further provides a computer-readable storage medium, such as a floppy disk, an optical disk, a hard disk, a flash memory, a USB flash drive, an SD (Secure Digital Memory Card), or an MMC (Multimedia Card). The computer-readable storage medium stores one or more instructions for implementing the aforementioned steps. When these one or more instructions are executed by one or more processors, the processors execute the static timing analysis method described above. For the specific implementation, please refer to the aforementioned description and will not be elaborated on here.

[0120] In addition to the above-mentioned methods and devices, an embodiment of the present application may also be a computer program product, which includes computer program instructions. When the computer program instructions are executed by a processor, the processor executes the steps of the static timing analysis method according to various embodiments of the present application described in the above content of this specification.

[0121] The computer program product may be written in any combination of one or more programming languages to implement the program code for performing the operations of the embodiments of the present application, including object-oriented programming languages such as Java, C++, and conventional procedural programming languages such as "C" or similar programming languages. The program code may be executed entirely on the user's computing device, partially on the user's computing device, as a standalone software package, partially on the user's computing device and partially on a remote computing device, or entirely on a remote computing device or server.

[0122] Those skilled in the art will appreciate that the contents disclosed in this disclosure may be subject to various modifications and improvements. For example, the various devices or components described above may be implemented through hardware, software, firmware, or a combination of some or all of the three.

[0123] In addition, although the present disclosure makes various references to certain units in the system according to embodiments of the present disclosure, any number of different units can be used and run on the client and / or server. The units are only illustrative, and different aspects of the system and method can use different units.

[0124] Flowcharts are used in this disclosure to illustrate the steps of the methods according to the embodiments of the present disclosure. It should be understood that the preceding or following steps do not necessarily need to be performed in exact order. Instead, the various steps may be performed in reverse order or simultaneously. Furthermore, other operations may be added to these processes.

[0125] Those skilled in the art will appreciate that all or part of the steps in the above method can be performed by instructing the relevant hardware using a computer program, and the program can be stored in a computer-readable storage medium, such as a read-only memory. Alternatively, all or part of the steps in the above embodiment can also be implemented using one or more integrated circuits. Accordingly, each module / unit in the above embodiment can be implemented in the form of hardware or in the form of software functional modules. The present disclosure is not limited to any particular combination of hardware and software.

[0126] Unless otherwise defined, all terms used herein have the same meaning as commonly understood by those skilled in the art to which the present disclosure belongs. It should also be understood that terms such as those defined in common dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and should not be interpreted in an idealized or highly formal sense unless expressly defined as such herein.

[0127] The above is an illustration of the present disclosure and should not be considered as a limitation thereof. Although several exemplary embodiments of the present disclosure have been described, it will be readily understood by those skilled in the art that many modifications may be made to the exemplary embodiments without departing from the novel teachings and advantages of the present disclosure. Therefore, all such modifications are intended to be included within the scope of the present disclosure as defined by the claims. It should be understood that the above is an illustration of the present disclosure and should not be considered as limited to the specific embodiments disclosed, and modifications to the disclosed embodiments and other embodiments are intended to be included within the scope of the appended claims. The present disclosure is defined by the claims and their equivalents.

Claims

1. A static timing analysis method, characterized in that: include: Obtaining an average voltage drop value corresponding to each polarity reversal event of each logic unit in the integrated circuit within a target time interval, wherein the target time interval includes multiple clock cycles; Determine an actual voltage value of each logic unit in each clock cycle, where the actual voltage is the difference between the nominal voltage corresponding to the logic unit and the corresponding average voltage drop value; determining an actual cell delay corresponding to an actual voltage value of each logic cell; The setup time margin and the hold time margin of the corresponding timing path are determined according to the actual unit delay of each logic unit.

2. The method according to claim 1, characterized in that The obtaining of an average voltage drop value corresponding to each polarity reversal event of each logic unit in the integrated circuit within a target time interval includes: Obtaining a waveform file, wherein the waveform file records a waveform output by the integrated circuit in response to a test stimulus within a preset time length; Dividing the preset duration into a plurality of time intervals, and respectively calculating the power consumption of the integrated circuit in each of the time intervals according to the waveform file; Determine the time interval with the largest power consumption among the time intervals as the target time interval; An average voltage drop value corresponding to each polarity reversal event within the target time interval is determined for each logic unit of the integrated circuit.

3. The method according to claim 1, characterized in that Determining the actual voltage value of each logic unit in each clock cycle includes: Analyze the output polarity of each logic unit in each timing path of the integrated circuit step by step; Determining the polarity reversal event corresponding to each logic unit and the average voltage drop value corresponding to the polarity reversal event according to the output polarity change; Based on the corresponding relationship between the polarity reversal event and the clock cycle, the actual voltage value of each logic unit in each clock cycle is determined.

4. The method according to claim 3, characterized in that The logic unit includes a clock unit, a timing unit and a data unit; Determining the actual voltage value of each logic unit in each clock cycle includes: Determine an actual voltage value of each clock unit, sequential unit, and data unit in a first clock cycle, and an actual voltage value of each clock unit and sequential unit in a second clock cycle; The first clock cycle is any clock cycle in the target time interval, and the second clock cycle is a clock cycle next to the first clock cycle.

5. The method according to claim 4, characterized in that The timing path of the integrated circuit includes a transmission path, a data path and a capture path; The determining of the actual voltage value of each clock unit, sequential unit, and data unit in the first clock cycle, and the actual voltage value of each clock unit and sequential unit in the second clock cycle, includes: Determine an actual voltage value of each clock unit in the transmit path and the capture path and each timing unit and data unit in the data path in a first clock cycle; And, determining the actual voltage value of each clock unit and timing unit in the capture path in the second clock cycle.

6. The method according to claim 4, characterized in that The timing path of the integrated circuit includes a clock path and a data path; The step-by-step analysis of the output polarity of each logic unit of each timing path in the integrated circuit includes: Starting from the clock origin of the clock path, analyze the output polarity of each clock unit in the clock path step by step; Starting from the output end of the sequential unit of the data path, the output polarity of each sequential unit and data unit in the data path is analyzed step by step.

7. The method according to claim 1, characterized in that The process of determining the actual unit delay corresponding to the actual voltage value of any logic unit includes: Acquire a preset mapping relationship, where the preset mapping relationship includes a correspondence between a voltage value of a logic unit and a unit delay; According to the preset mapping relationship, an actual unit delay corresponding to the actual voltage value of the logic unit is determined.

8. The method according to claim 1, characterized in that The process of determining the actual unit delay corresponding to the actual voltage value of any logic unit includes: Obtaining a standard cell timing library file, wherein the standard cell timing library file records cell delays of different logic cells at different nominal voltages; Extracting the target nominal voltage of the logic unit and the target cell delay corresponding to the target nominal voltage recorded in the standard cell timing library file; An interpolation calculation is performed based on the target nominal voltage, the target unit delay, and the actual voltage value of the logic unit to obtain the actual unit delay of the logic unit.

9. The method according to claim 4, characterized in that The step of determining the setup time margin and the hold time margin of the corresponding timing path according to the actual unit delay of each logic unit includes: Determine setup time margins of timing paths to which the clock unit, the sequential unit, and the data unit belong based on actual unit delays of the clock unit, the sequential unit, and the data unit in the first clock cycle and actual unit delays of the clock unit and the sequential unit in the second clock cycle; According to actual unit delays of the clock unit, the timing unit, and the data unit in the first clock cycle, hold time margins of timing paths to which the clock unit, the timing unit, and the data unit belong are determined.

10. The method according to any one of claims 1 to 9, characterized in that The method further includes performing timing repair on a timing path having a setup time violation and / or a hold time violation in the integrated circuit.

11. A static timing analysis device, characterized in that: include: an acquisition unit, configured to acquire an average voltage drop value corresponding to each polarity reversal event of each logic unit in the integrated circuit within a target time interval, wherein the target time interval includes a plurality of clock cycles; A first determining unit is configured to determine an actual voltage value of each logic unit in each clock cycle, where the actual voltage is the difference between a nominal voltage corresponding to the logic unit and a corresponding average voltage drop value; a second determining unit, configured to determine an actual unit delay corresponding to an actual voltage value of each logic unit; The analysis unit is used to determine the setup time margin and the hold time margin of the corresponding timing path according to the actual unit delay of each logic unit.

12. A server comprising a memory, a processor, and a computer program stored in the memory and executed by the processor, wherein: When the processor executes the computer program, the steps of the static timing analysis method according to any one of claims 1 to 10 are implemented.

13. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the static timing analysis method according to any one of claims 1 to 10 are implemented.

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