Analysis method and analysis device
By performing static timing analysis of the circuit model, selecting signal paths that violate timing limitations and calculating timing reference values, the problem of circuit analysis time in complex circuit structures is solved, and efficient analysis of circuit design is achieved.
Patent Information
- Application Number
- CN202410183147.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-02-19
- Publication Date
- 2025-08-19
AI Technical Summary
Complex circuit structures lead to an increase in the number of operating conditions that need to be considered during circuit analysis, which increases the burden of design or analysis.
By performing static timing analysis of the circuit model to be tested, selecting selected signal paths that violate the timing limitations, obtaining timing information under each operating condition, and calculating timing reference values to simplify the analysis process.
By calculating the timing reference value, the analysis time of the overall circuit model is simplified and the efficiency of circuit design is improved.
Smart Images
Figure CN120509366A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to a method and a device, and in particular to an analysis method and an analysis device. Background Art
[0002] With the development of 2.5D and 3D chips, increasingly complex circuit structures are placing a significant burden on circuit analysis, both in terms of computational performance and time. Generally speaking, circuit simulation or analysis often requires adjusting process, voltage, and temperature variations to simulate or analyze the designed circuit under varying operating conditions. However, the complexity of circuit structures significantly increases the number of operating conditions that must be considered during the analysis process, thus increasing the burden on existing circuit design or analysis processes. Summary of the Invention
[0003] The present invention provides an analysis method and an analysis device, which can reduce the analysis time of a circuit model to be tested.
[0004] The analysis method of the present invention includes: performing static timing analysis on a circuit model to be tested to select selected signal paths that violate timing constraints from the circuit model to be tested; obtaining timing information of each selected signal path under respective operating conditions; and selecting selected timing information from the timing information based on a first threshold, and calculating a timing reference value corresponding to each operating condition based on the selected timing information.
[0005] An analysis device according to the present invention includes a memory and a processor. The memory is configured to store a circuit model under test. The processor is configured to: perform static timing analysis on the circuit model under test to select selected signal paths in the circuit model under test that violate timing constraints; obtain timing information for each selected signal path under respective operating conditions; and select selected timing information from the timing information based on a first threshold, and calculate timing reference values corresponding to respective operating conditions based on the selected timing information.
[0006] Based on the above, the analysis device and analysis method of the present invention can effectively calculate the timing reference value, thereby simplifying the analysis time of the entire circuit model. BRIEF DESCRIPTION OF THE DRAWINGS
[0007] The accompanying drawings are included to provide a further understanding of the present invention and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the present invention and together with the description serve to explain the principles of the present invention.
[0008] Figure 1 is a block diagram of an analysis device according to an embodiment of the present invention;
[0009] Figure 2 This is a flow chart of an analysis method according to an embodiment of the present invention;
[0010] Figures 3A to 3F This is an operational flow chart of an analysis method according to an embodiment of the present invention. DETAILED DESCRIPTION
[0011] In a typical digital circuit design process, designers first design the circuit using a circuit description language (e.g., VHDL or Verilog) and implement it using register-transfer level (RTL) code. Designers then perform logic synthesis on the RTL code, converting it into a gate-level circuit. Finally, the logic gate circuit is run through automatic place and route (APR) to generate a layout corresponding to the physical circuit. After completing these steps, static timing analysis (STA) is performed on the logic gate circuit, incorporating manufacturing process parameters related to the physical structure based on the routing relationships depicted on the layout. This analysis determines whether the APR-generated physical circuit's timing performance meets design requirements. If STA results indicate that the APR-generated circuit does not fully meet design requirements, designers can modify the original circuit using engineering change orders (ECOs), for example by adjusting the thrust of some driver circuits without changing the circuit's functionality. Furthermore, to ensure that the final circuit layout meets the design requirements, APR, STA, and possibly ECO are performed. The loop formed by these steps can be repeatedly used to analyze and correct the input circuit until the final circuit layout meets the design requirements.
[0012] Figure 1 FIG. 1 is a block diagram of an analysis device 1 according to an embodiment of the present invention. Figure 1The analysis device 1 includes a processor 10 and a memory 11. The analysis device 1 may store a designed circuit model 110 under test in the memory 11. The processor 10 is coupled to the memory 110 and can access the memory 111 to perform circuit design processes such as STA and ECO on the circuit model 110 under test. In this embodiment, the circuit model 110 under test stored in the memory 11 may be, for example, a circuit layout generated after APR. The processor 10 sets multiple operating conditions on the circuit model 110 under test and performs STA. This determines selected signal paths in the circuit model 110 that violate timing constraints and calculates the worst-case percentage of these selected signal paths under each operating condition. Finally, the processor 10 selects at least one selected operating condition based on the calculated worst-case percentage corresponding to each operating condition. This allows the processor 10 to select at least one selected operating condition based on the calculated worst-case percentage corresponding to each operating condition. Consequently, when the circuit model 110 under test is subsequently corrected, such as through ECO, and then undergoes STA, the processor 10 can perform STA only on the corrected circuit model under the selected operating conditions, thereby accelerating the overall chip design time.
[0013] In some embodiments, the processor 10 may be, for example, a central processing unit (CPU), or other programmable general-purpose or special-purpose microcontroller unit (MCU), microprocessor, digital signal processor (DSP), programmable controller, application-specific integrated circuit (ASIC), graphics processing unit (GPU), arithmetic logic unit (ALU), complex programmable logic device (CPLD), field programmable gate array (FPGA), any other type of integrated circuit, state machine, Advanced RISC Machine (ARM)-based processor, or other similar components or combinations thereof. Alternatively, the processor 10 may be a hardware circuit designed and implemented using a hardware description language (HDL) or any other digital circuit design method known to those skilled in the art. In some embodiments, the memory 11 may be, for example, any type of fixed or removable random access memory (RAM), read-only memory (ROM), flash memory, hard disk drive (HDD), solid state drive (SSD), or similar device or a combination of the above devices, for storing the circuit model 110 to be tested, or other necessary program codes for execution by the processor 10.
[0014] Figure 2 Flowchart of an analysis method according to embodiment 1 of the present invention. Figure 2 The analytical method shown can be Figure 1 Executed by the analysis device 1. Figure 2 The analysis method includes steps S20 to S22.
[0015] In step S20, the processor 10 may perform static timing analysis on the circuit model 110 to select selected signal paths that violate timing constraints from the signal paths included in the circuit model 110. Specifically, when performing static timing analysis, the processor 10 may set the circuit model 110 to be tested under different operating conditions and obtain the delays of all signal paths in the circuit by performing static timing analysis. In order to perform extensive testing and analysis on the circuit model 110 to be tested, the processor 10 may set the circuit model 110 to be tested under a variety of operating conditions by adjusting parameters such as process, voltage, and temperature (PVT). Therefore, the processor 10 can obtain delay information for all signal paths in the circuit model 110 to be tested. For each operating condition, the processor 10 may compare the delays of all signal paths under that operating condition with preset timing constraints, thereby identifying the signal paths to be recorded that violate the timing constraints under that operating condition. Finally, after the processor 10 completes the analysis of all operating conditions, the processor 10 may merge the signal paths to be recorded under all operating conditions into a selected signal path.
[0016] In step S21, the processor 10 obtains the timing information of each selected signal path under each operating condition. Specifically, for each selected signal path, the processor 10 can calculate the delay of the selected signal path under all operating conditions, and calculate the timing margin (slack) value of the selected signal path compared to the timing constraint under each operating condition based on these delays, and store it as the timing information. Generally speaking, the timing margin value can be interpreted as the margin of the signal path compared to the timing constraint, and the processor 10 can obtain the timing margin value by deducting the timing constraint from the delay of the signal path. A negative timing margin value indicates that the signal path does not meet the timing constraint, and the smaller the timing margin value, the more the signal path lags behind the timing constraint.
[0017] In step S22, the processor 10 may select selected timing information from the timing information based on the first threshold, and calculate the timing reference value corresponding to each operating condition based on the selected timing information. Specifically, for each selected signal path, the processor 10 may select one or more timing information from the timing information corresponding to all operating conditions of the selected signal path based on the first threshold as the selected timing information. Finally, for each operating condition, the processor 10 may calculate the statistics of the selected timing information under the operating condition, and calculate the proportion of the statistics in all the timing information, and use it as the timing reference value of the operating condition.
[0018] In some embodiments, the first threshold may be, for example, a preset range or a preset number. That is, for each selected signal path, the processor 10 may select a preset number of selected timing information, or selected timing information that meets the preset range. For example, in the case where the timing margin value is used as the timing information, for each selected signal path, the processor 10 may select the minimum margin value and the operating condition corresponding to it from the timing margin values of the selected signal path under all operating conditions, and use the minimum margin value as the selected timing information. After determining the selected timing information of all selected signal paths, for each operating condition, the processor 10 may calculate the statistical value of the minimum margin value corresponding to each operating condition in the proportion of all minimum margin values as the timing reference value corresponding to each operating condition.
[0019] In some embodiments, the processor 10 calculates the timing reference value corresponding to each operating condition by dividing the number of minimum margin values corresponding to the operating condition by the total number of all minimum margin values, and uses the ratio of the two as the timing reference value corresponding to each operating condition.
[0020] In some embodiments, the processor 10 calculates the timing reference value corresponding to each operating condition by dividing the sum of the minimum margin values corresponding to each operating condition by the ratio of all the minimum margin values, and uses the ratio of the two as the timing reference value corresponding to each operating condition.
[0021] In a certain aspect, the processor 10 can determine under which operating conditions the timing performance of each selected signal path is relatively poor by judging the selected timing information and the corresponding operating conditions. Further, the processor 10 can count the proportion of the selected timing information corresponding to each operating condition in the total selected timing information, and use it as a timing reference value, thereby judging the probability or proportion of relatively poor timing performance under the operating condition, and thus select the operating condition with poor timing performance as the selected operating condition based on the first threshold. In this way, after completing ECO and APR, the processor 10 only needs to set the corrected circuit model to be tested 110 to the selected operating condition with poor timing performance to perform static timing analysis. The processor 10 only needs to observe whether the timing information of the selected signal path in the corrected circuit model to be tested 110 meets the timing constraints under the selected operating conditions. When the processor 10 determines that the timing information of the selected signal path of the modified circuit model 110 under the selected operating conditions meets the timing constraints, the processor 10 can then perform a complete static timing analysis on the modified circuit model 110, that is, a static timing analysis including all operating conditions.
[0022] Figures 3A to 3F This is an operational flow chart of an analysis method according to an embodiment of the present invention. Figures 3A to 3E The analysis method can be, for example, by Figure 1 The analysis device is performed. Figure 3A In the embodiment, the processor 10 may perform static timing analysis on the circuit model under test 310 to obtain timing information of multiple signal paths in the circuit model under test 310 under multiple operating conditions.
[0023] exist Figure 3B In this example, the processor 10 may perform static timing analysis on the circuit model under test 310 under operating conditions C1 to C3, and select signal paths to be recorded that violate timing constraints in the circuit model under test 310. Specifically, the processor 10 may determine that under operating condition C1, signal paths P1, P5, P6, and P9 in the circuit model under test 310 violate timing constraints; under operating condition C2, signal paths P2, P5, P6, and P7 in the circuit model under test 310 violate timing constraints; and under operating condition C3, signal paths P1, P2, P5, and P7 in the circuit model under test 310 violate timing constraints.
[0024] exist Figure 3C In this example, the processor 10 may combine all signal paths to be recorded that violate the timing constraints under various operating conditions into selected signal paths. In this example, the processor 10 may combine all signal paths to be recorded and select selected signal paths P1, P2, P5, P6, P7, and P9.
[0025] exist Figure 3D In the embodiment, the processor 10 can determine the selected timing information and the operating conditions corresponding to the selected timing information from the timing information. In detail, for each selected path, the processor 10 can select the selected timing information from the timing information of the selected path under each operating condition. For example, in an embodiment where the timing information is a timing margin value, for each selected path, the processor 10 can compare the timing margin value of the selected signal path under operating conditions C1 to C3, and select the minimum timing margin value as the selected timing information. Then, the processor 10 can further count the minimum timing margin value corresponding to each operating condition, thereby calculating the timing reference value corresponding to the operating condition.
[0026] Therefore, in Figure 3D In the embodiment, the processor 10 may determine that the selected timing information of the selected signal paths P1, P2, P5, and P9 corresponds to the operating condition C1, and the selected timing information of the selected signal paths P6 and P7 corresponds to the operating condition C2.
[0027] Figure 3E The judgment process of selecting the timing information is shown. Figure 3ETable T1 in Figure 1 shows the ranking of the timing margin values for selected signal paths P1, P2, P5, P6, P7, and P9 under operating conditions C1 to C3. As shown in the first column of Table T1, signal path P1 has the smallest timing margin value under operating condition C1 and the largest timing margin value under operating condition C2. Therefore, the timing margin value for signal path P1 under operating condition C1 is determined to be the selected timing information. The timing information corresponding to selected signal paths P2, P5, P6, P7, and P9 can be deduced similarly and will not be further detailed here.
[0028] In some embodiments, for each operating condition, the processor 10 calculates the ratio of the number of minimum margin values corresponding to each operating condition divided by the total number of all minimum margin values, and uses the ratio as the timing reference value for each of the timing reference values. For example, taking operating condition C1 as an example, the selected timing information of a total of four selected signal paths P1, P2, P5, and P9 will correspond to operating condition C1. Therefore, the processor 10 can divide the number of selected timing information corresponding to operating condition C1 by the total number of selected timing information, that is, four divided by six, to calculate the proportion of the selected timing information corresponding to operating condition C1 in all selected timing information, and use the proportion as the timing reference value for operating condition C1. Similarly, for operating condition C2, the processor 10 can divide the number of selected timing information of selected paths P6 and P7 corresponding to operating condition C2 by the total number of selected timing information, that is, two divided by six, to calculate the proportion of the selected timing information corresponding to operating condition C2 in all selected timing information.
[0029] In some embodiments, for each operating condition, the processor 10 may calculate the ratio of the sum of the minimum margin values corresponding to each operating condition divided by the sum of all minimum margin values, and use this ratio as the timing reference value for each operating condition. For example, taking operating condition C1 as an example, the processor 10 may sum the minimum margin values of the selected signal paths P1, P2, P5, and P9 with the minimum margin values under operating condition C1, and then divide this sum by the sum of the minimum margin values of all selected signal paths P1, P2, P5, P6, P7, and P9. This calculates the ratio of the minimum margin value corresponding to operating condition C1 to the total minimum margin values. Finally, the processor 10 may use this ratio as the timing reference value for operating condition C1. Similarly, for operating condition C2, the processor 10 can sum up the minimum margin values of the selected signal paths P6 and P7 with the minimum margin values under operating condition C2 and divide the sum by the sum of the minimum margin values of all selected signal paths P1, P2, P5, P6, P7, and P9, and use the resulting ratio as the timing reference value for operating condition C2.
[0030] Figure 3FThe process of determining the selected operating condition is shown. After the processor 10 determines and calculates the timing reference value, the processor 10 can determine the selected operating condition based on the timing reference value. Figure 3F Table T2 in shows the timing reference values of the operating conditions C1 to C3. In detail, the processor 10 can sort all the operating conditions from large to small according to the timing reference value, and select which operating conditions as the selected operating conditions according to the second threshold. In this embodiment, the timing reference value can be, for example, the proportion of the minimum margin value corresponding to the operating condition. In this way, when the processor 10 can select the selected operating condition according to the sorted timing reference value from large to small, until the sum of the timing reference values of the selected operating conditions is greater than the second threshold. Figure 3F In the example, the second threshold can be, for example, 95%. In this way, processor 10 can select operating conditions C1 and C2 as selected operating conditions, so that the sum of the timing reference values for the selected operating conditions is greater than the threshold. Furthermore, in the subsequent analysis method, after processor 10 performs ECO and APR on circuit model 310 under test, it is only necessary to perform static timing analysis on the modified circuit model 310 under the selected operating conditions, significantly reducing the overall timing analysis time.
[0031] In summary, the analysis device and analysis method of the present invention can effectively calculate the timing reference value, thereby simplifying the analysis time of the entire circuit model.
Claims
1. An analysis method comprising: performing static timing analysis on the circuit model to be tested to select a plurality of selected signal paths that violate timing constraints from the circuit model to be tested; obtaining a plurality of timing information of each of the selected signal paths under a plurality of operating conditions; as well as A plurality of selected timing information is selected from the plurality of timing information according to a first threshold, and a timing reference value corresponding to each of the operating conditions is calculated according to the plurality of selected timing information.
2. The analysis method according to claim 1, comprising: Setting the circuit model to be tested under each of the operating conditions to perform the static timing analysis; selecting, based on the first threshold, from the circuit model to be tested, a signal path to be recorded that violates the timing constraint under each of the operating conditions; as well as The signal paths to be recorded under the various operating conditions are merged into the multiple selected signal paths.
3. The analysis method according to claim 1, comprising: For each of the selected signal paths, determining a plurality of timing margin values that violate the timing constraint under the plurality of operating conditions, as the plurality of timing information; as well as For each of the selected signal paths, a minimum margin value is selected from the corresponding plurality of timing margin values to serve as the selected timing information.
4. The analysis method according to claim 3, comprising: For each of the operating conditions, a ratio of the plurality of minimum margin values corresponding to each of the operating conditions to all of the plurality of minimum margin values is calculated to serve as each of the timing reference values.
5. The analysis method according to claim 4, wherein calculating each of the timing reference values comprises: For each of the operating conditions, a ratio of the number of the minimum margin values corresponding to each of the operating conditions divided by the total number of all the minimum margin values is calculated, and the ratio is used as each of the timing reference values.
6. The analysis method according to claim 4, wherein calculating each of the timing reference values comprises: For each of the operating conditions, a ratio of a sum of the plurality of minimum margin values corresponding to each of the operating conditions divided by a total of all of the plurality of minimum margin values is calculated and used as each of the timing reference values.
7. The analysis method according to claim 1, comprising: At least one selected operating condition is selected from the plurality of operating conditions according to the plurality of timing reference values, wherein a sum of the at least one timing reference value corresponding to the at least one selected operating condition is greater than or equal to a second threshold.
8. The analysis method according to claim 7, comprising: The plurality of selected signal paths in the circuit model under test are modified, and the modified circuit model under test is set to perform the static timing analysis under the at least one selected operating condition.
9. An analysis device comprising: A memory for storing a circuit model to be tested; and Processor, to execute: Performing static timing analysis on the circuit model to be tested to select a plurality of selected signal paths that violate timing constraints from the circuit model to be tested; obtaining a plurality of timing information of each of the selected signal paths under a plurality of operating conditions; as well as A plurality of selected timing information is selected from the plurality of timing information according to a first threshold, and a timing reference value corresponding to each of the operating conditions is calculated according to the plurality of selected timing information.
10. The analysis device according to claim 9, wherein the processor is configured to execute: Setting the circuit model to be tested under each of the operating conditions to perform the static timing analysis; selecting, based on the first threshold, from the circuit model to be tested, a signal path to be recorded that violates the timing constraint under each of the operating conditions; as well as The signal paths to be recorded under the various operating conditions are merged into the multiple selected signal paths.
11. The analysis device according to claim 9, wherein the processor is configured to execute: For each of the selected signal paths, determining a plurality of timing margin values that violate the timing constraint under the plurality of operating conditions, respectively, to serve as the plurality of timing information; and For each of the selected signal paths, a minimum margin value is selected from the corresponding plurality of timing margin values as the selected timing information.
12. The analysis device according to claim 11, wherein the processor is configured to execute: For each of the operating conditions, a ratio of the plurality of minimum margin values corresponding to each of the operating conditions to all of the plurality of minimum margin values is calculated to serve as each of the timing reference values.
13. The analysis device according to claim 12, wherein the step of the processor calculating each of the timing reference values comprises: For each of the operating conditions, a ratio of the number of the minimum margin values corresponding to each of the operating conditions divided by the total number of all the minimum margin values is calculated, and the ratio is used as each of the timing reference values.
14. The analysis device according to claim 12, wherein the step of the processor calculating each of the timing reference values comprises: For each of the operating conditions, a ratio of a sum of the plurality of minimum margin values corresponding to each of the operating conditions divided by a total of all of the plurality of minimum margin values is calculated and used as each of the timing reference values.
15. The analysis device according to claim 9, wherein the processor is configured to execute: At least one selected operating condition is selected from the plurality of operating conditions according to the plurality of timing reference values, wherein a sum of the at least one timing reference value corresponding to the at least one selected operating condition is greater than or equal to a second threshold.
16. The analysis device according to claim 15, wherein the processor is configured to execute: The plurality of selected signal paths in the circuit model under test are modified, and the modified circuit model under test is set to perform the static timing analysis under the at least one selected operating condition.