FPGA (Field Programmable Gate Array)-based dedicated chip real-time evaluation method

Abstract

The invention relates to the technical field of real-time kernel performance testing of special chips, in particular to a special chip real-time performance evaluation method based on an FPGA (Field Programmable Gate Array), which comprises the following steps: (1) aiming at a real-time system on an ASIC (Application Specific Integrated Circuit) chip, setting an external interrupt source and an interrupt service program through a hardware interrupt controller; (2) two tasks with the same priority are created, scheduling of the tasks is achieved through time slice rotation, and a real dynamic load scene is simulated; (3) configuring an external FPGA (Field Programmable Gate Array) to generate a square wave signal to trigger external interruption of the ASIC chip, receiving a feedback signal, and connecting the FPGA and the GPIO through an external physical connecting line to form a hardware interruption triggering-response closed loop; and (4) realizing nanosecond timestamp capture through a counter built in the FPGA, acquiring time delay data, calculating interrupt response time, and transmitting the time delay data to a PC (Personal Computer) through a UART (Universal Asynchronous Receiver / Transmitter) to calculate a maximum value, a minimum value, an average value and a data jitter range of test data. The method can effectively solve the problem that the traditional internal closed-loop test cannot reflect the real interruption randomness and the dynamic load.

Description

Technical Field

[0001] The present invention relates to the technical field of real-time kernel performance testing of special chips, and in particular to a real-time performance evaluation method of special chips based on FPGA. Background Art

[0002] With the rapid development of integrated circuits and artificial intelligence technologies, robotics are evolving towards high performance, low power consumption, and strong real-time capabilities. The robot controller is the most critical component of a robot, significantly impacting its performance. Excellent real-time performance has always been a key requirement for robot controllers. This refers to the core's ability to respond to and process external events in a timely manner. Various real-time performance indicators, such as interrupt latency, interrupt response time, interrupt processing time, interrupt recovery time, and task response time, provide users with an objective basis for evaluating the quality of real-time cores.

[0003] Most real-time kernels use a preemptive scheduling strategy, such as Figure 1 As shown in the timing diagram of preemptive scheduling, interrupt latency, interrupt response time, interrupt processing time, interrupt recovery time, and task response time can be reflected. Several key indicators are introduced below.

[0004] Interrupt latency is the time from when an interrupt request is generated to when the CPU begins processing it. When an interrupt request is generated, the current instruction may not have completed execution or the interrupt enable may be disabled, temporarily preventing the CPU from processing the interrupt request. Interrupts are external asynchronous events, meaning they can occur at any time. Therefore, the state of the CPU's interrupt enable is uncertain when an interrupt request is generated.

[0005] Interrupt response time is the time from when an interrupt request is generated to when the CPU begins executing the interrupt service routine. After the CPU begins processing the interrupt request, it must go through two steps: saving the context and calling the interrupt service routine entry function before it can begin running the interrupt service routine. Therefore, the interrupt response time for preemptive scheduling is composed of three parts: interrupt latency, context saving time, and the time to call the interrupt service routine entry function.

[0006] Task response time is the time from when an interrupt request is generated to when the CPU starts executing the task. When an interrupt request is generated, the blocked task handling the interrupt request is awakened. If the priority of the blocked task is higher than the current task, the real-time kernel preemptively schedules the blocked task to enter the running state.

[0007] The current real-time kernel evaluation method (patented) utilizes an internal self-excited closed-loop test mechanism. This involves constructing a task loop within the real-time system to trigger GPIO pin level transitions, simulating an interrupt signal source. Another task then responds to and processes the interrupt, while a third task simultaneously collects and calculates latency data. This internal interrupt's fixed trigger frequency, priority, and concurrency pattern cannot simulate the randomness and dynamic load of real external events. Furthermore, the internal task loop and latency calculation introduce additional clock delays. Other evaluation methods, such as oscilloscope acquisition, suffer from significant errors due to the limited number of samples collected per acquisition, and large calculation errors. Alternatively, an external microcontroller triggers interrupts and collects data, but the time-consuming software instruction compilation and conversion introduces additional errors.

[0008] Therefore, a new technical solution is urgently needed to solve the above technical problems. Summary of the Invention

[0009] The purpose of the present invention is to overcome the above-mentioned problems of the prior art and provide a real-time evaluation method for a dedicated chip based on FPGA to solve the technical problem that traditional internal closed-loop testing cannot reflect the actual interrupt randomness and dynamic load.

[0010] The above objectives are achieved through the following technical solutions: A method for evaluating the real-time performance of a dedicated chip based on FPGA, comprising: Step (1) for the real-time system on the ASIC chip, an external interrupt source and an interrupt service routine are set through a hardware interrupt controller, a first LGPIO pin is configured as an input mode to detect an external interrupt trigger signal, and a second LGPIO pin is configured as an output mode in the interrupt service routine to drive a response signal; Step (2) creates two tasks of the same priority, performs complex calculations within the tasks, and uses time slice rotation to schedule the tasks, simulating a real dynamic load scenario; Step (3) configuring the external FPGA to generate a square wave signal to trigger the external interrupt of the ASIC chip, and receiving a feedback signal, connecting the GPIO output terminal of the FPGA to the first LGPIO pin through an external physical connection, and connecting the second LGPIO pin to the GPIO input terminal of the FPGA, thereby forming a hardware interrupt trigger-response closed loop; Step (4) uses the built-in counter of the FPGA to capture nanosecond timestamps, obtain delay data and calculate the interrupt response time, and transmit it to the PC host computer via UART. After executing a predetermined number of tests, the maximum value, minimum value, average value and data jitter range of the test data are calculated to reflect the real-time performance of the real-time kernel.

[0011] Furthermore, the hardware interrupt controller is an enhanced core local interrupt controller, which configures the interrupt triggering mode of the external interrupt source to be high-level triggering, with a priority of 1, and is bound to the interrupt service routine.

[0012] Furthermore, the dynamic load task is started by the FreeRTOS scheduler, and the execution of the two tasks with the same priority forces the idle task to enter a blocked state, simulating CPU resource preemption and context switching in a high-load scenario.

[0013] Furthermore, the real-time system uses FreeRTOS real-time system with version number V10.3.1.

[0014] Furthermore, the FPGA uses Xilinx's AXU3EGB development board to provide an interrupt trigger source.

[0015] Furthermore, the method for obtaining the interrupt response time includes: The GPIO output terminal of the FPGA is used to output an interrupt trigger signal, and the first LGPIO pin of the ASIC is used as an interrupt input signal, and the two are physically connected; the second LGPIO pin of the ASIC outputs a response signal, and the GPIO input terminal of the FPGA is used as a response input signal, and the two are physically connected; The FPGA uses a counter to generate a pulse signal by cyclically pulling up the GPIO, and at the same time marks the timestamp t1 at the rising edge of the level setting high; When the real-time kernel of the ASIC chip receives a rising edge level, it enters the interrupt response process; because the processing mode of the interrupt source is non-vector processing, the CPU will jump to the interrupt handler shared by all non-vector interrupts. After saving the registers mcause, mepc, and msubm and saving the general registers, it executes the instructions csrrwra, CSR_JALMNXTI, ra to jump to the interrupt service routine of the interrupt source and finally enter the interrupt service routine LGPIO0_IRQHandler; In the interrupt service program LGPIO0_IRQHandler, the response LGPIO level is pulled high, and then the GPIO input end of the FPGA receives the rising edge level of the response signal, at which time the timestamp t2 is marked; The interrupt response time is calculated by the formula delay=t2-t1.

[0016] Furthermore, the timestamp is obtained by using a general timer of the FPGA as a high-precision time source.

[0017] Furthermore, the FPGA collects interrupt response time cyclically for a total of 100,000 times, thereby reducing the error and randomness of the test results.

[0018] The present invention provides an FPGA-based real-time performance evaluation method for dedicated chips. This method achieves high-precision real-time performance measurement through an external interrupt trigger-response closed-loop design and dynamic load simulation. It uses time-slice round-robin scheduling to simulate CPU resource competition scenarios and employs the FPGA's built-in high-precision counter as a clock source to quantify the interrupt handling stability and determinism of the real-time core under dynamic load. This method addresses the problem that traditional internal closed-loop testing cannot reflect the actual interrupt randomness and dynamic load. Specifically, it includes: 1. The collaboration of the ECLIC interrupt controller's precise triggering, FreeRTOS's dynamic load simulation, and the FPGA hardware timing closed loop solves the problem of internal timer interrupt testing failing to reflect the random triggering of real interrupts.

[0019] 2. A high-precision clock system is used as the test clock source. The FPGA counter directly measures instead of reading the software timestamp, eliminating errors caused by system calls and cache accesses. 3. Collect more than 100,000 data points as data samples for real-time evaluation to ensure the accuracy of the test and the persuasiveness of the data. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 A preemptive scheduling timing diagram that marks real-time performance indicators in existing real-time kernels; Figure 2 This is a flow chart of a method for real-time performance evaluation of a dedicated chip based on FPGA according to the present invention; Figure 3 This is a schematic diagram of the system structure of a real-time evaluation method for a dedicated chip based on FPGA described in the present invention. DETAILED DESCRIPTION

[0021] The present invention will be further described in detail below with reference to the accompanying drawings and examples. The described embodiments are only some embodiments of the present invention, not all embodiments. All other embodiments derived by persons of ordinary skill in the art based on the embodiments of the present invention without inventive effort shall fall within the scope of protection of the present invention.

[0022] like Figure 2 As shown in the figure, this solution provides an FPGA-based real-time performance evaluation method for dedicated chips. It uses interrupt response time, a real-time performance metric, as an objective basis for evaluating the real-time performance of the kernel. The goal is to establish an evaluation method that accurately quantifies the performance of the real-time kernel. This method is suitable for verifying the interrupt performance of embedded real-time operating systems (RTOS), especially for scenarios requiring highly deterministic responses, such as industrial robots and autonomous driving. This includes: Step (1) for a real-time system on an ASIC chip, an external interrupt source and an interrupt service routine are set through a hardware interrupt controller, a first LGPIO pin is configured as an input mode to detect an external interrupt trigger signal, and a second LGPIO pin is configured as an output mode in the interrupt service routine to drive a response signal; wherein the hardware interrupt controller is an enhanced core local interrupt controller (ECLIC), the interrupt trigger mode of the external interrupt source is configured as a high-level trigger, the priority is 1, and the interrupt is bound to the interrupt service routine; Step (2) creates two tasks of the same priority, performs complex calculations within the tasks, and uses time slice rotation to implement task scheduling, simulating a real dynamic load scenario; wherein the dynamic load task is started by the FreeRTOS scheduler, and the execution of the two tasks of the same priority forces the idle task to enter a blocked state, simulating CPU resource preemption and context switching under a high load scenario; Step (3) configuring the external FPGA to generate a square wave signal to trigger the external interrupt of the ASIC chip, and receiving a feedback signal, connecting the GPIO output terminal of the FPGA to the first LGPIO pin through an external physical connection, and connecting the second LGPIO pin to the GPIO input terminal of the FPGA, thereby forming a hardware interrupt trigger-response closed loop; Step (4) uses the built-in counter of the FPGA to capture nanosecond timestamps, obtain delay data and calculate the interrupt response time, and transmit it to the PC host computer via UART. After executing a predetermined number of tests, the maximum value, minimum value, average value and data jitter range of the test data are calculated to reflect the real-time performance of the real-time kernel.

[0023] The method for obtaining the interrupt response time in this embodiment includes: The GPIO output terminal of the FPGA is used to output an interrupt trigger signal, and the first LGPIO pin of the ASIC is used as an interrupt input signal, and the two are physically connected; the second LGPIO pin of the ASIC outputs a response signal, and the GPIO input terminal of the FPGA is used as a response input signal, and the two are physically connected; The FPGA uses a counter to generate a pulse signal by cyclically pulling up the GPIO, and at the same time marks the timestamp t1 at the rising edge of the level setting high; When the real-time kernel of the ASIC chip receives a rising edge level, it enters the interrupt response process; because the processing mode of the interrupt source is non-vector processing, the CPU will jump to the interrupt handler shared by all non-vector interrupts. After saving the registers mcause, mepc, and msubm and saving the general registers, it executes the instructions csrrwra, CSR_JALMNXTI, ra to jump to the interrupt service routine of the interrupt source and finally enter the interrupt service routine LGPIO0_IRQHandler; In the interrupt service program LGPIO0_IRQHandler, the response LGPIO level is pulled high, and then the GPIO input end of the FPGA receives the rising edge level of the response signal, at which time the timestamp t2 is marked; The interrupt response time is calculated by the formula delay=t2-t1.

[0024] The timestamp is obtained by using the FPGA's universal timer as a high-precision time source. The FPGA collects interrupt response times 100,000 times in a cycle, reducing the error and randomness of the test results.

[0025] This method addresses the rigidity of trigger modes in traditional internal self-oscillating closed-loop testing by coordinating FPGA hardware triggering with ASIC dynamic task scheduling. It uses dual floating-point tasks of equal priority (using FreeRTOS round-robin scheduling) to simulate real-world CPU resource contention. Combined with FPGA random square wave triggering, it models dynamic load randomness. FPGA counters are used to directly sample trigger-response signals (using the 200MHz PL clock of the AXU3EGB development board), achieving 5ns accuracy. Physically isolated GPIO links eliminate parasitic delays introduced by internal task loops and software instruction compilation. This method, validated through 100,000 test cycles, calculates average interrupt response times within 1% of oscilloscope observations, significantly improving accuracy compared to the μs-level errors associated with microcontroller triggering. It also addresses the limitations of oscilloscope automation and multiple acquisitions. Hardware triggering isolates software interference, nanosecond-level timing closed-loops, and dynamic load contention scheduling, providing a highly accurate, reliable, and industrial-grade solution for real-time kernel performance evaluation.

[0026] like Figure 3 As shown, this solution also provides a system for implementing the above method, using the UX900 based on the RISC-V architecture as the hardware platform, and the real-time system using the FreeRTOS real-time system, version: V10.3.1; FPGA uses Xilinx's AXU3EGB development board to provide interrupt trigger source. In this embodiment, the timestamp used to calculate the interrupt response time is provided by the 200MHz system clock of AXU3EGB with high precision time source; the interrupt control module and dynamic load task scheduling module used are both based on the FreeRTOS system.

[0027] 1. Interrupt control module construction This embodiment uses the ASIC hardware platform's LGPIO0 pin to detect interrupt trigger signals, while LGPIO1 drives the response feedback signal. LGPIO can detect four types of external interrupt signals from the PAD: rising edge, falling edge, high level, and low level, but only generates high-level interrupts to the CPU. Use the LGPIO_Mode function to configure LGPIO0 to high-impedance (HIGHZ) input mode to detect external signals, and LGPIO1 to push-pull (PP) output mode to drive the response signal.

[0028] ECLIC (Enhanced Core Local Interrupt Controller) is an interrupt controller optimized by Corelink Technology based on CLIC (Core Local Interrupt Controller) in the RISC-V instruction set architecture. In FreeRTOS, register an external interrupt source using the ECLIC_Register_IRQ function. Set the interrupt number to 26, corresponding to LGPIO, the trigger mode to high-level trigger, the interrupt level to 1, and the priority to 1. Bind the interrupt service routine to LGPIO0_IRQHandler.

[0029] The hardware interrupt controller (ECLIC) collaborates with LGPIO to ensure electrical isolation and precise timing control between the interrupt trigger signal and the response signal, thus avoiding measurement errors caused by signal crosstalk.

[0030] 2. Dynamic load task scheduling module Two tasks (Task A and Task B) of the same priority (Priority 1) were created, both performing floating-point-intensive operations. The FreeRTOS scheduler, vTaskStartScheduler, was used to start the priority 0 idle task. Because Tasks A and B have higher priorities than the idle task, Tasks A and B took turns running according to their time slices, forcing the idle task into a blocked state. This simulated CPU resource contention under high load in real-time systems and verified the stability of interrupt response during task preemption and context switching.

[0031] 3. FPGA hardware collaboration module The FPGA uses a general-purpose timer to generate a 10Hz square wave signal, outputting it through GPIO_out. Another GPIO_in pin is configured as the input detection feedback signal. External physical wires connect the FPGA's GPIO_out to LGPIO0 (the interrupt trigger terminal), and LGPIO1 to the FPGA's GPIO_in (the response feedback terminal). This creates a hardware-level interrupt trigger-response closed loop, enabling nanosecond timestamp capture through the FPGA counter, eliminating parasitic delays introduced by software timing.

[0032] 4. Interrupt response time measurement logic This embodiment uses the differential 200MHz PL system clock source provided by the FPGA to capture timestamps, marking the timestamp t1 on the rising edge of the GPIO_out level. In the interrupt service routine LGPIO0_IRQHandler, the LGPIO1 level is pulled high using the LGPIO_WriteBit function, and the FPGA detects the GPIO_in level jump, recording the counter value t2 at this time. The counter difference value, that is, the difference between t2 and t1, is output through the UART serial port. After a predetermined number of tests, the data is processed to calculate the maximum and average interrupt response time and the time jitter range. The hardware counter is used to directly quantify the full-link delay of "interrupt trigger → ISR execution → signal feedback", and combined with statistical analysis to evaluate the fluctuation range of the system's real-time performance.

[0033] The above description is only for explaining the embodiments of the present invention and is not intended to limit the present invention. For those skilled in the art, any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

Claims

1. A method for real-time evaluation of a dedicated chip based on FPGA, characterized in that: include: Step (1) for the real-time system on the ASIC chip, an external interrupt source and an interrupt service routine are set through a hardware interrupt controller, a first LGPIO pin is configured as an input mode to detect an external interrupt trigger signal, and a second LGPIO pin is configured as an output mode in the interrupt service routine to drive a response signal; Step (2) creates two tasks of the same priority, performs complex calculations within the tasks, and uses time slice rotation to schedule the tasks, simulating a real dynamic load scenario; Step (3) configuring the external FPGA to generate a square wave signal to trigger the external interrupt of the ASIC chip, and receiving a feedback signal, connecting the GPIO output terminal of the FPGA to the first LGPIO pin through an external physical connection, and connecting the second LGPIO pin to the GPIO input terminal of the FPGA, thereby forming a hardware interrupt trigger-response closed loop; Step (4) uses the built-in counter of the FPGA to capture nanosecond timestamps, obtain delay data and calculate the interrupt response time, and transmit it to the PC host computer via UART. After executing a predetermined number of tests, the maximum value, minimum value, average value and data jitter range of the test data are calculated to reflect the real-time performance of the real-time kernel.

2. The method for real-time performance evaluation of a dedicated chip based on FPGA according to claim 1, characterized in that: The hardware interrupt controller is an enhanced core local interrupt controller, which configures the interrupt trigger mode of the external interrupt source to be high-level trigger, with a priority of 1, and is bound to the interrupt service program.

3. The method for real-time performance evaluation of a dedicated chip based on FPGA according to claim 1, characterized in that: The dynamic load task is started by the FreeRTOS scheduler, and the execution of the two tasks with the same priority forces the idle task to enter the blocked state, simulating CPU resource preemption and context switching in a high-load scenario.

4. The method for real-time performance evaluation of a dedicated chip based on FPGA according to claim 1, characterized in that: The real-time system uses FreeRTOS real-time system, and the version number is V10.3.

1.

5. The method for real-time performance evaluation of a dedicated chip based on FPGA according to claim 1, characterized in that: The FPGA uses Xilinx's AXU3EGB development board to provide an interrupt trigger source.

6. The method for real-time performance evaluation of a dedicated chip based on FPGA according to claim 1, characterized in that: The method for obtaining the interrupt response time includes: The GPIO output terminal of the FPGA is used to output an interrupt trigger signal, and the first LGPIO pin of the ASIC is used as an interrupt input signal, and the two are physically connected; the second LGPIO pin of the ASIC outputs a response signal, and the GPIO input terminal of the FPGA is used as a response input signal, and the two are physically connected; The FPGA uses a counter to generate a pulse signal by cyclically pulling up the GPIO, and at the same time marks the timestamp t1 at the rising edge of the level setting high; When the real-time kernel of the ASIC chip receives the rising edge level, it enters the interrupt response process; because the processing mode of the interrupt source is non-vector processing, the CPU will jump to the interrupt handler shared by all non-vector interrupts. After saving the registers mcause, mepc, and msubm and saving the general registers, it executes the instruction csrrw ra, CSR_JALMNXTI, ra to jump to the interrupt service routine of the interrupt source and finally enter the interrupt service routine LGPIO0_IRQHandler; In the interrupt service program LGPIO0_IRQHandler, the response LGPIO level is pulled high, and then the GPIO input end of the FPGA receives the rising edge level of the response signal, at which time the timestamp t2 is marked; The interrupt response time is calculated by the formula delay=t2-t1.

7. The method for real-time evaluation of a dedicated chip based on FPGA according to claim 6, characterized in that: The timestamp is obtained by using the general timer of the FPGA as a high-precision time source.

8. The method for real-time evaluation of a dedicated chip based on FPGA according to claim 7, characterized in that: The FPGA collects interrupt response time cyclically for a total of 100,000 times, thereby reducing the error and randomness of the test results.

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