Assembly line optimization method, device and equipment for SM4 encrypted circuit and medium

Abstract

The invention relates to the technical field of digital integrated circuit design, in particular to an SM4 encrypted circuit assembly line optimization method and device, equipment and a medium. The method comprises the following steps: acquiring the total number of rounds of encryption operation; based on the total number of rounds of encryption operation, the target SM4 encryption circuit is divided into a plurality of encryption assembly lines, and each encryption assembly line comprises at least one round of encryption operation; the method comprises the steps of obtaining a sub-key corresponding to each encryption operation round from a preset multi-round key library, dividing an encryption assembly line corresponding to each encryption operation round into a plurality of sub-assembly line stages, and controlling the plurality of sub-assembly line stages to execute corresponding encryption operations based on the sub-key corresponding to each encryption operation round. Therefore, by optimizing the pipeline architecture design, the subkey generation mechanism and the task scheduling strategy, the problem of performance reduction caused by data dependence in a hardware pipeline is solved, and the performance and the resource utilization rate of the SM4 hardware accelerator are improved.

Description

Technical Field

[0001] The present application relates to the technical field of digital integrated circuit design, and in particular to a pipeline optimization method, device, equipment and medium for an SM4 encryption circuit. Background Art

[0002] With the rapid development of information technology, data security has become a crucial issue in today's digital age. From protecting personal privacy to securing commercial secrets and safeguarding national critical information infrastructure, efficient encryption technology is essential. The SM4 block cipher, a commercial cryptographic algorithm independently designed in my country, boasts excellent security and performance. It is widely used in numerous fields, including finance, communications, the Internet of Things, and autonomous driving, meeting the demands for high-throughput and highly secure data encryption.

[0003] In related technologies, the SM4 hardware accelerator is mainly implemented based on a pipeline architecture, which is divided into a pipeline encryption part, a key expansion part, a task scheduling and data control part, and a data buffer and storage part.

[0004] However, in this method, subsequent rounds of calculations still need to wait for the results of the previous round, and there is a performance degradation problem caused by data dependence, which needs to be solved urgently. Summary of the Invention

[0005] The present application provides a pipeline optimization method, apparatus, device, and medium for an SM4 encryption circuit to solve the performance degradation problem caused by data dependency in the hardware pipeline and improve the performance and resource utilization of the SM4 hardware accelerator.

[0006] To achieve the above objectives, the first embodiment of the present application proposes a pipeline optimization method for an SM4 encryption circuit, comprising the following steps:

[0007] Get the total number of encryption rounds;

[0008] Based on the total number of encryption operation rounds, dividing the target SM4 encryption circuit into a plurality of encryption pipelines, wherein each encryption pipeline includes at least one encryption operation round;

[0009] From a preset multi-round sub-key library, obtain the sub-key corresponding to each encryption operation round, and divide the encryption pipeline corresponding to each encryption operation round into multiple sub-pipeline stages, and based on the sub-key corresponding to each encryption operation round, control the multiple sub-pipeline stages to perform corresponding encryption operations respectively.

[0010] According to one embodiment of the present application, when controlling the multiple sub-pipeline stages to respectively perform corresponding encryption operations based on the sub-key corresponding to each encryption operation round, the method further includes:

[0011] Get the current resource status and current bubble status of each sub-pipeline stage;

[0012] Adjust the data flow distribution of the multiple encryption pipelines according to the current resource state, and / or adjust the task distribution of the multiple encryption pipelines according to the current bubble state.

[0013] According to one embodiment of the present application, before obtaining the subkey corresponding to each encryption operation round from the preset multi-round subkey library, the method further includes:

[0014] Generate multiple round sub-keys, and store the multiple multi-round sub-keys in a preset first cache space to obtain the preset multi-round sub-key library.

[0015] According to one embodiment of the present application, after generating the multi-round sub-keys, the method further includes:

[0016] The multiple multi-round subkeys are stored in a preset second cache space, so that batch encryption tasks reuse the subkeys in the preset second cache space.

[0017] According to one embodiment of the present application, the target SM4 encryption circuit is divided into multiple encryption pipelines based on the total number of encryption operation rounds, including:

[0018] Determine the number of computational rounds for each encryption pipeline;

[0019] The multiple encryption pipelines are obtained based on the total number of encryption operation rounds and the number of calculation rounds of each encryption pipeline.

[0020] According to the pipeline optimization method for the SM4 encryption circuit proposed in the embodiment of the present application, based on the total number of encryption rounds, the target SM4 encryption circuit can be divided into multiple encryption pipelines, where each encryption pipeline includes at least one encryption round. The subkey corresponding to each encryption operation round is obtained from a preset multi-round subkey library, and the encryption pipeline corresponding to each encryption operation round is divided into multiple sub-pipeline stages. Based on the subkey corresponding to each encryption operation round, the multiple sub-pipeline stages are controlled to perform the corresponding encryption operations respectively. Thus, by optimizing the pipeline architecture design, subkey generation mechanism, and task scheduling strategy, the performance degradation problem caused by data dependence in the hardware pipeline is solved, and the performance and resource utilization of the SM4 hardware accelerator are improved.

[0021] To achieve the above objectives, a second embodiment of the present application provides a pipeline optimization device for an SM4 encryption circuit, comprising:

[0022] An acquisition module is used to obtain the total number of encryption rounds;

[0023] A partitioning module, configured to partition the target SM4 encryption circuit into a plurality of encryption pipelines based on the total number of encryption operation rounds, wherein each encryption pipeline includes at least one encryption operation round;

[0024] A control module is used to obtain the subkey corresponding to each encryption operation round from a preset multi-round subkey library, divide the encryption pipeline corresponding to each encryption operation round into multiple sub-pipeline stages, and control the multiple sub-pipeline stages to perform corresponding encryption operations based on the subkey corresponding to each encryption operation round.

[0025] According to one embodiment of the present application, when controlling the multiple sub-pipeline stages to respectively perform corresponding encryption operations based on the sub-key corresponding to each encryption operation round, the control module is further configured to:

[0026] Get the current resource status and current bubble status of each sub-pipeline stage;

[0027] Adjust the data flow distribution of the multiple encryption pipelines according to the current resource state, and / or adjust the task distribution of the multiple encryption pipelines according to the current bubble state.

[0028] According to one embodiment of the present application, before obtaining the subkey corresponding to each encryption operation round from the preset multi-round subkey library, the control module further includes:

[0029] The obtaining unit is configured to generate a plurality of multi-round sub-keys and store the plurality of multi-round sub-keys in a preset first cache space to obtain the preset multi-round sub-key library.

[0030] According to one embodiment of the present application, after generating the multi-round sub-keys, the obtaining unit is further configured to:

[0031] The multiple multi-round subkeys are stored in a preset second cache space, so that batch encryption tasks reuse the subkeys in the preset second cache space.

[0032] According to one embodiment of the present application, the partitioning module is specifically configured to:

[0033] Determine the number of computational rounds for each encryption pipeline;

[0034] The multiple encryption pipelines are obtained based on the total number of encryption operation rounds and the number of calculation rounds of each encryption pipeline.

[0035] According to the pipeline optimization device for the SM4 encryption circuit proposed in the embodiment of the present application, based on the total number of encryption rounds, the target SM4 encryption circuit can be divided into multiple encryption pipelines, where each encryption pipeline includes at least one encryption round. The subkey corresponding to each encryption operation round is obtained from a preset multi-round subkey library, and the encryption pipeline corresponding to each encryption operation round is divided into multiple sub-pipeline stages. Based on the subkey corresponding to each encryption operation round, the multiple sub-pipeline stages are controlled to perform the corresponding encryption operations respectively. Thus, by optimizing the pipeline architecture design, subkey generation mechanism, and task scheduling strategy, the performance degradation problem caused by data dependence in the hardware pipeline is solved, and the performance and resource utilization of the SM4 hardware accelerator are improved.

[0036] To achieve the above-mentioned objectives, the third aspect embodiment of the present application proposes an electronic device, comprising: a memory, a processor, and a computer program stored on the memory and executable on the processor, wherein the processor executes the program to implement the pipeline optimization method of the SM4 encryption circuit as described in the above embodiment.

[0037] To achieve the above-mentioned objectives, the fourth embodiment of the present application proposes a computer-readable storage medium on which a computer program is stored. The program is executed by a processor to implement the pipeline optimization method of the SM4 encryption circuit as described in the above embodiment.

[0038] Additional aspects and advantages of the present application will be given in part in the description below, and in part will become apparent from the description below, or will be learned through practice of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] The above and / or additional aspects and advantages of the present application will become apparent and easily understood from the following description of the embodiments in conjunction with the accompanying drawings, in which:

[0040] Figure 1 A flowchart of a pipeline optimization method for an SM4 encryption circuit provided according to an embodiment of the present application;

[0041] Figure 2 Schematic diagram of the SM4 encryption process according to one embodiment of the present application;

[0042] Figure 3 This is a flowchart of SM4 key expansion according to one embodiment of the present application;

[0043] Figure 4 Schematic diagram of the structure of the S-box in the SM4 round function according to one embodiment of the present application;

[0044] Figure 5 Schematic diagram of a four-stage pipeline structure according to one embodiment of the present application;

[0045] Figure 6 Schematic diagram of a pipeline wheel function according to one embodiment of the present application;

[0046] Figure 7 1 is a block diagram of a pipeline optimization system for an SM4 encryption circuit according to an embodiment of the present application;

[0047] Figure 8 Schematic diagram of a block diagram of a pipeline optimization device for an SM4 encryption circuit according to an embodiment of the present application;

[0048] Figure 9 A schematic diagram of the structure of an electronic device provided according to an embodiment of the present application. DETAILED DESCRIPTION

[0049] The following describes in detail embodiments of the present application. Examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are intended to be used to explain the present application, and should not be construed as limiting the present application.

[0050] The following describes the pipeline optimization method, device, equipment and medium of the SM4 encryption circuit proposed in accordance with the embodiments of the present application with reference to the accompanying drawings.

[0051] Figure 1 This is a flow chart of a pipeline optimization method for an SM4 encryption circuit according to an embodiment of the present application.

[0052] Before introducing the pipeline optimization method of the SM4 encryption circuit proposed in the embodiment of the present application, the relevant technical background is first introduced.

[0053] Currently, the following technical problems are common in the design of SM4 hardware accelerators: (1) Pipeline bubbles caused by data dependency: The SM4 encryption algorithm contains 32 rounds of iterative calculations, and the calculation results of each round depend on the intermediate data of the previous round and the corresponding round key. Therefore, in the pipeline architecture, the calculation of the subsequent round must wait until the previous round is completed before it can start. This data dependency will cause some stages of the pipeline to stagnate, forming "bubbles". This phenomenon reduces the throughput of the pipeline and significantly affects the hardware resource utilization and encryption efficiency. (2) Subkey generation dependency problem: The round keys of SM4 encryption need to be generated round by round through the key expansion module, while the encryption module of the pipeline needs to read the corresponding round keys in real time for calculation. If the speed of the key expansion module cannot keep up with the calculation speed of the round function, the pipeline will stagnate further, forming a more serious performance bottleneck. (3) Insufficient multi-data stream parallel processing capabilities: In high-throughput scenarios (such as autonomous driving), hardware accelerators need to process multiple encryption tasks simultaneously, but the current pipeline architecture lacks flexibility in resource scheduling and task allocation, and cannot effectively utilize hardware resources to process multi-data stream tasks, resulting in throughput that cannot meet high-performance requirements.

[0054] The primary technology currently used to address data dependency issues within the SM4 hardware pipeline is the pipeline-based SM4 cryptographic hardware accelerator. Its general structure comprises the following modules: a pipeline cryptographic module, a key expansion module, a task scheduling and data control module, and a data buffering and storage module. The pipeline cryptographic module is used to split round function operations into multiple pipeline stages; the key expansion module is responsible for generating round keys; the task scheduling and data control module manages data flow and task scheduling; and the data buffering and storage module temporarily stores data.

[0055] However, the above method has obvious limitations: the pipeline design does not completely solve the bubble problem caused by data dependence; the sub-key generation speed of the key expansion module may become a bottleneck; the parallel processing capability of multiple data streams is insufficient, the scheduling strategy is simple and the resource utilization is low.

[0056] Precisely in response to the aforementioned issues, an embodiment of the present application proposes a pipeline optimization method for an SM4 encryption circuit. Based on the total number of encryption rounds, the target SM4 encryption circuit can be divided into multiple encryption pipelines, each of which includes at least one encryption round. The subkey corresponding to each encryption round is obtained from a preset multi-round subkey library, and the encryption pipeline corresponding to each encryption round is divided into multiple sub-pipeline stages. Based on the subkey corresponding to each encryption round, the multiple sub-pipeline stages are controlled to perform the corresponding encryption operations. This method can solve the performance degradation problem caused by data dependency in the hardware pipeline and improve the performance and resource utilization of the SM4 hardware accelerator.

[0057] For example, Figure 1 As shown, the pipeline optimization method of the SM4 encryption circuit includes the following steps:

[0058] In step S101, the total number of encryption rounds is obtained.

[0059] The SM4 algorithm is a symmetric block cipher issued by the China National Cryptography Administration and widely used in China's commercial cryptography sector. The SM4 algorithm has a block length of 128 bits and a key length of 128 bits, meaning it processes 128-bit blocks of data at a time and uses a 128-bit key for encryption and decryption. The SM4 algorithm uses a 32-round iterative structure, representing the total number of rounds required for the encryption process (i.e., the total number of rounds), with each round using a different round key.

[0060] In step S102, based on the total number of encryption operation rounds, the target SM4 encryption circuit is divided into multiple encryption pipelines, wherein each encryption pipeline includes at least one round of encryption operation.

[0061] In other words, based on these 32 rounds of encryption operations, the entire target SM4 encryption circuit can be divided into multiple encryption pipelines. Each encryption pipeline contains several rounds of encryption operations. This division allows for parallel processing of multiple stages, reducing the impact of data dependencies between adjacent rounds, thereby improving encryption efficiency.

[0062] As a possible implementation method, in some embodiments, the target SM4 encryption circuit is divided into multiple encryption pipelines based on the total number of encryption operation rounds, including: determining the number of calculation rounds for each encryption pipeline; and obtaining multiple encryption pipelines based on the total number of encryption operation rounds and the number of calculation rounds for each encryption pipeline.

[0063] Specifically, first, the number of calculation rounds of each encryption pipeline can be determined. Then, based on the total number of encryption operations and the determined number of calculation rounds of each encryption pipeline, multiple encryption pipelines working in parallel can be calculated and designed to achieve higher data processing capabilities and encryption efficiency.

[0064] For example, an embodiment of the present application can divide 32 rounds of encryption operations into four independent pipeline stages, with each pipeline stage responsible for processing eight rounds of encryption calculation tasks. In this design approach, the input data of each pipeline stage is directly derived from the output results of the previous pipeline stage. In this way, each stage of the pipeline can operate in a relatively independent environment, effectively reducing the propagation and impact of data dependencies throughout the pipeline.

[0065] In step S103, the sub-key corresponding to each encryption operation round is obtained from the preset multi-round sub-key library, and the encryption pipeline corresponding to each encryption operation round is divided into multiple sub-pipeline stages, and based on the sub-key corresponding to each encryption operation round, the multiple sub-pipeline stages are controlled to perform corresponding encryption operations respectively.

[0066] Specifically, the round function in the SM4 algorithm includes three main operations: S-box replacement, linear transformation, and round key addition. In order to further improve the performance of the entire encryption circuit, the embodiment of the present application can split each round of encryption calculation tasks in each encryption pipeline of the SM4 encryption algorithm, and further subdivide its calculation process into multiple sub-pipeline stages, that is, specifically divided into three stages: S-box replacement, linear transformation, and round key addition. Such subdivision realizes the pipelining within the round function, that is, the encryption operations originally executed sequentially within a round are decomposed into different hardware modules so that they can be executed independently. Even within a single round, data can be transferred in a streaming manner between each sub-pipeline stage.

[0067] Furthermore, by introducing data buffers between sub-pipeline stages, asynchronous data transfer is achieved. This means that data can be transferred between sub-pipeline stages without waiting for the previous sub-pipeline stage to complete all operations or for the next sub-pipeline stage to be ready. Based on this asynchronous transfer mechanism, when a sub-pipeline stage completes its encryption operation and writes the result to the buffer, the next sub-pipeline stage can read the data from the buffer for subsequent processing without having to wait for the previous sub-pipeline stage to complete its encryption operation. This reduces the impact of computational delays in the previous pipeline stage on subsequent stages.

[0068] Furthermore, in some embodiments, when controlling multiple sub-pipeline stages to respectively perform corresponding encryption operations based on the sub-key corresponding to each encryption operation round, it also includes: obtaining the current resource status and current bubble status of each sub-pipeline stage; adjusting the data flow distribution of multiple encryption pipelines according to the current resource status, and / or adjusting the task distribution of multiple encryption pipelines according to the current bubble status.

[0069] It is understandable that in order to improve the throughput of the entire SM4 encryption circuit and make it perform better when processing a large number of encryption tasks, the embodiment of the present application performs intelligent allocation and scheduling of resources through a dynamic task scheduling mechanism. Specifically, by obtaining the current (hardware) resource status and the current bubble status of each sub-pipeline stage, the so-called "bubble" refers to the idle state in the pipeline due to waiting for data or other reasons, which will cause waste of resources. First, the distribution of data streams can be dynamically adjusted according to the current resource status, such as which pipeline routes are idle and which are busy. This ensures that pipeline resources are maximized, avoids idle resources, and thus improves the overall encryption efficiency. Secondly, a bubble detection circuit can be integrated into the pipeline. Once a bubble is detected, other data streams waiting to be processed can be automatically allocated to the idle pipeline line level. This can reduce the waste of resources caused by bubbles, keep the pipeline running efficiently, and avoid the emergence of performance bottlenecks.

[0070] The following describes in detail how to obtain the preset multi-round key library.

[0071] Furthermore, in some embodiments, before obtaining the subkey corresponding to each encryption operation round from the preset multi-round sub-key library, it also includes: generating multi-round sub-keys and storing the multiple multi-round sub-keys in a preset first cache space to obtain the preset multi-round sub-key library.

[0072] Specifically, when executing the round function pipeline operation of the encryption operation, the subkey generation operation can also be executed in parallel. In other words, they can run simultaneously without interfering with each other. At the beginning of the encryption process, the subkey generation operation can run independently, generating all 32 round subkeys required for SM4 encryption at one time, and storing these subkeys in a cache (i.e., the preset first cache space) to form a preset multi-round subkey library. The advantage of this is that when the encryption pipeline reaches the corresponding round, the prepared subkey can be read directly from the preset first cache space without waiting for the subkey to be generated on the spot, reducing the waiting time during the encryption process.

[0073] Furthermore, in some other embodiments, after generating the multi-round subkeys, the method further includes: storing the multiple multi-round subkeys in a preset second cache space, so that the batch encryption tasks reuse the subkeys in the preset second cache space.

[0074] Specifically, after generating multiple rounds of subkeys, in addition to storing them in a preset first cache space, a high-speed caching mechanism can also be used to store multiple multi-round subkeys in a preset second cache space. The preset second cache space is an on-chip high-speed memory. The on-chip high-speed memory has a fast read and write speed, which can meet the needs of multiple data stream tasks for fast access to subkeys and ensure the efficiency of the encryption process. In the case of batch encryption tasks, multiple encryption tasks can reuse the subkeys in the preset second cache space. This can avoid repeated calculation of subkeys, save computing resources, and improve the computing efficiency of the entire encryption hardware.

[0075] It can be understood that in the embodiment of the present application, the two processes of subkey generation and round function pipeline execution can be completely separated. That is, when the round function performs the encryption operation, there is no need to wait for the subkey to be slowly generated, which eliminates the pipeline stagnation caused by untimely key generation and improves the hardware computing efficiency.

[0076] To facilitate those skilled in the art to further understand the pipeline optimization method of the SM4 encryption circuit proposed in the embodiments of the present application, it is further elaborated below in conjunction with specific embodiments.

[0077] like Figure 2 As shown, Figure 2 This is a diagram of the SM4 encryption process. The process begins with the input of plaintext data, typically a 128-bit block. The encryption process then begins. The first step (initial key encryption) involves performing an exclusive-or operation on the input plaintext and the initial key to ensure initial randomness. After initial key encryption, the data undergoes 32 rounds of iterative operations. Each round includes several key operations: S-box substitution, linear transformation, and round key addition. After 32 rounds of iterative operations, the final ciphertext data is obtained, which is also 128 bits.

[0078] like Figure 3 As shown, Figure 3 This is the SM4 key expansion flow chart. The process begins with a 128-bit master key as input, followed by a key expansion operation. The master key is used to generate 32 round keys through the key expansion process. This key expansion process uses a nonlinear feedback shift register structure and introduces a fixed constant array to ensure the generated round keys have good randomness and cryptographic properties. Each of the 32 generated round keys is 32 bits long and is used in each round of encryption iteration.

[0079] Figure 4 This is a schematic diagram of the structure of the S-box in the SM4 round function, as shown in Figure 4As shown, an S-box receives 8 bits of input data. Inside the S-box, the input data undergoes a nonlinear transformation, producing a new 8-bit output. This transformation is based on a predefined substitution table, replacing the 8-bit input data with the new 8-bit output data. The S-box is designed to increase the nonlinearity of the encryption algorithm, making it difficult for attackers to decipher the key through linear analysis.

[0080] Furthermore, if Figure 5 As shown, Figure 5 A schematic diagram of the four-stage pipeline structure is shown. The 32 rounds of SM4 encryption are divided into four pipeline stages, with each stage responsible for completing eight rounds of encryption calculations. This allows the 32 rounds, which would normally be executed sequentially, to be performed in parallel, allowing each pipeline stage to process different data blocks at different times. During the normal pipeline startup phase, the first three cycles are primarily dedicated to filling the pipeline. In the first cycle, the first pipeline stage begins executing its eight rounds of encryption calculations. In the second cycle, the first pipeline stage continues processing while the second pipeline stage begins. In the third cycle, the first three pipeline stages execute sequentially, and the fourth pipeline stage starts. After four cycles, the pipeline is fully filled. Once the pipeline is filled, each cycle outputs a piece of encrypted data ciphertext. This is because each pipeline stage continuously processes data, and after processing a data block, each stage passes it to the next stage. Therefore, starting from the fourth cycle, each cycle will complete the processing of a data block through all four pipeline stages, outputting a piece of encrypted ciphertext.

[0081] Figure 6 The hardware implementation structure of the round function in the SM4 encryption circuit is shown, such as Figure 6 As shown in Figure 1, the round key encryption hardware features four independent 32-bit XOR units, each dedicated to processing a 32-bit data block. Since the SM4 algorithm uses a 128-bit block length, these four units can perform XOR operations on 128 bits of data in parallel, with each unit processing 32 bits. This enables efficient parallel computing and significantly improves encryption speed.

[0082] The S-box replacement operation processes 16 bytes of 128-bit data at a time. Each byte undergoes a nonlinear replacement through the S-box, a key nonlinear transformation step in the SM4 algorithm that increases encryption complexity and security. Since 128-bit data consists of 16 bytes, the designed S-box replacement module can perform the replacement operation on all 16 bytes simultaneously, maximizing parallelism and reducing processing latency.

[0083] During the linear transformation and XOR operation, each shift operation is performed by an independent shift module. Specifically, there are four shift modules, which can operate in parallel within a single clock cycle. This design enables fast shift operations, improving the efficiency of the linear transformation. The result of the XOR operation is stored in a buffer, which temporarily stores intermediate results for use in the next round of encryption. This ensures smooth data flow within the pipeline and reduces delays caused by data waiting.

[0084] Figure 7This is a block diagram of the pipeline optimization system for the SM4 encryption circuit involved in the pipeline optimization method for the SM4 encryption circuit proposed in an embodiment of the present application. The system consists of a data input buffer, a subkey generation and cache module, a dynamic task scheduling module, a hierarchical pipeline module, an intermediate state buffer module, and an output module. The input buffer is used to receive and store data blocks to be encrypted, ensuring that the data is ready before the pipeline is started. Data can be loaded from the main memory to the input buffer via DMA (Direct Memory Access). The buffer supports preprocessing of batch tasks and provides services for multiple task streams at the same time. The subkey generation and cache module can independently generate the 32-round subkeys required for the SM4 algorithm and store them in a shared cache. The cache module supports concurrent access to the pipeline, avoiding direct dependency between the subkey generation process and pipeline calculations. All subkeys are generated during task initialization to eliminate key generation delays. A shared access mechanism is also provided, allowing multiple tasks to reuse the same subkey resources. The dynamic task scheduling module is used to dynamically monitor the status of pipeline resources (such as bubble / idle status) and intelligently assign new tasks to idle pipeline stages. This module supports parallel processing of multiple data stream tasks, maximizing pipeline utilization. It integrates bubble detection circuitry, enabling real-time monitoring of idle resources within the pipeline (e.g., when a stage is stalled). When idle resources are detected, new tasks are scheduled to the corresponding pipeline stage, fully utilizing hardware resources. Furthermore, the module can simultaneously manage multiple task queues, allocating independent or shared resources to each task stream, improving the efficiency of multi-task parallel processing. The hierarchical pipeline module divides the 32-round SM4 algorithm into four stages, with each stage responsible for eight rounds. Data is passed from stage to stage, reducing dependencies. Data is passed from stage to stage, and each pipeline stage is connected via an intermediate buffer, enabling asynchronous computation. Within each pipeline stage, a single round of computation is split into sub-stages, further increasing parallelism. This design allows the pipeline to operate independently within each stage, reducing the propagation of data dependencies throughout the pipeline, thereby preventing the spread of data bubbles and improving pipeline throughput. The intermediate state buffer module stores intermediate state between pipeline stages, supporting asynchronous data exchange among multiple tasks. After each pipeline stage completes computation, the intermediate results are written to the buffer. The next pipeline stage reads data from the buffer without waiting for the previous stage to complete, reducing the impact of computational delays on subsequent stages. The buffer supports a FIFO (First In, First Out) mechanism to ensure the order and efficiency of data delivery. The output module is responsible for outputting the final results to the buffer or other main memory. When the data completes all 32 rounds of computation in the final pipeline stage, the results are written to the output buffer and ultimately returned to the user or other system modules.

[0085] According to the pipeline optimization method for the SM4 encryption circuit proposed in the embodiment of the present application, based on the total number of encryption rounds, the target SM4 encryption circuit can be divided into multiple encryption pipelines, where each encryption pipeline includes at least one encryption round. The subkey corresponding to each encryption operation round is obtained from a preset multi-round subkey library, and the encryption pipeline corresponding to each encryption operation round is divided into multiple sub-pipeline stages. Based on the subkey corresponding to each encryption operation round, the multiple sub-pipeline stages are controlled to perform the corresponding encryption operations respectively. Thus, by optimizing the pipeline architecture design, subkey generation mechanism, and task scheduling strategy, the performance degradation problem caused by data dependence in the hardware pipeline is solved, and the performance and resource utilization of the SM4 hardware accelerator are improved.

[0086] Next, the pipeline optimization device of the SM4 encryption circuit proposed in the embodiment of the present application is described with reference to the accompanying drawings.

[0087] Figure 8 It is a block diagram of a pipeline optimization device for an SM4 encryption circuit according to an embodiment of the present application.

[0088] like Figure 8 As shown, the pipeline optimization device 10 of the SM4 encryption circuit includes: an acquisition module 100, a division module 200 and a control module 300.

[0089] The acquisition module 100 is used to obtain the total number of encryption rounds;

[0090] A partitioning module 200 is configured to partition the target SM4 encryption circuit into a plurality of encryption pipelines based on the total number of encryption operation rounds, wherein each encryption pipeline includes at least one encryption operation round;

[0091] The control module 300 is used to obtain the sub-key corresponding to each encryption operation round from a preset multi-round sub-key library, divide the encryption pipeline corresponding to each encryption operation round into multiple sub-pipeline stages, and control the multiple sub-pipeline stages to perform corresponding encryption operations respectively based on the sub-key corresponding to each encryption operation round.

[0092] Optionally, in some embodiments, when controlling multiple sub-pipeline stages to respectively perform corresponding encryption operations based on the sub-key corresponding to each encryption operation round, the control module 300 is further configured to:

[0093] Get the current resource status and current bubble status of each sub-pipeline stage;

[0094] Adjust data flow distribution of multiple encryption pipelines according to current resource status, and / or adjust task distribution of multiple encryption pipelines according to current bubble status.

[0095] Optionally, in some embodiments, before obtaining the subkey corresponding to each encryption operation round from the preset multi-round subkey library, the control module 300 further includes:

[0096] The obtaining unit is used to generate a multi-round sub-key and store the multiple multi-round sub-keys in a preset first cache space to obtain a preset multi-round sub-key library.

[0097] Optionally, in some embodiments, after generating multiple rounds of subkeys, the obtaining unit is further configured to:

[0098] The plurality of multi-round subkeys are stored in a preset second cache space, so that the batch encryption tasks reuse the subkeys in the preset second cache space.

[0099] Optionally, in some embodiments, the partitioning module 200 is specifically configured to:

[0100] Determine the number of computational rounds for each encryption pipeline;

[0101] Based on the total number of encryption operation rounds and the number of calculation rounds of each encryption pipeline, multiple encryption pipelines are obtained.

[0102] It should be noted that the above explanation of the embodiment of the pipeline optimization method for the SM4 encryption circuit is also applicable to the pipeline optimization device for the SM4 encryption circuit of this embodiment, and will not be repeated here.

[0103] According to the pipeline optimization device for the SM4 encryption circuit proposed in the embodiment of the present application, based on the total number of encryption rounds, the target SM4 encryption circuit can be divided into multiple encryption pipelines, where each encryption pipeline includes at least one encryption round. The subkey corresponding to each encryption operation round is obtained from a preset multi-round subkey library, and the encryption pipeline corresponding to each encryption operation round is divided into multiple sub-pipeline stages. Based on the subkey corresponding to each encryption operation round, the multiple sub-pipeline stages are controlled to perform the corresponding encryption operations respectively. Thus, by optimizing the pipeline architecture design, subkey generation mechanism, and task scheduling strategy, the performance degradation problem caused by data dependence in the hardware pipeline is solved, and the performance and resource utilization of the SM4 hardware accelerator are improved.

[0104] Figure 9 This is a schematic diagram of the structure of an electronic device provided in an embodiment of the present application. The electronic device may include:

[0105] A memory 901 , a processor 902 , and a computer program stored in the memory 901 and executable on the processor 902 .

[0106] When the processor 902 executes the program, the pipeline optimization method of the SM4 encryption circuit provided in the above embodiment is implemented.

[0107] Furthermore, the electronic device further includes:

[0108] The communication interface 903 is used for communication between the memory 901 and the processor 902 .

[0109] The memory 901 is used to store computer programs that can be run on the processor 902 .

[0110] The memory 901 may include a high-speed RAM (Random Access Memory) memory, and may also include a non-volatile memory, such as at least one disk memory.

[0111] If the memory 901, the processor 902, and the communication interface 903 are implemented independently, the communication interface 903, the memory 901, and the processor 902 can be connected to each other via a bus and communicate with each other. The bus can be an ISA (Industry Standard Architecture) bus, a PCI (Peripheral Component Interconnect) bus, or an EISA (Extended Industry Standard Architecture) bus. The bus can be divided into an address bus, a data bus, a control bus, etc. For ease of representation, Figure 9 Only one thick line is used in the diagram, but this does not mean that there is only one bus or one type of bus.

[0112] Optionally, in a specific implementation, if the memory 901, the processor 902 and the communication interface 903 are integrated on a chip, the memory 901, the processor 902 and the communication interface 903 can communicate with each other through an internal interface.

[0113] The processor 902 may be a CPU (Central Processing Unit), or an ASIC (Application Specific Integrated Circuit), or one or more integrated circuits configured to implement the embodiments of the present application.

[0114] An embodiment of the present application also provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the pipeline optimization method of the SM4 encryption circuit as described above.

[0115] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of the technical features being referred to. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of such features. Throughout the description of this application, "plurality" means at least two, for example, two, three, etc., unless otherwise specifically defined.

[0116] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art can combine and combine different embodiments or examples described in this specification and features of different embodiments or examples without contradiction.

[0117] Although the embodiments of the present application have been shown and described above, it can be understood that the above embodiments are exemplary and cannot be understood as limitations on the present application. Ordinary technicians in this field can change, modify, replace and modify the above embodiments within the scope of the present application.

Claims

1. A pipeline optimization method for an SM4 encryption circuit, characterized in that: The following steps are involved: Get the total number of encryption rounds; Based on the total number of encryption operation rounds, dividing the target SM4 encryption circuit into a plurality of encryption pipelines, wherein each encryption pipeline includes at least one encryption operation round; From a preset multi-round sub-key library, obtain the sub-key corresponding to each encryption operation round, and divide the encryption pipeline corresponding to each encryption operation round into multiple sub-pipeline stages, and based on the sub-key corresponding to each encryption operation round, control the multiple sub-pipeline stages to perform corresponding encryption operations respectively.

2. The method according to claim 1, characterized in that When controlling the plurality of sub-pipeline stages to respectively perform corresponding encryption operations based on the sub-key corresponding to each encryption operation round, the method further includes: Get the current resource status and current bubble status of each sub-pipeline stage; Adjust the data flow distribution of the multiple encryption pipelines according to the current resource state, and / or adjust the task distribution of the multiple encryption pipelines according to the current bubble state.

3. The method according to claim 1, characterized in that Before obtaining the subkey corresponding to each encryption operation round from the preset multi-round subkey library, the method further includes: Generate multiple round sub-keys, and store the multiple multi-round sub-keys in a preset first cache space to obtain the preset multi-round sub-key library.

4. The method according to claim 3, characterized in that After generating the multi-round sub-keys, the method further includes: The multiple multi-round subkeys are stored in a preset second cache space, so that batch encryption tasks reuse the subkeys in the preset second cache space.

5. The method according to claim 1, wherein The target SM4 encryption circuit is divided into multiple encryption pipelines based on the total number of encryption operation rounds, including: Determine the number of computational rounds for each encryption pipeline; The multiple encryption pipelines are obtained based on the total number of encryption operation rounds and the number of calculation rounds of each encryption pipeline.

6. A pipeline optimization device for an SM4 encryption circuit, characterized in that: include: An acquisition module is used to obtain the total number of encryption rounds; A partitioning module, configured to partition the target SM4 encryption circuit into a plurality of encryption pipelines based on the total number of encryption operation rounds, wherein each encryption pipeline includes at least one encryption operation round; A control module is used to obtain the subkey corresponding to each encryption operation round from a preset multi-round subkey library, divide the encryption pipeline corresponding to each encryption operation round into multiple sub-pipeline stages, and control the multiple sub-pipeline stages to perform corresponding encryption operations based on the subkey corresponding to each encryption operation round.

7. The device according to claim 6, characterized in that The control module is specifically used to: Get the current resource status and current bubble status of each sub-pipeline stage; Adjust the data flow distribution of the multiple encryption pipelines according to the current resource state, and / or adjust the task distribution of the multiple encryption pipelines according to the current bubble state.

8. The device according to claim 6, characterized in that Before obtaining the subkey corresponding to each encryption operation round from the preset multi-round subkey library, the control module further includes: The obtaining unit is configured to generate a plurality of multi-round sub-keys and store the plurality of multi-round sub-keys in a preset first cache space to obtain the preset multi-round sub-key library.

9. An electronic device, characterized in that: include: A memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the program to implement the pipeline optimization method for the SM4 encryption circuit according to any one of claims 1 to 5.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that: The program is executed by a processor to implement the pipeline optimization method for the SM4 encryption circuit according to any one of claims 1 to 5.

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