Systems and methods for improved amplitude shift keying (ASK) communications in wireless power transfer applications

Abstract

The present disclosure relates to systems and methods for improved amplitude shift keying (ASK) communications in wireless power transfer applications. The comparator has a hysteresis value that is adjustable in response to the hysteresis setting control signal. An input of the comparator receives a modulated signal polluted by in-band noise. The pulse signal output from the comparator is converted into an analog signal by a digital-to-analog converter circuit. The analog signal is converted to a digital signal value by an analog-to-digital converter. A comparison circuit compares the digital signal value with a threshold value and generates a hysteresis setting control signal to adjust a hysteresis value of the comparator in response to a result of the comparison so as to suppress in-band noise from an output of the pulse signal output from the comparator.

Description

Technical Field

[0001] The present invention relates generally to wireless power transfer, and in particular to improvements in amplitude shift keying (ASK) communication over a wireless power transfer interface. Background Art

[0002] refer to Figure 1 , Figure 1 A simplified block diagram of a wireless power transfer system 10 is shown. The system 10 includes a wireless power transmitter (TX) 12 and a wireless power receiver (RX) 14. Magnetic inductive coupling exists between the wireless power transmitter 12 and the wireless power receiver 14. Both the transmitter 12 and the receiver 14 include resonant circuits 16tx, 16rx formed by a series connection of a capacitor C and an inductor L. The transmitter 12 and the receiver 14 also include circuitry configured to handle communication and power transfer.

[0003] To establish power transfer from the transmitter 12 to the receiver 14, and to assist in controlling the power transfer, the transmitter 12 and the receiver 14 execute a communication protocol with each other governed by established industry standards (e.g., using the Qi standard protocol, as known to those skilled in the art and defined by the Wireless Power Consortium (WPC)). This communication protocol uses frequency shift keying (FSK) modulation for information communication sent from the transmitter 12 to the receiver 14 (for example, in providing synchronization and information transfer to the receiver), and uses amplitude shift keying (ASK) modulation for communication sent from the receiver 14 to the transmitter 12 (for example, in conveying requests and information to the transmitter). FSK modulation is achieved by the transmitter 12 modulating its operating frequency. ASK modulation is achieved by the receiver 14 modulating its reflected impedance.

[0004] Power transfer from transmitter 12 to receiver 14, as well as communication between the transmitter and receiver, is achieved using magnetic inductive coupling between inductors L of resonant circuits 16tx and 16rx. Therefore, communication between the transmitter and receiver is inevitably affected by in-band switching noise from the power transfer. In the case of high-power transfer from transmitter 12 to receiver 14, this in-band noise can cause communication failures in the information transfer from the receiver to the transmitter. Communication failures during wireless power transfer can adversely affect the safety and efficiency of the power transfer operation. In practical applications, the communication robustness of ASK modulation used to convey information from receiver 14 to transmitter 12 is poorer than the communication robustness of FSK modulation used for communication from transmitter 12 to receiver 14.

[0005] There is a need in the art to improve the communication robustness of ASK modulation used to convey information from the receiver 14 to the transmitter 12 . Summary of the Invention

[0006] In one embodiment, a circuit includes: a comparator having a hysteresis value that can be adjusted in response to a hysteresis setting control signal; wherein an input of the comparator is configured to receive a modulated signal contaminated by in-band noise; a digital-to-analog converter circuit configured to convert a pulse signal output from the comparator into an analog signal; an analog-to-digital converter configured to convert the analog signal into a digital signal value; and a comparison circuit configured to compare the digital signal value with a threshold value and generate a hysteresis setting control signal in response to a result of the comparison to adjust the hysteresis value of the comparator so as to suppress in-band noise from an output of the pulse signal output from the comparator.

[0007] In one embodiment, a method includes: a) resetting the hysteresis of an adjustable hysteresis comparator in response to completion of a modulation signal frame; b) converting a pulse signal output from the adjustable hysteresis comparator into an analog signal; c) converting the analog signal into a digital signal value; d) comparing the digital signal value with a threshold; e1) if the digital signal value is less than the threshold, increasing the hysteresis value of the adjustable hysteresis comparator and returning to step b); and e2) if the digital signal value is not less than the threshold, utilizing the hysteresis value of the adjustable hysteresis comparator until completion of the next modulation signal frame.

[0008] In one embodiment, a wireless power transfer system includes: a wireless power transmitter; and a wireless power receiver; wherein the wireless power transmitter and the wireless power receiver are coupled for power transfer from the wireless power transmitter to the wireless power receiver and for information transmission from the wireless power receiver to the wireless power transmitter. The wireless power transmitter includes: a circuit configured to receive a modulated information transmission signal from the wireless power receiver and generate a modulated signal contaminated by in-band noise; a comparator having a hysteresis value adjustable in response to a hysteresis setting control signal; wherein an input of the comparator is configured to receive the modulated signal contaminated by in-band noise; a digital-to-analog converter circuit configured to convert a pulse signal output from the comparator into an analog signal; an analog-to-digital converter configured to convert the analog signal into a digital signal value; and a comparison circuit configured to compare the digital signal value with a threshold value and, in response to the comparison result, generate a hysteresis setting control signal to adjust the hysteresis value of the comparator to suppress in-band noise from the output of the pulse signal output from the comparator. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] For a better understanding of the embodiments, reference will now be made, by way of example only, to the accompanying drawings, in which:

[0010] Figure 1 shows a simplified block diagram of a wireless power transfer system;

[0011] Figure 2 A block diagram of a wireless power transmitter circuit is shown;

[0012] Figure 3 A block diagram showing a portion of an ASK demodulation circuit;

[0013] Figure 4 A block diagram showing a portion of another ASK demodulation circuit;

[0014] Figures 5A to 5C illustrates a signal waveform at the output of a hysteresis comparator of an ASK demodulation circuit with different adjustable hysteresis values; and

[0015] Figure 6 is a flowchart illustrating the operation of a hysteresis control circuit for controlling the setting of an adjustable hysteresis of a hysteresis comparator of an ASK demodulation circuit. DETAILED DESCRIPTION

[0016] Now refer to Figure 2 , Figure 2 FIG shows a block diagram of a wireless power transmitter circuit 100. The circuit 100 may be used, for example, with Figure 1The wireless power transmitter circuit 100 is used in conjunction with the transmitter 12 of the system 10. The resonant circuit 16tx for the wireless power transmitter circuit 100 is driven by a full-bridge circuit 102. The full-bridge circuit 102 includes a first half-bridge formed by a series connection of a first high-side driver transistor 104 and a first low-side driver transistor 106. In this implementation, transistors 104 and 106 can both be n-channel power MOSFET devices. The drain of transistor 104 is coupled to the bridge power supply node Vb, and the source of transistor 104 is coupled to a first switching node 108. The drain of transistor 106 is coupled to the first switching node 108, and the source of transistor 106 is coupled to the ground reference node Vgnd. The full-bridge circuit 102 also includes a second half-bridge formed by a series connection of a second high-side driver transistor 114 and a second low-side driver transistor 116. In this implementation, transistors 114 and 116 can both be n-channel power MOSFET devices. The drain of transistor 114 is coupled to the bridge power supply node Vb, and the source of transistor 114 is coupled to the second switching node 118. The drain of transistor 116 is coupled to the second switching node 118, and the source of transistor 116 is coupled to the ground reference node Vgnd. The resonant circuit 16tx of the transmitter circuit 12 includes an inductor L and a capacitor C coupled in series with each other between the first switching node 108 and the second switching node 118. For example, a first terminal of the inductor L is connected to the first switching node 108, a second terminal of the inductor L is connected to the first terminal of the capacitor C at the intermediate node 146, and a second terminal of the capacitor C is connected to the second switching node 118. The selective actuation of the transistors 104, 106, 114, and 116 is controlled by a pulse width modulation (PWM) control circuit 130, which is configured to generate control signals (G1, G2, G3, G4) that are applied to the gate terminals of the transistors in the bridge circuit 102. Other operations of the transmitter related to wireless power transfer are controlled by other control circuits in a manner known in the art.

[0017] A first amplitude shift keying (ASK) demodulation circuit 140 of the wireless power transmitter circuit 100 is coupled to sense the current flowing through the first half-bridge and / or the second half-bridge of the full-bridge circuit 102 using a current sensing circuit 142 (e.g., including a current sensing resistor). A second amplitude shift keying (ASK) demodulation circuit 144 of the wireless power transmitter circuit 100 is coupled to sense the voltage at an intermediate node 146 between the series-connected inductor L and capacitor C of the resonant circuit 16tx. The signals demodulated by the first and second ASK demodulation circuits 140 and 144 from the receiver 14 (see FIG. Figure 1) is processed in feedback circuit 150 to control the operation of PWM control circuit 130. Feedback circuit 150 may, for example, include signal processing (or microcontroller) circuitry that processes the demodulated information and generates control signals for controlling PWM control circuit 130. It will be appreciated that the demodulation results do not necessarily directly control the operation of PWM control circuit 130. Feedback circuit 150 control is a logic control operation. The demodulated information can be used by PWM control circuit 130 to adjust the frequency and / or duty cycle of PWM signaling. The demodulated information can also be used, for example, by other control circuits of transmitter 12 to adjust voltage.

[0018] Now refer to Figure 3 , Figure 3A block diagram of a portion of the first ASK demodulation circuit 140 is shown. A signal conditioning circuit 200 is coupled to sense a voltage drop across a resistor of the current sensing circuit 142 and generate a sensed bridge current signal 202. The signal conditioning circuit 200 may, for example, include a differential amplifier circuit configured to sense the voltage drop across a resistor of the current sensing circuit 142. A gain stage circuit 204 applies a selected gain G to the sensed bridge current signal 202 to generate an amplified sensed bridge current signal 206. The amplified sensed bridge current signal 206 is filtered by a bandpass filter circuit 208 to filter out the carrier signal and generate an analog current demodulation signal (Idemod_ana) 210 that retains only the modulation signal (possibly contaminated by in-band noise). The bandpass filter circuit 208 may, for example, include a cascade of a high-pass filter (e.g., a second-order Butterworth filter) and a low-pass filter (e.g., a second-order Butterworth filter). The analog current demodulation signal 210 is input to a comparator circuit 212 with an adjustable hysteresis H to generate a digital current demodulation signal (Idemod_dig) 214. The signal Idemod_dig 214 can be considered a pulse width modulated (PWM) signal, whether for ASK frames or in-band noise. The dashed double-ended arrow schematically illustrates the step-wise change of the hysteresis H in response to the hysteresis control signal 242 (where the comparator circuit 212 is selectively controllable to be set to any one of a plurality of discrete hysteresis values). The control of the hysteresis H setting is performed to substantially (if not completely) eliminate in-band switching noise. The analog current demodulation signal 210 and the digital current demodulation signal 214 can then be further processed by the processing circuit 220 to generate demodulation information transmitted by the receiver 14 of the wireless power transfer system 10. For example, the processing circuit 220 can implement a signal decoding operation. The output from the processing circuit 220 may be used in conjunction with the feedback circuit 150, which controls the operation of the PWM control circuit 130 and / or other control circuits of the transmitter 12. Additionally, the analog current demodulated signal (Idemod_ana) 210 may be converted by an analog-to-digital converter to provide a digital value in a feedback control loop 250, which is used to adjust the gain setting of the gain stage circuit 204. Furthermore, the digital current demodulated signal (Idemod_dig) 214 may be detected and decoded to recover the information transmitted by the receiver circuit 14.

[0019] The hysteresis control circuit 230 operates to control the setting of the adjustable hysteresis H of the comparator circuit 212. The hysteresis control circuit 230 includes a digital-to-analog converter (DAC) circuit 232 that converts the output pulses of the digital current demodulation signal (Idemod_dig) 214 into an analog voltage level 234 that indicates the amount of in-band noise present in the ASK modulation signal. As an example, a resistor-capacitor circuit can be used to convert the PWM pulses of the digital current demodulation signal (Idemod_dig) 214 into an analog voltage level 234, and the level of the analog voltage level 234 depends on the duty cycle. The analog voltage level 234 for a correct ASK frame is generally a constant at a fraction of the supply Vdd voltage level, while the analog voltage level 234 for in-band noise to be eliminated is close to the Vdd level. However, in the case where there is in-band noise in the signal Idemod_dig 214, the analog voltage level 234 has a relatively low value. The analog-to-digital converter circuit 236 converts the analog voltage level 234 into a digital value (Dv) 238. The threshold comparison circuit 240 compares the digital value 238 with a digital threshold (Dth). In the case where the digital value 238 is greater than or equal to the digital threshold (i.e., Dv≥Dth), the hysteresis control circuit 230 does not adjust the adjustable hysteresis H of the comparator circuit 212 via the hysteresis control signal 242. However, in the case where the digital value 238 is less than the digital threshold (i.e., Dv<Dth), the hysteresis control circuit 230 incrementally increases the adjustable hysteresis H of the comparator circuit 212 (e.g., by one step value) using the hysteresis control signal 242. This operation is repeated,随之递增增加可调整滞后H,直到数字值236大于或等于数字阈值(即Dv≥Dth)。将注意,如果在执行该过程中达到可调整滞后H的最大值,那么阈值比较电路240将不再尝试执行可调整滞后H的递增增加。

[0020] In one embodiment, the gain stage circuit 204 can have selectable gain levels (e.g., at multiple discrete values or within a range of values). As an example, and not by way of limitation, the gain stage circuit 204 can be operable at two discrete gain levels, where the choice between the two levels depends on the analog current demodulation signal (Idemod_ana) 210 as discussed above. Alternatively, the gain stage circuit 204 can be omitted. Additionally, a signal conditioning circuit 200 can be used instead to implement gain control.

[0021] Now refer to Figure 4 , Figure 4 It should be noted that there is an unclear part in the translation of which is marked as "随之递增增加可调整滞后H,直到数字值236大于或等于数字阈值(即Dv≥Dth)。将注意,如果在执行该过程中达到可调整滞后H的最大值,那么阈值比较电路240将不再尝试执行可调整滞后H的递增增加。" in the original Chinese text. The original text seems a bit muddled in this regard. It might need to be further clarified in the original for a more accurate translation.A block diagram of a portion of the second ASK demodulation circuit 144 is shown. A signal conditioning circuit 300 is coupled to sense the voltage at the intermediate node 146 between the series-connected inductor L and capacitor C of the resonant circuit 16tx. This voltage is high-pass filtered by a DC blocking filter circuit 301. The signal conditioning circuit 300 includes a signal rectification circuit that processes the sensed voltage to generate a rectified voltage signal (V_rect) 302a. A peak-to-peak voltage sensing circuit of the signal conditioning circuit 300 processes the sensed voltage to generate a peak-to-peak voltage signal (V_P2P) 302b. Circuits that process AC voltage signals (such as the sensed and high-pass filtered voltage of the resonant circuit 16tx) to generate a rectified signal and a peak-to-peak signal are well known to those skilled in the art. A switching circuit 304 (e.g., in the form of an analog multiplexer circuit) selects one of the signals V_rect 302a and V_P2P 302b to generate a sensed voltage signal 306. A source selection signal (source_sel) is used to control the signal selection performed by the switching circuit 304. The selected sensed voltage signal 306 is filtered by a bandpass filter circuit 308 to filter out the carrier signal and generate an analog voltage demodulation signal (Vdemod_ana) 310, which retains only the modulation signal (which may be contaminated by in-band noise). The bandpass filter circuit 308 can, for example, include a cascade of a high-pass filter (e.g., a second-order Butterworth filter) and a low-pass filter (e.g., a second-order Butterworth filter). The analog voltage demodulation signal 310 is input to a comparator circuit 312 with an adjustable hysteresis H to generate a digital voltage demodulation signal (Vdemod_dig) 314. Whether for ASK frames or in-band noise, the signal Vdemod_dig 314 can be regarded as a pulse width modulated (PWM) signal. The dashed double-ended arrow schematically illustrates a step-wise change in hysteresis H in response to hysteresis control signal 342 (where comparator circuit 312 is selectively controllable to be set to any one of a plurality of discrete hysteresis values). Control of hysteresis H is performed to substantially (if not completely) eliminate in-band switching noise. The analog voltage demodulated signal 310 and the digital voltage demodulated signal 314 may then be further processed by processing circuitry 320 to generate demodulated information transmitted by receiver 14 of wireless power transfer system 10. For example, processing circuitry 320 may implement signal decoding operations. The output from processing circuitry 320 may be used in conjunction with feedback circuitry 150, which controls the operation of PWM control circuitry 130 and / or other control circuitry of transmitter 12.Additionally, the analog voltage demodulation signal (Vdemod_ana) 310 can be converted by an analog-to-digital converter to provide a digital value in a feedback control loop 350 for generating a source selection (source_sel) signal for selecting between signal V_rect 302a or signal V_P2P 302b (i.e., selecting the best one of signal V_rect 302a or signal V_P2P 302b) for use in signal processing operations. Further, the digital voltage demodulation signal (Vdemod_dig) 314 is detected and decoded to recover the information transmitted by the receiver circuit 14.

[0022] The hysteresis control circuit 330 operates to control the setting of the adjustable hysteresis H of the comparator circuit 312. The hysteresis control circuit 330 includes a digital-to-analog converter (DAC) circuit 332 that converts the output pulses of the digital voltage demodulation signal (Vdemod_dig) 314 into an analog voltage level 334 that indicates the amount of in-band noise present in the ASK modulation signal. As an example, a resistor-capacitor circuit can be used to convert the PWM pulses of the digital voltage demodulation signal (Vdemod_dig) 314 into an analog voltage level 334, the level of which depends on the duty cycle. In the case where there is in-band noise in the signal Vdemod_dig 314, the analog voltage level 334 has a relatively low value. The analog-to-digital converter circuit 336 converts the analog voltage level 334 into a digital value (Dv) 338. The threshold comparison circuit 340 compares the digital value 338 with a digital threshold (Dth). In the case where the digital value 338 is greater than or equal to the digital threshold (i.e., Dv≥Dth), the hysteresis control circuit 330 does not adjust the adjustable hysteresis H of the comparator circuit 312 via the hysteresis control signal 342. However, in the case where the digital value 338 is less than the digital threshold (i.e., Dv<Dth), the hysteresis control circuit 330 incrementally increases the adjustable hysteresis H of the comparator circuit 312 (e.g., by one step value) using the hysteresis control signal 342. This operation is repeated, incrementally increasing the adjustable hysteresis H until the digital value 336 is greater than or equal to the digital threshold (i.e., Dv≥Dth). It will be noted that if the maximum value of the adjustable hysteresis H is reached during this process, the threshold comparison circuit 340 will no longer attempt to perform an incremental increase of the adjustable hysteresis H.

[0023] Now referring to Figure 5A , Figure 5AThe waveforms of the signals (214, 314) at the outputs of the hysteresis comparators 212, 312 are shown, where, when the adjustable hysteresis H is set to a minimum value, in-band switching noise (in-band noise) and ASK modulation information (ASK frame) are simultaneously present at the outputs of the hysteresis comparators 212, 312. One problem with this is that the in-band noise may contaminate the ASK frame, or a decoding operation may be triggered by the in-band noise.

[0024] Figure 5B The waveforms of the signals (214, 314) at the outputs of the hysteresis comparators 212, 312 are shown, wherein the hysteresis control circuits 230, 330 operate to control the setting of the adjustable hysteresis H to a value where the digital value 236, 336 is greater than or equal to the digital threshold value (i.e., Dv≥Dth). It will be noted that in-band switching noise (in-band noise) has been substantially (if not completely) eliminated without adversely affecting the ASK modulated information (ASK frame) (e.g., frame loss).

[0025] For comparison purposes, Figure 5C The waveforms of the signals (214, 314) at the outputs of the hysteresis comparators 212, 312 are shown, where the adjustable hysteresis H has been set to its maximum value. It will be noted that in this case, the in-band switching noise (in-band noise) has been substantially (if not completely) eliminated, but there is a significant adverse effect on the ASK modulated information (ASK frame), thereby showing the corruption of the ASK frame. Therefore, it is critical to control the increment of the value of the adjustable hysteresis H only to a set point where the in-band switching noise (in-band noise) is controlled without losing the fidelity of the ASK modulated information (ASK frame).

[0026] Now refer to Figure 6 , Figure 6Shown is a flowchart illustrating the operation of a hysteresis control circuit for setting an adjustable hysteresis of a hysteresis comparator for controlling an ASK demodulation circuit. This process is performed in the time interval between consecutive ASK frames. After completing the reception of a given ASK frame (reference numeral 400), the trigger (reference numeral 402) of frame completion controls the start (reference numeral 404) of the hysteresis H adjustment process. The value of the adjustable hysteresis H is reset (reference numeral 406) to a minimum value. Then, analog-to-digital converter circuits 236, 336 read and convert (reference numeral 408) the analog voltage levels 234, 334 at the output of digital-to-analog converter circuits 232, 332 to generate digital values (Dv) 238, 338. Then digital values (Dv) 238, 338 are compared (reference numeral 410) with a digital threshold value (Dth). In the event that the digital value (Dv) 238, 338 is less than or equal to the digital threshold value (Dth) (path labeled "Y1"), a test is performed as to whether the current hysteresis value is at a maximum level (reference numeral 412). If not (path labeled "N2"), the current hysteresis value is incremented (reference numeral 414) and the process returns to step 408. Conversely, if a) the digital value (Dv) 238, 338 is greater than the digital threshold value (Dth) via the path labeled "N1", or b) the maximum hysteresis value has been reached via the path labeled "Y2", the process ends (reference numeral 416) and the currently selected (adjusted) hysteresis value is then applied by the hysteresis comparator 212, 312 for the duration between ASK frames. The process as described above is then repeated upon completion of the next and each subsequent ASK frame (reference numeral 418).

[0027] In one embodiment, the subsequent ASK frame (reference numeral 418) may include the next ASK frame that immediately follows the given ASK frame (reference numeral 400) as shown. However, it will be noted that the subsequent ASK frame (reference numeral 418) may alternatively include an ASK frame that does not necessarily immediately follow the given ASK frame (reference numeral 400), in which case the interframe time interval will be between two non-consecutive ASK frames.

[0028] The technical solution presented herein performs closed-loop control of the adjustable hysteresis H of the hysteresis comparators 212 and 312 based on the level characteristics of the signal domain (ASK frame) and the noise domain (in-band switching noise) in the following manner: DAC / ADC operations are performed on the PWM signal pulses output from the hysteresis comparators 212 and 312, followed by comparison with a threshold value selected to correspond to a point where the in-band switching noise is controlled without risk of frame loss of the ASK modulation information (ASK frame). This technical solution has advantages over previous technical solutions for addressing in-band noise pollution: it can operate in real time (as opposed to in an open-loop mode with a fixed hysteresis setting), has high robustness (i.e., dynamically adjusts to noise and operates on a frame-by-frame basis), and has low power consumption.

[0029] Will note that although Figure 6 The preferred implementation of the process is to perform the hysteresis adjustment on a frame-by-frame basis as shown, but other options exist. For example, the hysteresis adjustment process can be performed on a periodic basis (independent of the interval between frames) or on an event-driven basis (not specific to the completion of each ASK frame).

[0030] Although the present invention has been described and illustrated in detail in the drawings and the foregoing description, such illustration and description are to be considered illustrative or exemplary rather than restrictive; the invention is not limited to the disclosed embodiments. Other variations to the disclosed embodiments can be understood and effected by those skilled in the art in practicing the claimed invention, from a study of the drawings, the disclosure, and the appended claims.

Claims

1. A circuit comprising: a comparator having a hysteresis value adjustable in response to a hysteresis setting control signal; wherein the input of the comparator is configured to receive a modulated signal contaminated by in-band noise; a digital-to-analog converter circuit configured to convert a pulse signal output from the comparator into an analog signal; an analog-to-digital converter configured to convert the analog signal into a digital signal value; as well as a comparison circuit configured to compare the digital signal value with a threshold value and, in response to a result of the comparison, generate the hysteresis setting control signal to adjust the hysteresis value of the comparator so as to suppress the in-band noise from the output of the pulse signal output from the comparator.

2. The circuit of claim 1, wherein the modulation signal is derived from an amplitude shift keyed (ASK) information communication signal. 3 . The circuit of claim 2 , wherein the ASK information communication signal is generated by modulating a reflected impedance in a wireless power transfer system. 4 . The circuit of claim 1 , wherein when the digital signal value is less than the threshold value, the hysteresis value of the comparator is incrementally adjusted by one step by the hysteresis setting control signal.

5. The circuit according to claim 1 , further comprising: a current sensing circuit configured to sense current flowing in the bridge circuit and generate a current sensing signal; as well as A bandpass filter circuit is configured to filter the current sensing signal to generate the modulation signal.

6. The circuit of claim 5, wherein the bridge circuit is coupled as a resonant circuit driving a wireless power transmitter.

7. The circuit of claim 1 , further comprising: a voltage sensing circuit configured to sense a voltage in the resonant circuit and generate a voltage sensing signal; as well as A bandpass filter circuit is configured to filter the voltage sensing signal to generate the modulation signal. The circuit of claim 7 , wherein the voltage sensing signal is a rectified voltage signal.

9. The circuit of claim 7, wherein the voltage sensing signal is a peak-to-peak voltage signal.

10. The circuit of claim 7, wherein the resonant circuit is driven by a bridge circuit of a wireless power transmitter.

11. A method comprising: a) in response to completion of a modulation signal frame, resetting hysteresis of an adjustable hysteresis comparator; b) converting the pulse signal output from the adjustable hysteresis comparator into an analog signal; c) converting the analog signal into a digital signal value; d) comparing the digital signal value with a threshold value; e1) if the digital signal value is less than the threshold value, incrementing the hysteresis value of the adjustable hysteresis comparator and returning to step b); and e2) When the digital signal value is not less than the threshold value, utilizing the hysteresis value of the adjustable hysteresis comparator until the next modulation signal frame is completed.

12. The method according to claim 11, wherein step e1 further comprises: Checking whether the hysteresis value of the adjustable hysteresis comparator is at a maximum value, and if so, utilizing the maximum value of the hysteresis value until completion of a next modulated signal frame.

13. The method according to claim 11, wherein the next modulated signal frame is a next modulated signal frame immediately after the modulated signal frame.

14. A wireless power transfer system comprising: Wireless power transmitter; wireless power receiver; wherein the wireless power transmitter and the wireless power receiver are coupled for power transfer from the wireless power transmitter to the wireless power receiver, and are coupled for information transfer from the wireless power receiver to the wireless power transmitter; The wireless power transmitter comprises: circuitry configured to receive a modulated information transmission signal from the wireless power receiver and generate a modulated signal contaminated by in-band noise; a comparator having a hysteresis value adjustable in response to a hysteresis setting control signal; wherein the input of the comparator is configured to receive the modulated signal contaminated by in-band noise; a digital-to-analog converter circuit configured to convert a pulse signal output from the comparator into an analog signal; an analog-to-digital converter configured to convert the analog signal into a digital signal value; and a comparison circuit configured to compare the digital signal value with a threshold value and, in response to a result of the comparison, generate the hysteresis setting control signal to adjust the hysteresis value of the comparator so as to suppress the in-band noise from the output of the pulse signal output from the comparator.

15. The system of claim 14, wherein the modulated information transmission signal is an amplitude shift keyed (ASK) information communication signal.

16. The system of claim 15, wherein the ASK information communication signal is generated by modulating a reflected impedance in the wireless power transfer system. 17 . The system of claim 15 , wherein when the digital signal value is less than the threshold value, the hysteresis value of the comparator is incrementally adjusted by one step by the hysteresis setting control signal.

18. The system of claim 14, wherein the modulated signal contaminated by in-band noise is generated by sensing current flowing in a bridge circuit of the wireless power transmitter configured to drive a resonant circuit.

19. The system of claim 14, wherein the modulated signal contaminated by in-band noise is generated by sensing a voltage in a resonant circuit of the wireless power transmitter driven by a bridge circuit.

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