Method for etching DTC dielectric layer
By using argon to replace boron trichloride during the etching of DTC dielectric layer and reducing biased RF power, the problem of uneven surface after etching is solved, and the reliability and yield of capacitor devices are improved.
Patent Information
- Application Number
- CN202510484319.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-04-16
- Publication Date
- 2025-08-12
AI Technical Summary
The surface flatness of the DTC dielectric layer is poor after etching, resulting in failure of the performance of the capacitor device, especially when the edges of the etching area are weak, which makes it easy to cause metal losses.
Boron trichloride is used as an etching gas auxiliary agent, combined with low bias RF power, and argon is introduced to replace boron trichloride during the third etching process to reduce the bias power to improve etching flatness.
The flatness of the DTC dielectric layer after etching is improved, the reliability and yield of the device are enhanced, metal loss is avoided, and the performance of capacitor devices is improved.
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Abstract
Description
Technical Field
[0001] The present application relates to the technical field of semiconductor devices and integrated circuits, and in particular to an etching method applied to a DTC dielectric layer. Background Art
[0002] Compared to traditional planar capacitors, deep trench capacitors (DTCs) are widely used due to their three-dimensional structure, enabling them to achieve ultra-high capacitance density. Typically, DTCs consist of metal electrodes and high-k dielectric layers (a dielectric with a dielectric constant k greater than 3). By alternately depositing metal and dielectric layers in trenches, they form parallel capacitors through metal interconnects, significantly increasing capacitance density.
[0003] In the DTC etching process, due to the thin thickness of the dielectric layer (usually designed to be 80 angstroms Therefore, the surface flatness of the dielectric layer after etching is poor, and it is difficult to ensure that its overall thickness reaches a safe range (the thickness after etching must be greater than 60 angstroms). In particular, the edge of the etched area is relatively weak. The superposition of the previous layer and the fluctuation of the machine process may even cause the dielectric layer in this area to be completely etched. In severe cases, metal loss may occur, resulting in performance failure of the capacitor device. Summary of the Invention
[0004] The present application provides a method for etching a DTC dielectric layer, which can solve the problem of poor surface flatness of the dielectric layer obtained by etching the DTC dielectric layer provided in the related art. The method comprises:
[0005] A wafer is provided, wherein a first insulating layer is formed on the wafer, a deep trench is formed in the first insulating layer, a DTC multilayer film structure is formed on the first insulating layer and the deep trench, a second insulating layer is formed on the DTC multilayer film structure, the second insulating layer fills the deep trench, and the DTC multilayer film structure includes a metal layer and a dielectric layer overlapping in sequence;
[0006] Covering the second insulating layer with a photoresist, and removing the photoresist in a target area by sequentially performing exposure and development to expose the second insulating layer in the target area;
[0007] Performing a first etching to remove the second insulating layer in the target area;
[0008] Performing a second etching to a predetermined depth in the top metal layer, wherein the gases introduced during the second etching process include chlorine and boron trichloride;
[0009] A third etching is performed until the dielectric layer below the top metal layer is exposed. During the third etching, the content of boron trichloride is reduced and argon gas is introduced. The bias power is reduced as much as possible within the range allowed by the process conditions.
[0010] In some embodiments, the dielectric layer includes an aluminum oxide layer.
[0011] In some embodiments, the metal layer includes a titanium nitride layer.
[0012] In some embodiments, the first insulating layer and the second insulating layer include silicon dioxide layers.
[0013] In some embodiments, during the third etching process, the flow rate of boron trichloride is 25 SCCM to 30 SCCM.
[0014] In some embodiments, during the third etching process, the bias power is 30 watts to 50 watts.
[0015] In some embodiments, during the third etching process, the source power ranges from 400 watts to 600 watts.
[0016] The technical solution of this application has at least the following advantages:
[0017] During the etching process of the DTC dielectric layer, by introducing argon instead of boron trichloride as the main etching auxiliary gas, combined with low bias RF power, the problem of uneven surface after etching of the ultra-thin capacitor dielectric layer can be effectively solved, thereby improving the reliability and yield of the device products. BRIEF DESCRIPTION OF THE DRAWINGS
[0018] In order to more clearly illustrate the specific implementation methods of the present application or the technical solutions in the prior art, the following is a brief introduction to the drawings required for use in the specific implementation methods or the description of the prior art. Obviously, the drawings described below are some implementation methods of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.
[0019] Figure 1 This is a flow chart of a method for etching a DTC dielectric layer provided by an exemplary embodiment of the present application;
[0020] Figures 2 to 4 Schematic diagram of the etching process of the DTC dielectric layer provided by an exemplary embodiment of the present application. DETAILED DESCRIPTION
[0021] The following is a clear and complete description of the technical solutions in this application in conjunction with the accompanying drawings. Obviously, the embodiments described are part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making any creative efforts are within the scope of protection of this application.
[0022] In the description of this application, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicating orientations or positional relationships, are based on the orientations or positional relationships shown in the accompanying drawings and are intended solely to facilitate the description of this application and simplify the description. They do not indicate or imply that the devices or components referred to must have a specific orientation, be constructed, or operate in a specific orientation. Therefore, they should not be construed as limitations on this application. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.
[0023] In the description of this application, it should be noted that, unless otherwise expressly specified or limited, the terms "installed," "connected," and "connected" should be understood in a broad sense. For example, they can refer to fixed connections, detachable connections, or integral connections; they can refer to mechanical connections or electrical connections; they can refer to direct connections or indirect connections through an intermediate medium; they can refer to internal connections between two components; they can refer to wireless connections or wired connections. Those skilled in the art will understand the specific meanings of the above terms in this application based on the specific circumstances.
[0024] In addition, the technical features involved in the different embodiments of the present application described below can be combined with each other as long as they do not conflict with each other.
[0025] refer to Figure 1 , which shows a flow chart of a method for etching a DTC dielectric layer provided by an exemplary embodiment of the present application, as shown in FIG. Figure 1 As shown, the method includes:
[0026] Step S1, providing a wafer, a first insulating layer is formed on the wafer, a deep trench is formed in the first insulating layer, a DTC multilayer film structure is formed on the first insulating layer and the deep trench, a second insulating layer is formed on the DTC multilayer film structure, the second insulating layer fills the deep trench, and the DTC multilayer film structure includes metal layers and dielectric layers overlapping in sequence.
[0027] Step S2 , covering the second insulating layer with a photoresist, and removing the photoresist in the target area by sequentially performing exposure and development to expose the second insulating layer in the target area.
[0028] refer to Figure 2, which shows a cross-sectional schematic diagram of the photoresist after exposure and development. Figure 2 As shown, the chip ( Figure 2 Only a cross-sectional schematic diagram of a part of the area above the chip is shown, and the chip itself and the deep trenches formed in the chip are not shown. The deep trenches are usually trenches with a depth-to-width ratio greater than 6. A first insulating layer 210 is formed on the chip, and deep trenches are formed in the first insulating layer 210. A DTC multilayer film structure is formed on the first insulating layer 210 and the deep trenches. A second insulating layer 230 is formed on the DTC multilayer film structure, and the second insulating layer 230 fills the deep trenches. The DTC multilayer film structure includes a metal layer 221 and a dielectric layer 222 that overlap in sequence. A photoresist 300 can be covered on the second insulating layer 230. The photoresist in the target area is removed by exposure and development in sequence to expose the second insulating layer 230 in the target area.
[0029] The dielectric layer 222 includes an aluminum oxide (Al 2 O 3 ) layer, the metal layer 221 includes a titanium nitride (TiN) layer, and the first insulating layer 210 and the second insulating layer 230 include silicon dioxide (SiO 2 ) layers.
[0030] Step S3: performing a first etching to remove the second insulating layer in the target area.
[0031] Exemplarily, during the first etching process, the gases introduced include carbon tetrafluoride (CF4) and oxygen (O2), with a flow rate of carbon tetrafluoride of 50 standard cubic centimeter per minute (SCCM) to 100 SCCM, and a flow rate of oxygen of 10 SCCM to 15 SCCM, at a relatively high source radio frequency power (1000 watts (W) to 1200 watts) to ensure sufficient over etch.
[0032] Step S4 , performing a second etching to a predetermined depth in the top metal layer. The gases introduced during the second etching process include chlorine and boron trichloride.
[0033] refer to Figure 3 , which shows a cross-sectional schematic diagram after the second etching. Figure 3 As shown, the gases introduced during the second etching process include chlorine (Cl2) and boron trichloride (BCl3), the flow rate of chlorine is 20SCCM to 30SCCM, and the flow rate of boron trichloride is 100SCCM to 130SCCM. The source RF power in the second etching is the same as the source RF power in the first etching, and the etching is carried out to a predetermined depth in the top metal layer (the topmost metal layer of the DTC multilayer film).
[0034] Step S5 , performing a third etching until the dielectric layer below the top metal layer is exposed. During the third etching process, the content of boron trichloride is reduced and argon gas is introduced. The bias power is reduced as much as possible within the range allowed by the process conditions.
[0035] refer to Figure 4 , which shows a cross-sectional schematic diagram after the third etching. Figure 4 As shown, during the third etching process, the content of boron trichloride is reduced and argon (Ar) is introduced, the flow rate of boron trichloride is reduced to 25 SCCM to 30 SCCM, the bias power is 30 watts to 50 watts, the source power range is 400 watts to 600 watts, and BCL 3+ and Ar + The force of the downward bombardment is weakened to a lower level.
[0036] Due to the high density of argon and its fast settling speed, the undissociated argon can quickly settle and coat the surface of the dielectric film, providing timely and effective protection for the capacitor dielectric layer. In addition, because argon is an inert gas, it will not react chemically with aluminum oxide. Although it is in close contact with the dielectric layer, it will not have any etching effect, thereby ensuring the flatness of the etching. The reaction formula involved in this process is:
[0037] BCl3→BCL 3+
[0038] BCl x +Cl2→BCl x+1 (side wall deposition), x is a natural number
[0039] BCL3+Al2O3→AlCl3+B2O3
[0040] Ar→Ar(surface deposition)+Ar +
[0041] To sum up, in the embodiment of the present application, during the etching process of the DTC dielectric layer, by introducing argon gas instead of boron trichloride as the main etching auxiliary gas, combined with a low bias RF power, the problem of uneven surface after etching of the ultra-thin capacitor dielectric layer can be effectively solved, thereby improving the reliability and yield of the device product.
[0042] Obviously, the above embodiments are merely examples for clarity of explanation and are not intended to limit the implementation methods. Those skilled in the art will appreciate that other variations or modifications can be made based on the above description. It is not necessary and impossible to enumerate all implementation methods here. Obvious variations or modifications arising therefrom remain within the scope of protection of this application.
Claims
1. A method for etching a DTC dielectric layer, characterized in that: include: A wafer is provided, wherein a first insulating layer is formed on the wafer, a deep trench is formed in the first insulating layer, a DTC multilayer film structure is formed on the first insulating layer and the deep trench, a second insulating layer is formed on the DTC multilayer film structure, the second insulating layer fills the deep trench, and the DTC multilayer film structure includes a metal layer and a dielectric layer overlapping in sequence; Covering the second insulating layer with a photoresist, and removing the photoresist in a target area by sequentially performing exposure and development to expose the second insulating layer in the target area; Performing a first etching to remove the second insulating layer in the target area; Performing a second etching to a predetermined depth in the top metal layer, wherein the gases introduced during the second etching process include chlorine and boron trichloride; A third etching is performed until the dielectric layer below the top metal layer is exposed. During the third etching, the content of boron trichloride is reduced and argon gas is introduced. The bias power is reduced as much as possible within the range allowed by the process conditions.
2. The method according to claim 1, characterized in that The dielectric layer includes an aluminum oxide layer.
3. The method according to claim 2, characterized in that The metal layer includes a titanium nitride layer.
4. The method according to claim 3, characterized in that The first insulating layer and the second insulating layer include silicon dioxide layers.
5. The method according to any one of claims 1 to 4, characterized in that: During the third etching process, the flow rate of boron trichloride is 25 SCCM to 30 SCCM.
6. The method according to claim 5, characterized in that During the third etching process, the bias power is 30 watts to 50 watts.
7. The method according to claim 6, characterized in that During the third etching process, the source power ranges from 400 watts to 600 watts.