Method for improving morphology of gate oxide layer

Abstract

The invention provides a method for improving the morphology of a gate oxide layer, and the method comprises the steps: providing a semiconductor structure which comprises a substrate, a groove formed in the substrate, and a field oxide layer which is formed at the bottom and the side wall of the groove and extends to the surface of the substrate, and the field oxide layer is of an ONO stacked structure and comprises a bottom oxide layer, a middle nitride layer and a top oxide layer from the bottom to the top; forming a source polycrystalline silicon layer in the groove, wherein the thickness of the source polycrystalline silicon layer is smaller than the depth of the groove; etching to remove the exposed partial thickness top oxide layer above the source polycrystalline silicon layer; forming a tunneling oxide layer in the groove, wherein the sum of the thickness of the tunneling oxide layer and the thickness of the polycrystalline silicon layer is smaller than the depth of the groove; step-by-step etching is carried out to remove the exposed top oxide layer with the residual thickness above the tunneling oxide layer and the middle nitride layer and the bottom oxide layer below the top oxide layer; and forming a gate oxide layer on the surface of the tunneling oxide layer and the side wall of the groove. According to the invention, the problem that the morphology of the gate oxide layer formed by the existing method has defects is solved.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor manufacturing, in particular to a method for improving the morphology of a gate oxide layer. Background Art

[0002] SGT (Shielded Gate Transistor) MOSFET is mainly used in medium and low voltage fields. In some SGT processes, a thicker ONO layer (about ) as field oxygen to improve the voltage resistance level.

[0003] When removing the ONO layer and regenerating the gate oxide layer, it is necessary to remove the field oxide near the top of the trench in three steps of wet etching. In this process, the wet etching time is limited. This is because if the etching time is too short (less than 8 minutes), the field oxide at the top cannot be completely removed, resulting in the subsequent gate oxide layer having a stepped morphology (such as Figure 1 As shown), it cannot meet the mass production requirements; if the etching time is long (more than 9 minutes), the thickness of the tunnel oxide layer formed on the surface of the polysilicon layer will be too thin (less than ), which in turn causes the IGSS parameters of the device to fail. Summary of the Invention

[0004] In view of the above-mentioned shortcomings of the prior art, an object of the present invention is to provide a method for improving the morphology of a gate oxide layer, so as to solve the problem that the morphology of a gate oxide layer formed by the prior art has defects.

[0005] To achieve the above-mentioned and other related purposes, the present invention provides a method for improving the morphology of a gate oxide layer, the method comprising:

[0006] A semiconductor structure is provided, comprising a substrate, a trench formed in the substrate, and a field oxide layer formed at the bottom and sidewalls of the trench and extending to the surface of the substrate, wherein the field oxide layer is an ONO stacked structure, comprising, from bottom to top, a bottom oxide layer, a middle nitride layer, and a top oxide layer;

[0007] forming a source polysilicon layer in the trench, wherein the thickness of the source polysilicon layer is smaller than the depth of the trench;

[0008] Etching and removing a portion of the top oxide layer exposed above the source polysilicon layer;

[0009] forming a tunnel oxide layer in the trench, wherein the sum of the thickness of the tunnel oxide layer and the polysilicon layer is less than the depth of the trench;

[0010] Step-by-step etching to remove the top oxide layer with the remaining thickness exposed above the tunnel oxide layer and the middle nitride layer and the bottom oxide layer thereunder;

[0011] A gate oxide layer is formed on the surface of the tunnel oxide layer and the sidewall of the trench.

[0012] Optionally, the thickness of the bottom oxide layer includes The thickness of the intermediate nitride layer includes The thickness of the top oxide layer includes

[0013] Optionally, the thickness of the bottom oxide layer is The thickness of the intermediate nitride layer is The thickness of the top oxide layer is

[0014] Optionally, a wet etching process is used to remove a portion of the top oxide layer.

[0015] Optionally, the thickness of the removed top oxide layer is

[0016] Optionally, the remaining thickness of the top oxide layer, the middle nitride layer and the bottom oxide layer are removed by wet method.

[0017] Optionally, the top oxide layer and the bottom oxide layer are made of silicon oxide; and the middle nitride layer is made of silicon nitride.

[0018] Optionally, the thickness of the tunnel oxide layer is

[0019] Optionally, the top oxide layer is formed by a sub-atmospheric pressure chemical vapor deposition process.

[0020] Optionally, a thermal oxidation process is used to form the bottom oxide layer, the tunnel oxide layer and the gate oxide layer.

[0021] Optionally, the method further includes the step of forming a gate polysilicon layer in the trench, and the gate polysilicon layer is formed on the surface of the gate oxide layer.

[0022] As described above, the method for improving the gate oxide layer morphology of the present invention adds a wet etching process before the tunnel oxide layer is formed, and pre-cleans the gate oxide layer. The top oxide layer of about 1000 nm is formed, thereby shortening the etching time of the remaining thickness of the top oxide layer after the tunnel oxide layer is formed. The above approach can reduce the etching of the tunnel oxide layer during the removal process of the ONO stacked structure, ensuring that the thickness of the tunnel oxide layer meets the requirements (about 1000 nm). ), and can improve the morphology of the gate oxide layer while ensuring the IGSS parameters. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 An electron microscope image of a semiconductor structure showing a conventionally formed stepped gate oxide layer.

[0024] Figure 2 The figure shows a schematic cross-sectional structure of a semiconductor structure having trenches formed therein.

[0025] Figure 3 It is a schematic cross-sectional structural diagram of the semiconductor structure after forming a source polysilicon layer.

[0026] Figure 4 The diagram shows a cross-sectional structure of a semiconductor structure after a portion of the top oxide layer is removed.

[0027] Figure 5 Shown is a schematic cross-sectional structure diagram of a semiconductor structure after a tunnel oxide layer is formed.

[0028] Figure 6 It shows a schematic cross-sectional structure diagram of the semiconductor structure after removing the ONO stacked structure.

[0029] Figure 7 It is a schematic cross-sectional view of the semiconductor structure after the gate oxide layer is formed.

[0030] Figure 8 It is a schematic cross-sectional structural diagram of the semiconductor structure after the gate polysilicon layer is formed.

[0031] Figure 9 Shown is a flow chart of the method for improving gate oxide layer morphology according to the present invention. DETAILED DESCRIPTION

[0032] The following describes the embodiments of the present invention through specific examples. Those skilled in the art will readily understand the other advantages and benefits of the present invention from the disclosure herein. The present invention may also be implemented or applied through various other specific embodiments, and the details in this specification may be modified or altered based on different viewpoints and applications without departing from the spirit of the present invention.

[0033] See also Figures 1 to 9 It should be noted that the illustrations provided in this embodiment are merely schematic illustrations of the basic concept of the present invention. Although the illustrations only show components related to the present invention and are not drawn according to the number, shape, and size of components in actual implementation, the form, quantity, and proportion of each component in actual implementation may be arbitrarily changed, and the component layout may also be more complex.

[0034] like Figure 9 As shown, this embodiment provides a method for improving the morphology of a gate oxide layer, the method comprising:

[0035] A semiconductor structure is provided, comprising a substrate, a trench formed in the substrate, and a field oxide layer formed at the bottom and sidewalls of the trench and extending to the surface of the substrate, wherein the field oxide layer is an ONO stacked structure, comprising, from bottom to top, a bottom oxide layer, a middle nitride layer, and a top oxide layer;

[0036] forming a source polysilicon layer in the trench, wherein the thickness of the source polysilicon layer is smaller than the depth of the trench;

[0037] Etching and removing a portion of the top oxide layer exposed above the source polysilicon layer;

[0038] forming a tunnel oxide layer in the trench, wherein the sum of the thickness of the tunnel oxide layer and the polysilicon layer is less than the depth of the trench;

[0039] Step-by-step etching to remove the top oxide layer with the remaining thickness exposed above the tunnel oxide layer and the middle nitride layer and the bottom oxide layer thereunder;

[0040] A gate oxide layer is formed on the surface of the tunnel oxide layer and the sidewall of the trench.

[0041] Specifically, the thickness of the bottom oxide layer includes The thickness of the intermediate nitride layer includes The thickness of the top oxide layer includes

[0042] More specifically, the thickness of the bottom oxide layer is The thickness of the intermediate nitride layer is The thickness of the top oxide layer is

[0043] Specifically, the top oxide layer and the bottom oxide layer are made of silicon oxide; and the middle nitride layer is made of silicon nitride.

[0044] Specifically, the top oxide layer is formed by a sub-atmospheric pressure chemical vapor deposition process.

[0045] Specifically, the bottom oxide layer, the tunnel oxide layer and the gate oxide layer are formed by a thermal oxidation process.

[0046] Specifically, a wet etching process is used to remove a portion of the top oxide layer.

[0047] More specifically, the thickness of the top oxide layer removed is like Figure 4As shown, in this embodiment, the thickness of the top oxide layer removed by wet method is

[0048] Specifically, the thickness of the tunnel oxide layer is like Figure 5 As shown, in this embodiment, the thickness of the tunnel oxide layer is

[0049] Specifically, the remaining thickness of the top oxide layer, the middle nitride layer and the bottom oxide layer are removed by wet method.

[0050] In this embodiment, when the remaining thickness of the top oxide layer is removed by wet etching, the time taken is 8 minutes and 10 seconds.

[0051] Specifically, the method further includes the step of forming a gate polysilicon layer in the trench, and the gate polysilicon layer is formed on the surface of the gate oxide layer.

[0052] In summary, the method for improving the gate oxide layer morphology of the present invention adds a wet etching process before the tunnel oxide layer is formed, and pre-cleansing The top oxide layer of about 1000 nm is formed, thereby shortening the etching time of the remaining thickness of the top oxide layer after the tunnel oxide layer is formed. The above approach can reduce the etching of the tunnel oxide layer during the removal process of the ONO stacked structure, ensuring that the thickness of the tunnel oxide layer meets the requirements (about 1000 nm). ), and can improve the morphology of the gate oxide layer while ensuring the IGSS parameters. Therefore, the present invention effectively overcomes the various shortcomings of the prior art and has high industrial utilization value.

[0053] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the present invention. Anyone skilled in the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by one of ordinary skill in the art without departing from the spirit and technical principles disclosed herein are intended to be covered by the claims of the present invention.

Claims

1. A method for improving gate oxide layer morphology, characterized in that: The method comprises: A semiconductor structure is provided, comprising a substrate, a trench formed in the substrate, and a field oxide layer formed at the bottom and sidewalls of the trench and extending to the surface of the substrate, wherein the field oxide layer is an ONO stacked structure, comprising, from bottom to top, a bottom oxide layer, a middle nitride layer, and a top oxide layer; forming a source polysilicon layer in the trench, wherein the thickness of the source polysilicon layer is smaller than the depth of the trench; Etching and removing a portion of the top oxide layer exposed above the source polysilicon layer; forming a tunnel oxide layer in the trench, wherein the sum of the thickness of the tunnel oxide layer and the polysilicon layer is less than the depth of the trench; Step-by-step etching to remove the top oxide layer with the remaining thickness exposed above the tunnel oxide layer and the middle nitride layer and the bottom oxide layer thereunder; A gate oxide layer is formed on the surface of the tunnel oxide layer and the sidewall of the trench.

2. The method for improving gate oxide layer morphology according to claim 1, wherein: The thickness of the bottom oxide layer includes The thickness of the intermediate nitride layer includes The thickness of the top oxide layer includes 3. The method for improving gate oxide layer morphology according to claim 2, wherein: The thickness of the bottom oxide layer is The thickness of the intermediate nitride layer is The thickness of the top oxide layer is 4. The method for improving gate oxide layer morphology according to claim 2, wherein: A wet etching process is used to remove a portion of the top oxide layer.

5. The method for improving gate oxide layer morphology according to claim 4, wherein: The thickness of the removed top oxide layer is 6. The method for improving gate oxide layer morphology according to claim 1, wherein: The remaining thickness of the top oxide layer, the middle nitride layer and the bottom oxide layer are removed by wet method.

7. The method for improving gate oxide layer morphology according to claim 1, wherein: The top oxide layer and the bottom oxide layer are made of silicon oxide; the middle nitride layer is made of silicon nitride.

8. The method for improving gate oxide layer morphology according to claim 1, wherein: The thickness of the tunnel oxide layer is 9. The method for improving gate oxide layer morphology according to claim 1, wherein: The top oxide layer is formed by a sub-atmospheric pressure chemical vapor deposition process.

10. The method for improving gate oxide layer morphology according to claim 1, wherein: The bottom oxide layer, the tunnel oxide layer and the gate oxide layer are formed by a thermal oxidation process.

11. The method for improving gate oxide layer morphology according to claim 1, wherein: The method further comprises the step of forming a gate polysilicon layer in the trench, and the gate polysilicon layer is formed on the surface of the gate oxide layer.

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