Anti-interference protection circuit for power semiconductor switch test

Abstract

An anti-interference protection circuit for a power semiconductor switch test comprises a differential sampling module, a turn-off module and a window threshold judgment module, and an output signal of the differential sampling module enters a window left input end of the window threshold judgment module after being delayed by a delay module. The output signal of the differential sampling module further enters the window right input end of the window threshold value judgment module, the output end of the window threshold value judgment module is connected with the input end of the turn-off module, and when it is detected that the left side signal and the right side signal of the window are both larger than threshold voltage, the window threshold value judgment module outputs a turn-off signal. The differential sampling module collects a voltage signal, generates a time window reference through a time delay circuit composed of a voltage follower, obtains an initial sampling value and a time delay sampling value respectively, and synchronously compares the two paths of sampling signals with a preset threshold voltage through threshold judgment to decide whether to cut off or not. According to the invention, the interference of current peak in the power semiconductor switch test is prevented, and the original function of the overcurrent protection circuit is reserved.

Description

Technical Field

[0001] The present invention belongs to the field of integrated circuits, and in particular relates to an anti-interference protection circuit for testing power semiconductor switches. Background Art

[0002] During the development of power semiconductors, device switching testing is an essential step. Because power devices can quickly deteriorate under high currents, adding an overcurrent protection circuit to the test loop is particularly important. However, due to reverse recovery issues with components like diodes during testing, high current spikes can cause the overcurrent protection circuit to trip unexpectedly. Therefore, it's necessary to incorporate a false-touch feature into the overcurrent protection circuit to eliminate interference from current spikes.

[0003] Traditional strategies for addressing spike interference, such as patent CN113067565A (An Anti-interference Short-Circuit Protection Circuit with Adjustable Blanking Time for SiC MOSFETs), published on March 12, 2024, employ a digital blanking solution to achieve anti-interference design. However, because this solution requires combining digital and analog circuits, its structure is complex and the design is relatively redundant. Another example is patent CN114123099A (GaN HEMT Device Overcurrent Protection Circuit), published on December 5, 2023, which employs an RC delay solution to achieve anti-interference. However, this solution is subject to the physical limitations of capacitors and resistors, resulting in excessive delay times, which can damage the device under test by the time the circuit is shut down. Generally speaking, the short-circuit current tolerance of power semiconductor devices is generally 300ns to 500ns, while the RC delay scheme requires more than 10us from judgment to shutdown. The digital blanking structure is complex and also has the problem of long delay. The shutdown delay is difficult to exceed 1us. When high current actually occurs, the overcurrent protection circuit cannot be shut down in time due to the delay in false touch detection, resulting in device damage. Summary of the Invention

[0004] In response to the problems existing in the prior art, the present invention provides an anti-interference protection circuit for power semiconductor switch testing, which prevents the interference of current spikes in power semiconductor switch testing, while fully retaining the original function of the overcurrent protection circuit and shutting down the circuit in time when the circuit is in an overcurrent state.

[0005] The present invention adopts the following technical solutions: An anti-interference protection circuit for testing a power semiconductor switch includes a differential sampling module and a shutdown module, and is characterized in that it also includes a window threshold judgment module. The output signal of the differential sampling module enters the left window input end of the window threshold judgment module after being delayed by a delay module. The output signal of the differential sampling module also enters the right window input end of the window threshold judgment module. The output end of the window threshold judgment module is connected to the input end of the shutdown module. When it is detected that the signals on the left and right sides of the window are both greater than the threshold voltage, the window threshold judgment module outputs a shutdown signal.

[0006] Furthermore, when the peak width of the peak current signal passing through the test loop is greater than the set window delay width, the window threshold judgment module outputs a shutdown signal.

[0007] Furthermore, the delay module includes a second operational amplifier U2, the inverting input terminal of the second operational amplifier U2 is connected to the output terminal of the differential sampling module; the non-inverting input terminal and the output terminal of the second operational amplifier U2 are short-circuited and connected to the window left input terminal of the window threshold judgment module.

[0008] Furthermore, the window threshold determination module includes a third operational amplifier U3, a fourth operational amplifier U4, a sixth resistor R6, a first DC voltage source V1, a second DC voltage source V2 and a third DC voltage source V3. The non-inverting input terminal of the third operational amplifier U3 serves as the window left input terminal of the window threshold judgment module, the inverting input terminal of the third operational amplifier U3 is connected to the positive electrode of the first DC voltage source V1, and the negative electrode of the first DC voltage source V1 is grounded; The non-inverting input terminal of the fourth operational amplifier U4 serves as the window right input terminal of the window threshold judgment module, the inverting input terminal of the fourth operational amplifier U4 is connected to the positive electrode of the second DC voltage source V2, and the negative electrode of the second DC voltage source V2 is grounded; One end of the sixth resistor R6 is connected to the output ends of the third operational amplifier U3 and the fourth operational amplifier U4 and serves as the output end of the window threshold judgment module. The other end of the sixth resistor R6 is connected to the positive electrode of the third DC voltage source V3, and the negative electrode of the third DC voltage source V3 is grounded.

[0009] Furthermore, the differential sampling module includes a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a fifth resistor R5, a first inductor L1, a second inductor L2 and a first operational amplifier U1. One end of the first inductor L1 is connected to one end of the first resistor R1 and is used to connect to the transistor under test of the transistor double pulse test circuit, and the other end is connected to one end of the second resistor R2, and the other end of the second resistor R2 is connected to the non-inverting input terminal of the first operational amplifier U1; the fourth resistor R4 is connected between the non-inverting input terminal and the output terminal of the first operational amplifier U1; One end of the second inductor L2 is connected to the other end of the first resistor R1 and is used to connect to the ground end of the transistor double pulse test circuit, and the other end is connected to one end of the third resistor R3, and the other end of the third resistor R3 is connected to the inverting input end of the first operational amplifier U1. The two ends of the fifth resistor R5 are respectively connected to the inverting input end of the first operational amplifier U1 and the ground potential.

[0010] Furthermore, the shutdown module includes a fifth operational amplifier U5, a seventh resistor R7, an eighth resistor R8, a ninth resistor R9, a first IGBTQ1, a second IGBTQ2 and a third IGBTQ3, wherein the inverting input terminal of the fifth operational amplifier U5 serves as the input terminal of the shutdown module; one end of the seventh resistor R7 is grounded, and the other end and one end of the eighth resistor R8 are connected to the non-inverting input terminal of the fifth operational amplifier U5; the other end of the eighth resistor R8 is connected to the output terminal of the fifth operational amplifier U5; one end of the ninth resistor R9 is connected to the output terminal of the fifth operational amplifier U5, and the other end is connected to the gates of the first IGBT, the second IGBT and the third IGBT; the source and drain of the first IGBTQ1, the second IGBTQ2 and the third IGBTQ3 are respectively connected and used to be connected in series in the transistor double pulse test circuit to form a three-parallel shutdown structure.

[0011] Compared with the prior art, the present invention has the following beneficial effects: When a current spike occurs during a switch test, the present invention uses a window rapid detection blanking method to select operational amplifiers of different bandwidths in the delay circuit to set the required window width. When the voltage on the left side of the window is detected to exceed the threshold voltage, the voltage on the right side of the window is rapidly detected to see if it exceeds the threshold voltage. If not, the double-pulse test circuit operates normally, thereby suppressing the interference of the current spike in the test circuit. Without affecting the test method and test circuit of the switch test and without introducing additional delays and additional control signals, the present invention can effectively suppress the phenomenon of the current spike formed by the reverse recovery of the freewheeling diode in the double-pulse test from falsely triggering the overcurrent protection circuit, thereby preventing the test circuit from frequently erroneously shutting down during the test. From the overall structure of the circuit implementation, only the delay circuit and the comparison circuit need to be designed to achieve the above-mentioned invention purpose, which is easy to implement and low in cost. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 Schematic diagram of the window blanking protection circuit structure for power semiconductor switch testing in an example of the present invention; Figure 2 This is a working timing diagram of the window blanking protection circuit for testing a power semiconductor switch in an example of the present invention; Figure 3 This is a simulation circuit diagram of a power semiconductor double pulse test with an anti-interference circuit added in an embodiment of the present invention; Figure 4 A waveform comparison of current spike detection using traditional methods and window blanking in power semiconductor switch testing. Figure 5 The following is a waveform comparison of overcurrent detection using the traditional solution and window blanking in power semiconductor switch testing. DETAILED DESCRIPTION

[0013] In order to better understand the purpose, structure and function of the present invention, the anti-interference protection circuit for testing a power semiconductor switch of the present invention is further described in detail below with reference to the accompanying drawings.

[0014] like Figure 1 As shown, an anti-interference protection circuit for power semiconductor switch testing is characterized by comprising: Differential sampling module, delay module, threshold judgment module, and shutdown module.

[0015] The differential sampling module includes a first test resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a fifth resistor R5, a first inductor L1, a second inductor L2, and a first operational amplifier U1. The first test resistor R1 is connected between the test transistor and ground; one end of the first inductor L1 is connected to the test tube terminal of the first resistor R1, and the other end is connected to one end of the second resistor R2; one end of the second inductor L2 is connected to the ground terminal of the first resistor R1, and the other end is connected to one end of the third resistor R3; the other end of the second resistor R2 is connected to the non-inverting input terminal of the first operational amplifier U1; the other end of the third resistor R3 is connected to the inverting input terminal of the first operational amplifier U1; the fourth resistor R4 is connected between the non-inverting input terminal and the output terminal of the first operational amplifier U1; and the fifth resistor R5 is connected between the inverting input terminal of the first operational amplifier U1 and the ground potential.

[0016] The delay module includes a second operational amplifier U2. The inverting input of the second operational amplifier U2 is connected to the output of the first operational amplifier U1; the non-inverting input and output of the second operational amplifier U2 are short-circuited; and the output of the second operational amplifier U2 is connected to the non-inverting input of the third operational amplifier U3.

[0017] The threshold determination module includes a third operational amplifier U3, a fourth operational amplifier U4, a sixth resistor R6, a first DC voltage source V1, a second DC voltage source V2, and a third DC voltage source V3. The inverting input terminal of the third operational amplifier U3 is connected to the positive electrode of the first DC voltage source V1, and the negative electrode of the first DC voltage source V1 is grounded; The non-inverting input terminal of the fourth operational amplifier U4 is connected to the output terminal of the first operational amplifier U1; the inverting input terminal of the fourth operational amplifier U4 is connected to the positive electrode of the second DC voltage source V2, and the negative electrode of the second DC voltage source V2 is grounded; one end of the sixth resistor R6 is connected to the output terminals of the third operational amplifier U3 and the fourth operational amplifier U4, and the other end is connected to the positive electrode of the third DC voltage source V3, and the negative electrode of the third DC voltage source V3 is grounded.

[0018] The shutdown module includes a fifth operational amplifier U5, a seventh resistor R7, an eighth resistor R8, a ninth resistor R9, a first IGBT Q1, a second IGBT Q2, and a third IGBT Q3. The inverting input of the fifth operational amplifier U5 is connected to the output of the third operational amplifier U3. One end of the seventh resistor R7 is grounded, and the other end and one end of the eighth resistor R8 are connected to the non-inverting input of the fifth operational amplifier U5. The other end of the eighth resistor R8 is connected to the output of the fifth operational amplifier U5. One end of the ninth resistor R9 is connected to the output of the fifth operational amplifier U5, and the other end is connected to the gates of the first, second, and third IGBTs. The source and drain of the first IGBT Q1 are connected in series in the main test circuit. The sources of the second IGBT Q2 and the third IGBT Q3 are connected to the source of the first IGBT Q1, and their drains are connected to the drain of the first IGBT Q1, forming a three-parallel shutdown structure.

[0019] In one embodiment of the present invention, the differential sampling circuit is configured to utilize a dual-inductor common-mode filtering topology in conjunction with a differential amplifier network. The right-side window signal is fed through a delay module to generate a controllably delayed DC current, while the left-side window signal is directly connected to a high-speed comparison unit to generate a real-time trigger DC current. A threshold determination module, cascaded with the differential sampling module, is configured to fuse the dual trigger signals through wired-AND logic and generate a shutdown command based on the threshold comparison result. The shutdown module, utilizing a parallel IGBT array and an isolated drive architecture, responds to protection commands to implement multiple latches in the test circuit.

[0020] In one embodiment of the present invention, the input of the shutdown circuit includes a delayed voltage signal V1 on the left side of the window and a real-time voltage signal V2 on the right side of the window. The two signals are input into the shutdown array after logical processing.

[0021] In one embodiment of the present invention, the delay time of the delayed voltage signal can be changed by selecting the bandwidth of the operational amplifier U2 constituting the voltage follower. The delay time can be .

[0022] In one embodiment of the present invention, when it is detected that the signal on the left side of the window is greater than the threshold voltage, the signal on the right side of the window is detected. If the signal on the right side of the window is also greater than the threshold voltage, the isolated driver sends a shutdown signal to shut down the main circuit, wherein the threshold voltage range is 2-3V, generally set to 2.7V.

[0023] In one embodiment of the present invention, when the test loop passes through a narrow spike current signal, the spike width is less than the set window delay width, and the protection circuit does not shut down, thereby realizing anti-interference design; when the test loop passes through a wide spike current signal, the spike width is greater than the set window delay width, and the protection circuit shuts down; when the test loop is in a continuous overcurrent state, after judging the window time width, the protection circuit is immediately shut down to realize overcurrent protection, wherein the window delay width of the delay circuit can be adjusted by selecting different operational amplifiers, and the adjustment range is between 20ns and 300ns. In power semiconductor switch testing, 300ns is generally taken, and a current spike with a time width less than the delay width is defined as a narrow spike, and a current spike with a time width greater than the delay width is defined as a wide spike.

[0024] Figure 2 This is a working timing diagram of the window blanking protection circuit for power semiconductor switch testing in an embodiment of the present invention. Figure 2 The working principle of this embodiment is described as follows: The window blanking protection circuit for power semiconductor switch testing samples the current signal through a sampling circuit. The collected signal is shown in the original waveform. Since the sampling circuit uses a high-speed op amp, there is almost no delay difference between the input signal on the right side of the window and the original waveform. However, the signal on the left side of the window, which is delayed by the voltage follower, has a transmission delay difference of the voltage follower compared to the original waveform, which is usually in the nanosecond level. Set Va as the threshold voltage, and observe the right side of the window when the threshold voltage is triggered on the left side of the window: At time t0, the voltage signal on the left side of the window reaches the threshold voltage Va. At this time, the signal on the right side of the window is detected. At this time, the signal on the right side of the window is lower than the threshold voltage Va, indicating that the triggered signal is a narrow current spike pulse, which is regarded as an interference signal and the output remains unchanged.

[0025] At time t1, the voltage signal on the left side of the window reaches the threshold voltage Va. At this time, the signal on the right side of the window is detected. At this time, the signal on the right side of the window is higher than the threshold voltage Va. The triggered signal is a current spike pulse wider than the dangerous tolerance value of the power device. At time t2, it is also found that the voltage signal on the left side of the window reaches the threshold voltage Va. At this time, the signal on the right side of the window is detected. At this time, the signal on the right side of the window is higher than the threshold voltage Va. At this time, the power device enters the overcurrent working state. In both cases, the device is at risk of damage and needs to be protected by overcurrent. The shutdown circuit is shut down for shutdown protection.

[0026] In order to compare the anti-narrow pulse interference effect of the present invention in the power semiconductor switch test, this embodiment builds a simulation circuit model based on LTspice software. The simulation circuit structure diagram is as follows: Figure 3 As shown. Among them, the power tube Q4 and Q5 models adopt the GS66508T model provided by GaNSyStem, the diode D1 in the main circuit adopts the 1N4148 model, the auxiliary transistors Q1, Q2, and Q3 adopt the GS61008P model, the capacitor C1 is 470uF, and C2 is 10uF. Compared with the traditional circuit without crosstalk suppression, the load inductor L3 of the simulation circuit model of this embodiment is 0.3mH, the load resistor R1 is 0.1Ω, and the DC input voltage VDC is 400V. The driving resistor R10 is 5Ω, the resistors R2, R3, R4, and R5 in the crosstalk suppression circuit are 10kΩ, the resistor R6 is 1kΩ, the resistor R7 is 100Ω, and the resistor R8 is 1kΩ. The DC input voltages V1 and V2 are 2.6V, and the DC input voltage V3 is 5V. Setting the shutdown array to three IGBTs in parallel will result in better performance at high currents. Based on this simulation circuit model, the waveforms of narrow current spikes and overcurrent signals are compared.

[0027] Figure 4 The following waveforms compare current spike detection using a traditional solution and window blanking in power semiconductor switch testing. The current spike is widened by adjusting the parallel capacitance of the reverse freewheeling diode, setting the current spike width to 300ns. At time t0, the narrow current spike exceeds the Va current threshold, and both the window blanking and traditional solutions enter judgment mode. At time t1, the window blanking circuit has a short window time (typically set on the order of 150ns). Therefore, when the window blanking circuit detects a wide pulse at time t1, it immediately shuts down. Traditional solutions, however, must make a judgment at the end of the delay. If the device is intact at this time, it will not be detected and judged until after the delay at t2. By then, the device has already experienced the wide current spike, which can lead to loss of life or even damage.

[0028] Figure 5 The waveform comparison diagram of overcurrent detection using the traditional solution and window blanking in the power semiconductor switch test. At t0, the current of the device under test has exceeded the Va current threshold, and both the window blanking and the traditional solution enter the judgment mode. At t1, the window blanking circuit has a short window time, generally set at the order of 150ns. Therefore, at t1, the window blanking circuit detects a wide pulse and immediately shuts down. The traditional solution must make a judgment at the end of the delay. At t2, the traditional solution will perform a second test after the delay ends. At this time, the device has been under overcurrent for a long time, and it is very easy to lose life or even be damaged. Therefore, Figure 4 and Figure 5It can be seen that the delay scheme used in the traditional solution has very poor detection sensitivity for narrow pulses and overcurrent conditions, which is far lower than that of the window blanking circuit. Therefore, the window blanking protection circuit tested using power semiconductor switches can increase resistance to current spike pulses while achieving a faster overcurrent protection response speed.

[0029] This patent focuses on optimizing the power semiconductor switch test system's resistance to current spike interference while optimizing the circuit's overcurrent protection efficiency. It provides a current spike suppression circuit based on a time window screening mechanism that effectively eliminates transient current false triggering caused by the reverse recovery characteristics of the freewheeling diode during double-pulse testing and promptly shuts down the circuit when overcurrent occurs. Through a unique circuit architecture and dynamic threshold control strategy, the risk of false operation of the overcurrent protection circuit is significantly suppressed without affecting the switching speed of the device under test, introducing additional control signals, or causing energy loss. It also accelerates the response to overcurrent detection risks, providing an innovative technical solution for improving power semiconductor device testing accuracy and system reliability. It will be understood that the present invention is described by way of some embodiments, and it will be appreciated by those skilled in the art that various changes or equivalent substitutions may be made to these features and embodiments without departing from the spirit and scope of the present invention. In addition, under the teachings of the present invention, these features and embodiments may be modified to adapt to specific circumstances and materials without departing from the spirit and scope of the present invention. Therefore, the present invention is not limited to the specific embodiments disclosed herein, and all embodiments falling within the scope of the claims of this application are intended to be protected by the present invention.

Claims

1. An anti-interference protection circuit for power semiconductor switch testing, comprising a differential sampling module and a shutdown module, characterized in that It also includes a window threshold judgment module. The output signal of the differential sampling module enters the left window input end of the window threshold judgment module after being delayed by the delay module. The output signal of the differential sampling module also enters the right window input end of the window threshold judgment module. The output end of the window threshold judgment module is connected to the input end of the shutdown module. When it is detected that the signals on the left and right sides of the window are both greater than the threshold voltage, the window threshold judgment module outputs a shutdown signal.

2. The anti-interference protection circuit for power semiconductor switch testing according to claim 1, characterized in that: When the peak width of the peak current signal passing through the test loop is greater than the set window delay width, the window threshold judgment module outputs a shutdown signal.

3. The anti-interference protection circuit for power semiconductor switch testing according to claim 1 or 2, characterized in that: The delay module includes a second operational amplifier U2, the inverting input terminal of the second operational amplifier U2 is connected to the output terminal of the differential sampling module; the non-inverting input terminal and the output terminal of the second operational amplifier U2 are short-circuited and connected to the window left input terminal of the window threshold judgment module.

4. The anti-interference protection circuit for power semiconductor switch testing according to claim 3, characterized in that: The window threshold determination module includes a third operational amplifier U3, a fourth operational amplifier U4, a sixth resistor R6, a first DC voltage source V1, a second DC voltage source V2 and a third DC voltage source V3. The non-inverting input terminal of the third operational amplifier U3 serves as the window left input terminal of the window threshold judgment module, the inverting input terminal of the third operational amplifier U3 is connected to the positive electrode of the first DC voltage source V1, and the negative electrode of the first DC voltage source V1 is grounded; The non-inverting input terminal of the fourth operational amplifier U4 serves as the window right input terminal of the window threshold judgment module, the inverting input terminal of the fourth operational amplifier U4 is connected to the positive electrode of the second DC voltage source V2, and the negative electrode of the second DC voltage source V2 is grounded; One end of the sixth resistor R6 is connected to the output ends of the third operational amplifier U3 and the fourth operational amplifier U4 and serves as the output end of the window threshold judgment module. The other end of the sixth resistor R6 is connected to the positive electrode of the third DC voltage source V3, and the negative electrode of the third DC voltage source V3 is grounded.

5. The anti-interference protection circuit for power semiconductor switch testing according to claim 4, characterized in that: The differential sampling module includes a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a fifth resistor R5, a first inductor L1, a second inductor L2 and a first operational amplifier U1. One end of the first inductor L1 is connected to one end of the first resistor R1 and is used to connect to the transistor under test of the transistor double pulse test circuit, and the other end is connected to one end of the second resistor R2, and the other end of the second resistor R2 is connected to the non-inverting input terminal of the first operational amplifier U1; the fourth resistor R4 is connected between the non-inverting input terminal and the output terminal of the first operational amplifier U1; One end of the second inductor L2 is connected to the other end of the first resistor R1 and is used to connect to the ground end of the transistor double pulse test circuit, and the other end is connected to one end of the third resistor R3, and the other end of the third resistor R3 is connected to the inverting input end of the first operational amplifier U1. The two ends of the fifth resistor R5 are respectively connected to the inverting input end of the first operational amplifier U1 and the ground potential.

6. The anti-interference protection circuit for power semiconductor switch testing according to claim 5, characterized in that: The shutdown module includes a fifth operational amplifier U5, a seventh resistor R7, an eighth resistor R8, a ninth resistor R9, a first IGBT Q1, a second IGBT Q2 and a third IGBT Q3. The inverting input terminal of the fifth operational amplifier U5 serves as the input terminal of the shutdown module; one end of the seventh resistor R7 is grounded, and the other end and one end of the eighth resistor R8 are connected to the non-inverting input terminal of the fifth operational amplifier U5; the other end of the eighth resistor R8 is connected to the output terminal of the fifth operational amplifier U5; one end of the ninth resistor R9 is connected to the output terminal of the fifth operational amplifier U5, and the other end is connected to the gates of the first IGBT, the second IGBT and the third IGBT; the source and drain of the first IGBT Q1, the second IGBT Q2 and the third IGBT Q3 are respectively connected and used to be connected in series in the transistor double pulse test circuit.

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