Method and device for training performance prediction model of semiconductor device and related equipment

Abstract

The invention provides a training method and device for a semiconductor device performance prediction model and related equipment, and the method comprises the steps: determining key parameters and performance parameters of a semiconductor device, the key parameters comprise key size parameters and / or process parameters, and the performance parameters comprise electrical characteristic parameters of the semiconductor device; based on the multiple groups of key parameter values and the corresponding performance parameter values, establishing a sample set; the key parameter values are disturbed, and the correlation degree of the key parameters and the performance parameters is determined; wherein after the key parameter value is disturbed, the change condition of the corresponding performance parameter value is used for representing the correlation degree of the key parameter and the performance parameter; initializing the weight of a preset neural network model based on the performance prediction target and the correlation degree of the key parameter and the performance parameter; and inputting at least part of samples in the sample set into a weight-initialized preset neural network model for training to obtain a semiconductor device performance prediction model.

Description

Technical Field

[0001] The embodiments of the present disclosure relate to the technical field of semiconductor device performance prediction, and in particular to a training method, apparatus, and related equipment for a semiconductor device performance prediction model. Background Art

[0002] In integrated circuits, DE-FinFET (Drain-Extended Fin-Field-Effect-Transistor) has been widely used in advanced nodes due to its advantages such as high integration, high operating voltage, and large operating current.

[0003] However, the current cost of device tape-out testing at advanced nodes is high, simulation calculations take a long time, and the calculation results are difficult to converge, which is very unfavorable for device research and development iteration.

[0004] Therefore, how to quickly and accurately predict the performance of DE-FinFET devices, so as to achieve advanced node device development and rapid iteration at extremely low cost, urgently needs to be solved by technical personnel in this field. Summary of the Invention

[0005] In response to the above technical problems, the embodiments of the present disclosure provide a method, apparatus, and related equipment for training a semiconductor device performance prediction model, which can establish a semiconductor device performance prediction model with high prediction accuracy.

[0006] In a first aspect, an embodiment of the present disclosure provides a method for training a semiconductor device performance prediction model, comprising:

[0007] Determining key parameters and performance parameters of a semiconductor device, wherein the key parameters include key dimensional parameters and / or process parameters, and the performance parameters include electrical characteristic parameters of the semiconductor device;

[0008] Establishing a sample set based on multiple sets of key parameter values and their corresponding performance parameter values;

[0009] Perturbing the key parameter value to determine the degree of correlation between the key parameter and the performance parameter; wherein, after the key parameter value is perturbed, the change in the corresponding performance parameter value is used to indicate the degree of correlation between the key parameter and the performance parameter;

[0010] Initialize the weights of the preset neural network model based on the performance prediction target and the correlation between the key parameters and the performance parameters;

[0011] At least part of the samples in the sample set are input into a preset neural network model after weight initialization for training to obtain a semiconductor device performance prediction model.

[0012] Optionally, the perturbation of the key parameter value to determine the correlation between the key parameter and the performance parameter includes:

[0013] Obtaining initial performance parameter values corresponding to key parameter values;

[0014] Adjust the value of the key parameter and obtain the disturbance performance parameter value corresponding to the adjusted key parameter value;

[0015] Comparing the initial performance parameter value with the disturbed performance parameter value to obtain a change in the performance parameter value before and after the disturbance;

[0016] Based on the changes, the degree of correlation between the key parameters and the performance parameters is determined; wherein, the greater the change, the higher the degree of correlation.

[0017] Optionally, initializing the weights of a preset neural network model based on the performance prediction target and the degree of correlation between the key parameters and the performance parameters includes:

[0018] Based on the correlation between the key parameters and the performance parameters, determining the key parameters whose correlation with the performance prediction target is within a preset range;

[0019] Allocating weights within a first preset weight range to the key parameters within the preset degree range;

[0020] A weight within a second preset weight range is assigned to the key parameters that are not within the preset degree range.

[0021] Optionally, the method further includes:

[0022] Based on the performance prediction target and the correlation between the key parameters and the performance parameters, the loss function of the preset neural network model is determined.

[0023] Optionally, determining the loss function of the preset neural network model based on the performance prediction target and the correlation between the key parameters and the performance parameters includes:

[0024] Based on the correlation between the key parameters and the performance parameters, determining the key parameters whose correlation with the performance prediction target is within a preset range;

[0025] Assigning a weight within a third preset weight range to the error term corresponding to the key parameter within the preset degree range;

[0026] A weight within a fourth preset weight range is assigned to the error term corresponding to the key parameter that is not within the preset degree range.

[0027] Optionally, the semiconductor device includes a drain-extended FinFET; and the key parameters of the semiconductor device include at least one of the following:

[0028] The length of the overlapping area between the field plate and the gate structure;

[0029] Length of the field plate extension area.

[0030] Optionally, the key parameters of the semiconductor device further include at least one of the following:

[0031] Thick gate oxide length;

[0032] Thin gate oxide length;

[0033] The length of the overlap between the drift region and the thick gate oxide layer;

[0034] Field plate structure thickness;

[0035] channel region doping concentration;

[0036] doping concentration on the drain side of the drift region;

[0037] Doping concentration on the channel side of the drift region;

[0038] Doping concentration of the drain region.

[0039] Optionally, the performance parameter includes at least one of the following:

[0040] Breakdown voltage;

[0041] On-resistance per unit area;

[0042] Threshold voltage;

[0043] transconductance;

[0044] Saturation current;

[0045] Leakage current;

[0046] Cutoff frequency;

[0047] Maximum oscillation frequency.

[0048] Optionally, the performance prediction target includes any one of the following:

[0049] The accuracy of breakdown voltage prediction is prioritized;

[0050] The prediction accuracy of on-resistance per unit area is prioritized;

[0051] Threshold voltage prediction accuracy is prioritized;

[0052] Transconductance prediction accuracy is prioritized;

[0053] Saturation current prediction accuracy is prioritized;

[0054] Leakage current prediction accuracy is prioritized;

[0055] The cutoff frequency prediction accuracy is prioritized;

[0056] The maximum oscillation frequency prediction accuracy is prioritized.

[0057] Optionally, establishing a sample set based on multiple groups of key parameter values and their corresponding performance parameter values includes:

[0058] Randomly generate multiple sets of key parameter values within the preset value range of each key parameter;

[0059] Obtain the performance parameter values corresponding to each group of key parameter values;

[0060] A sample set is established based on multiple groups of key parameter values and their corresponding performance parameter values.

[0061] Optionally, the preset value range is determined according to design requirements of the semiconductor device.

[0062] Optionally, the design requirement includes: an operating voltage of the semiconductor device meets a preset condition.

[0063] Optionally, obtaining the performance parameter values corresponding to each group of key parameter values includes any one of the following:

[0064] Obtain the performance parameter values corresponding to each group of key parameter values through software simulation;

[0065] The performance parameter values corresponding to each group of key parameter values are obtained through tape-out.

[0066] In a second aspect, an embodiment of the present disclosure provides a training device for a semiconductor device performance prediction model, comprising:

[0067] a parameter determination module configured to determine key parameters and performance parameters of a semiconductor device, wherein the key parameters include key dimensional parameters and / or process parameters, and the performance parameters include electrical characteristic parameters of the semiconductor device;

[0068] a sample set establishing module configured to establish a sample set based on a plurality of sets of key parameter values and their corresponding performance parameter values;

[0069] a perturbation test module configured to perturb the key parameter value to determine the degree of correlation between the key parameter and the performance parameter; wherein, after the key parameter value is perturbed, the change in the corresponding performance parameter value is used to indicate the degree of correlation between the key parameter and the performance parameter;

[0070] The model training module is configured to initialize the weights of a preset neural network model based on the performance prediction target and the correlation between the key parameters and the performance parameters; and input at least part of the samples in the sample set into the preset neural network model after weight initialization for training to obtain a semiconductor device performance prediction model.

[0071] In a third aspect, an embodiment of the present disclosure provides a storage medium having a computer program stored thereon, which, when executed by a processor, executes the steps of the method for training a semiconductor device performance prediction model described in any of the above embodiments.

[0072] In a fourth aspect, an embodiment of the present disclosure provides a computer program product, comprising a computer program, which, when running, executes the steps of the method for training a semiconductor device performance prediction model described in any of the above embodiments.

[0073] By adopting the training method of the semiconductor device performance prediction model provided by the embodiment of the present disclosure, by determining the key parameters and performance parameters of the semiconductor device, a sample set can be established based on multiple groups of key parameter values and their corresponding performance parameter values. By perturbing the key parameter values and determining the degree of correlation between the key parameters and the performance parameters, the weights of the preset neural network model can be initialized based on the performance prediction target and the degree of correlation between the key parameters and the performance parameters, and the semiconductor device performance prediction model can be obtained by inputting at least part of the samples in the sample set into the preset neural network model after weight initialization for training. Since the weights of the preset neural network model are initialized according to the degree of correlation between the key parameters and performance parameters of the semiconductor device, the trained semiconductor device performance prediction model can accurately predict the performance of the semiconductor device. BRIEF DESCRIPTION OF THE DRAWINGS

[0074] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are merely embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without any creative work.

[0075] Figure 1 A flow chart of a method for training a semiconductor device performance prediction model consistent with some embodiments of the present disclosure is shown.

[0076] Figure 2 A cross-sectional schematic diagram of a drain-extended FinFET consistent with some embodiments of the present disclosure is shown.

[0077] Figure 3A schematic diagram of key parameters of a drain-extended FinFET consistent with some embodiments of the present disclosure is shown.

[0078] Figure 4 A schematic structural diagram of a preset neural network model consistent with some embodiments of the present disclosure is shown.

[0079] Figure 5 A schematic structural diagram of a semiconductor device performance prediction model training device consistent with some embodiments of the present disclosure is shown. DETAILED DESCRIPTION

[0080] As described in the background technology, the cost of tape-out testing of devices at advanced nodes is currently high, simulation calculations take a long time, and the calculation results are difficult to converge, which is very unfavorable for device research and development iterations.

[0081] In response to the above problems, the embodiments of the present disclosure provide some training methods for semiconductor device performance prediction models. These methods can establish a sample set based on multiple groups of key parameter values and their corresponding performance parameter values by determining the key parameters and performance parameters of the semiconductor device. By perturbing the key parameter values and determining the degree of correlation between the key parameters and the performance parameters, the weights of the preset neural network model can be initialized based on the performance prediction target and the degree of correlation between the key parameters and the performance parameters, and the semiconductor device performance prediction model can be obtained by inputting at least part of the samples in the sample set into the preset neural network model after weight initialization for training. Since the weights of the preset neural network model are initialized according to the degree of correlation between the key parameters and the performance parameters of the semiconductor device, the trained semiconductor device performance prediction model can accurately predict the performance of the semiconductor device.

[0082] In order to enable those skilled in the art to better understand and implement the embodiments of the present disclosure, the concepts, schemes, principles and advantages of the embodiments of the present disclosure are described in detail below with reference to the accompanying drawings and through specific application examples.

[0083] Figure 1 A flow chart of a method for training a semiconductor device performance prediction model consistent with some embodiments of the present disclosure is shown. The method for training a semiconductor device performance prediction model can be performed by a processor or a first device. For example, the processor can be a central processing unit (CPU), a microprocessor (microprocessor), or a field programmable gate array (FPGA). For example, the first device can be a training device for a semiconductor device performance prediction model. In some embodiments, referring to Figure 5The schematic diagram of the structure of a training device for a semiconductor device performance prediction model consistent with some embodiments of the present disclosure is shown, the first device can be Figure 5 A training device for a semiconductor device performance prediction model consistent with the present invention. In one application scenario, referring to Figure 5 The training device T may include a parameter determination module T1, a sample set establishment module T2, a disturbance test module T3 and a model training module T4.

[0084] Reference Figure 1 In some embodiments, the training method of the semiconductor device performance prediction model may include steps A, B, C, D, and E. It is understandable that the training method of the semiconductor device performance prediction model may include more or fewer steps, and the order of the steps may be the same or different.

[0085] Step A: determining key parameters and performance parameters of a semiconductor device, wherein the key parameters include key dimensional parameters and / or process parameters, and the performance parameters include electrical characteristic parameters of the semiconductor device.

[0086] In some embodiments, the semiconductor device may include a diode, a transistor, a sensor, or the like.

[0087] For example, the semiconductor device may include a field effect transistor, a drain-extended fin field effect transistor, etc.

[0088] Critical Dimension (CD) parameters can be used to measure device performance and manufacturing process accuracy. They generally refer to the minimum feature size that requires strict control during the manufacturing process. Examples include gate length, contact hole size (CD), source / drain spacing (SDS), metal line width / space (MMS), and via diameter (CD).

[0089] Process parameters can directly or indirectly affect device performance, yield, and reliability. Process parameters often run through the entire manufacturing process (from substrate preparation to packaging and testing) and require strict monitoring and optimization. For example, important process parameters in the lithography process include exposure dose, focus accuracy, and overlay error. Important process parameters in the etching process include etch rate and selectivity. Important process parameters in the ion implantation process include implant energy, implant dose, annealing temperature, and tilt angle.

[0090] The electrical characteristic parameters of semiconductor devices can be considered core indicators for evaluating device performance, reliability, and applicability. They can directly or indirectly affect key chip performance such as speed, power consumption, noise, and robustness. For example, these parameters may include common electrical parameters applicable to most devices, such as threshold voltage, on-resistance, leakage current, and breakdown voltage (VBR).

[0091] It can be understood that the embodiments of the present disclosure do not impose any specific limitation on semiconductor devices.

[0092] Step B: establishing a sample set based on multiple sets of key parameter values and their corresponding performance parameter values.

[0093] The performance parameter values are related to the key parameter values. A set of key parameter values corresponds to a set of performance parameter values. A set of key parameter values and a set of performance parameter values constitute a sample, and multiple samples constitute a sample set.

[0094] It should be noted that in the process of establishing a sample set, only a single key parameter and / or performance parameter may be selected, or multiple key parameters and / or performance parameters may be selected, and the constructed sample set may be presented in the form of an array or matrix.

[0095] Step C: perturb the key parameter value to determine the correlation between the key parameter and the performance parameter; wherein, after the key parameter value is perturbated, the change in the corresponding performance parameter value is used to indicate the correlation between the key parameter and the performance parameter.

[0096] In a specific implementation, the key parameter value can be perturbed by adjusting the magnitude of the key parameter value. For example, the key parameter value can be increased by 5%, or decreased by 5%. After the key parameter value is perturbed, the corresponding performance parameter value will change. The change in the corresponding performance parameter value can indicate the degree of correlation between the key parameter and the performance parameter. For example, a larger change in the corresponding performance parameter value can indicate a higher degree of correlation between the key parameter and the performance parameter, while a smaller change in the corresponding performance parameter value can indicate a lower degree of correlation between the key parameter and the performance parameter.

[0097] Step D: Initialize the weights of the preset neural network model based on the performance prediction target and the correlation between the key parameters and the performance parameters.

[0098] Step E: Inputting at least part of the samples in the sample set into a preset neural network model after weight initialization for training to obtain a semiconductor device performance prediction model.

[0099] In some embodiments, the sample set may be divided into a training sample set and a test sample set. The training sample set is input into a preset neural network model for training to obtain a semiconductor device performance prediction model.

[0100] For example, the sample set can be divided in proportion, for example, 80% of the sample set can be used as a training sample set and 20% can be used as a testing sample set.

[0101] By employing the training method described in the above embodiment, by determining the key parameters and performance parameters of the semiconductor device, a sample set can be established based on multiple sets of key parameter values and their corresponding performance parameter values. By perturbing the key parameter values and determining the degree of correlation between the key parameters and the performance parameters, the weights of a preset neural network model can be initialized based on the performance prediction target and the degree of correlation between the key parameters and the performance parameters. Furthermore, by inputting at least some of the samples in the sample set into the preset neural network model after weight initialization for training, a semiconductor device performance prediction model is obtained. Since the weights of the preset neural network model are initialized based on the degree of correlation between the key parameters and the performance parameters of the semiconductor device, the trained semiconductor device performance prediction model can accurately predict the performance of the semiconductor device.

[0102] In some embodiments, the semiconductor device may include a drain-extended FinFET. Figure 2 A cross-sectional diagram of a drain-extended FinFET consistent with some embodiments of the present disclosure is shown. The drain-extended FinFET may include:

[0103] Silicon substrate 201.

[0104] A buried oxide layer 202 is grown on the silicon substrate 201 .

[0105] The source region 203 is epitaxially grown on the buried oxide layer 202 .

[0106] The channel region 204 is epitaxially grown on the buried oxide layer 202 and has a fin-like shape.

[0107] The drain extension region 205 is epitaxially grown on the buried oxide layer 202 .

[0108] The drain region 206 is epitaxially grown on the buried oxide layer 202 .

[0109] The gate structure consists of a gate thin oxide layer 207 , the overlapping portion of the gate thick oxide layer 208 and the channel region 204 , a hafnium dioxide layer 210 , a titanium nitride layer 211 , a polysilicon layer 212 and a silicon nitride sidewall 213 . The gate structure wraps the channel region 204 .

[0110] The field plate structure is composed of the overlapping portion of the gate thick oxide layer 208 and the drain extension region 205 , and the thick oxide layer 209 . The field plate structure wraps the drain extension region 205 .

[0111] In some embodiments, a key parameter of the drain-extended FinFET may include at least one of a length of an overlapping region between the field plate and the gate structure and a length of an extension region of the field plate.

[0112] For example, refer to Figure 3 The key parameter diagram of a drain-extended fin field effect transistor consistent with some embodiments of the present disclosure is shown in FIG. Figure 2 The key parameters of the drain-extended FinFET may include at least one of the length 1 of the overlap region between the field plate and the gate structure and the length 2 of the field plate extension region.

[0113] In some embodiments, the key parameters of the drain-extended fin field-effect transistor may include at least one of the length of the overlapping area between the field plate and the gate structure, the length of the field plate extension area, the length of the thick gate oxide layer, the length of the thin gate oxide layer, the length of the overlapping area between the drift region and the thick gate oxide layer, the thickness of the field plate structure, the doping concentration of the channel region, the doping concentration on the drain region side of the drift region, the doping concentration on the channel region side of the drift region, and the doping concentration of the drain region.

[0114] For example, continue to refer to Figure 3 , and combined with reference Figure 2The key parameters of the drain-extended fin field-effect transistor may include at least one of the length of the overlapping area between the field plate and the gate structure 1, the length of the field plate extension area 2, the length of the thick gate oxide layer 3, the length of the thin gate oxide layer 4, the length of the overlapping area between the drift region and the thick gate oxide layer 5, the thickness of the field plate structure 6, the doping concentration of the channel region 7, the doping concentration on the drain region side of the drift region 8, the doping concentration on the channel region side of the drift region 9, and the doping concentration of the drain region 10.

[0115] In some embodiments, the performance parameters of the semiconductor device may include at least one of breakdown voltage, on-resistance per unit area, threshold voltage, transconductance, saturation current, leakage current, cutoff frequency, and maximum oscillation frequency.

[0116] It is understood that the embodiments of the present disclosure do not impose any specific restrictions on key parameters and performance parameters. The above embodiments are merely illustrative.

[0117] Performance parameter values are correlated with key parameter values. For example, the length of the field plate extension region is correlated with the breakdown voltage. The longer the field plate extension region, the smaller the peak electric field near the channel region, the more uniform the electric field distribution, and the higher the breakdown voltage.

[0118] For another example, the doping concentration on the drain side of the drift region is related to the on-resistance per unit area. A higher doping concentration on the drain side of the drift region provides more carriers, increases the on-current, and thus reduces the on-resistance per unit area.

[0119] For another example, the length of the overlap region between the field plate and the gate structure is related to the cutoff frequency. The longer the overlap region between the field plate and the gate structure, the greater the parasitic capacitance between the gate region and the drain region, and the lower the cutoff frequency.

[0120] In some embodiments, step B may include the following steps:

[0121] Step B1: randomly generate multiple sets of key parameter values within the preset value range of each key parameter.

[0122] In some embodiments, the preset value range can be determined according to the design requirements of the semiconductor device.

[0123] The design requirements can be pre-set design rules, such as those that specify the minimum size, spacing, overlap, and other parameters of key structures such as transistors, interconnects, and contact holes, which directly affect the performance, yield, and reliability of the chip. They can also be customized specific requirements.

[0124] In some embodiments, the design requirement may include that a breakdown voltage of the semiconductor device meets a preset condition.

[0125] The breakdown voltage of the semiconductor device may include a gate oxide breakdown voltage, a source-drain-substrate breakdown voltage, a channel breakdown voltage, etc., and a range may be pre-set according to design requirements as the preset condition.

[0126] In other words, the preset condition is the parameter value of the breakdown voltage in the design rule.

[0127] In a non-limiting embodiment, taking the gate oxide breakdown voltage of DeFinFET as an example, the breakdown voltage of a low-end DeFinFET used for standard I / O circuits or low-power high-voltage applications can be 5V to 20V; combined with optimized drain doping and field plate design, the breakdown voltage of a high-end DeFinFET suitable for power management ICs can be 20V to 50V.

[0128] In some embodiments, the design requirement may include that an operating voltage of the semiconductor device meets a preset condition.

[0129] The operating voltage range of the semiconductor device may be affected by the process node, application scenario, and power consumption performance requirements, so the range may be pre-set according to design requirements as the preset condition.

[0130] In other words, the preset condition is the parameter value of the operating voltage in the design rule.

[0131] In a non-limiting embodiment, taking DeFinFET as an example, the operating voltage is generally 1.8V to 30V.

[0132] For example, continue to refer to Figure 3 When the design requirement of the drain-extended fin field-effect transistor is an operating voltage of 5V, the preset value range of the length 1 of the overlap region between the field plate and the gate structure can be set to [0.02-0.1] μm; the preset value range of the length 2 of the field plate extension region can be set to [0.15-0.3] μm; the preset value range of the length 3 of the thick gate oxide layer can be set to [0.02-0.04] μm; the preset value range of the length 4 of the thin gate oxide layer can be set to [0.01-0.03] μm; the preset value range of the length 5 of the overlap region between the drift region and the thick gate oxide layer can be set to [0.01-0.04] μm; the preset value range of the thickness of the field plate structure 6 can be set to [0.005-0.01] μm; the preset value range of the doping concentration of the channel region 7 can be set to [10 16 -10 18 ]cm -3The preset value range of the doping concentration 8 on the side of the drift region drain region can be set to [10 16 -10 18 ]cm -3 The preset value range of the doping concentration 9 on the side of the drift region channel region can be set to [10 15 -10 17 ]cm -3 The preset value range of the doping concentration 10 of the drain region can be set to [10 20 -10 21 ]cm -3 .

[0133] It is understood that the embodiments of the present disclosure do not impose specific restrictions on the preset value ranges of various key parameters, and those skilled in the art can determine them based on the actual design requirements of the semiconductor device. For example, when the operating voltage of the drain-extended FinFET changes from 5V to 6V, the preset value ranges of the field plate and gate structure overlap length 1, the field plate extension region length 2, the thick gate oxide layer length 3, the thin gate oxide layer length 4, the drift region and thick gate oxide layer overlap length 5, and the field plate structure thickness 6 can be increased, while the preset value ranges of the drift region drain region doping concentration 8, the drift region channel region doping concentration 9, and the drain region doping concentration 10 can be decreased.

[0134] Step B2: Obtain the performance parameter values corresponding to each group of key parameter values.

[0135] In some embodiments, the performance parameter values corresponding to each group of key parameter values can be obtained through software simulation.

[0136] For example, the performance of the semiconductor device may be simulated using a Technology Computer Aided Design (TCAD) tool to obtain performance parameter values corresponding to each group of key parameter values.

[0137] In some embodiments, the performance parameter values corresponding to each group of key parameter values can be obtained through tape-out.

[0138] Step B3: establishing a sample set based on multiple sets of key parameter values and their corresponding performance parameter values.

[0139] A set of key parameter values corresponds to a set of performance parameter values, and a set of key parameter values and a set of performance parameter values constitute a sample. For example, a sample may include 10 key parameters (field plate and gate structure overlap length, field plate extension region length, thick gate oxide layer length, thin gate oxide layer length, drift region and thick gate oxide layer overlap length, field plate structure thickness, channel region doping concentration, drift region drain region side doping concentration, drift region channel region side doping concentration, drain region doping concentration) and 8 performance parameters (breakdown voltage, on-resistance per unit area, threshold voltage, transconductance, saturation current, leakage current, cutoff frequency, and maximum oscillation frequency).

[0140] In some embodiments, step C may include the following steps:

[0141] Step C1: Obtain initial performance parameter values corresponding to key parameter values.

[0142] In some embodiments, initial performance parameter values corresponding to key parameter values may be obtained through software simulation.

[0143] For example, the performance of a semiconductor device may be simulated using a Technology Computer Aided Design (TCAD) tool.

[0144] In some embodiments, performance parameter values corresponding to key parameter values may be obtained through tape-out.

[0145] Step C2: adjusting the key parameter value and obtaining the disturbance performance parameter value corresponding to the adjusted key parameter value.

[0146] For example, the value of the key parameter is increased by 5%, and the disturbance performance parameter value corresponding to the adjusted key parameter value is obtained.

[0147] Step C3: Compare the initial performance parameter value with the disturbed performance parameter value to obtain changes in the performance parameter value before and after the disturbance.

[0148] In some embodiments, the difference between the initial performance parameter value and the disturbance performance parameter value may be used as the comparison result.

[0149] In some embodiments, a ratio of the initial performance parameter value to the disturbance performance parameter value may be used as the comparison result.

[0150] It is understandable that the embodiment of the present disclosure does not impose any specific limitation on how to compare the initial performance parameter value and the disturbance performance parameter value, as long as the obtained comparison result can characterize the difference between the initial performance parameter value and the disturbance performance parameter value.

[0151] Step C4: determining the degree of correlation between the key parameter and the performance parameter based on the change; wherein the greater the change, the higher the degree of correlation.

[0152] For example, when the value of the key parameter is increased by 5%, if the change rate of the disturbance performance parameter value corresponding to the adjusted key parameter value is less than 20% compared with the initial performance parameter value, it is considered that the correlation between the key parameter and the performance parameter is low; if the change rate of the disturbance performance parameter value corresponding to the adjusted key parameter value is greater than 20% compared with the initial performance parameter value, it is considered that the correlation between the key parameter and the performance parameter is high.

[0153] In some embodiments, step D may include the following steps:

[0154] Step D1: Based on the correlation between the key parameters and the performance parameters, determine the key parameters whose correlation with the performance prediction target is within a preset range.

[0155] In some embodiments, the performance prediction target may include any one of the following: breakdown voltage prediction accuracy priority, unit area on-resistance prediction accuracy priority, threshold voltage prediction accuracy priority, transconductance prediction accuracy priority, saturation current prediction accuracy priority, leakage current prediction accuracy priority, cutoff frequency prediction accuracy priority, and maximum oscillation frequency prediction accuracy priority.

[0156] In some embodiments, the preset degree range can be set according to the change rate of the disturbance performance parameter value corresponding to the adjusted key parameter value compared to the initial performance parameter value, for example, it can be set to (20%, +∞).

[0157] For example, when the performance prediction goal prioritizes breakdown voltage prediction accuracy, key parameters with a higher correlation with the breakdown voltage may be determined based on the correlation between the key parameters and the breakdown voltage.

[0158] Step D2: assigning weights within a first preset weight range to the key parameters within the preset degree range.

[0159] Step D3: assigning weights within a second preset weight range to the key parameters that are not within the preset degree range.

[0160] The weights within the first preset weight range are greater than the weights within the second preset weight range.

[0161] For example, the first preset weight range can be [5, 10], and the second preset weight range can be [1, 5). A value can be randomly selected within the first preset weight range as the weight of the key parameter within the preset degree range, and a value can be randomly selected within the second preset weight range as the weight of the key parameter not within the preset degree range.

[0162] By adopting the above embodiment, the key parameters whose correlation with the performance prediction target is within a preset range are determined based on the correlation between the key parameters and the performance parameters, and the key parameters within the preset range are assigned weights within a first preset weight range, and the key parameters not within the preset range are assigned weights within a second preset weight range, so that the weights of the key parameters with a higher correlation with the performance prediction target are greater than the key parameters with a lower correlation with the performance prediction target, thereby further improving the prediction accuracy of the trained semiconductor device performance prediction model under the performance prediction target.

[0163] In some embodiments, for step E, since there are many key parameters and performance parameters that can be selected, and different key parameters and performance parameters may have different dimensions, the ranges of different input and output data vary greatly when training the preset neural network model, and some data may exhibit an exponential distribution. Therefore, before training the preset neural network model, the sample set can be preprocessed.

[0164] For example, key parameters with exponential distributions (e.g., channel region doping concentration, drift region drain region doping concentration, drift region channel region doping concentration, and drain region doping concentration) or performance parameters (e.g., on-resistance per unit area, leakage current) can be logarithmized and all values normalized to 0-1 for training. When predicting output data, all values can be denormalized and the logarithmic values can be exponentialized.

[0165] In some embodiments, reference Figure 4 The schematic diagram of the structure of a preset neural network model consistent with some embodiments of the present disclosure is shown. The preset neural network model may include an input layer, 4 hidden layers and an output layer. The number of input layer neurons x corresponds to the key parameters of the determined semiconductor device (for example, 10, corresponding to the key parameters of the overlapping region between the field plate and the gate structure, the length of the field plate extension region, the length of the thick gate oxide layer, the length of the thin gate oxide layer, the length of the overlapping region between the drift region and the thick gate oxide layer, the thickness of the field plate structure, the doping concentration of the channel region, the doping concentration of the drift region drain region side, the doping concentration of the drift region channel region side, the doping concentration of the drain region), hidden layer 1 has 32 neurons, hidden layer 2 has 64 neurons, hidden layer 3 has 32 neurons, hidden layer 4 has 16 neurons, and the output layer neurons y correspond to the performance parameters of the determined semiconductor device (for example, 8, corresponding to the performance parameters breakdown voltage, on-resistance per unit area, threshold voltage, transconductance, saturation current, leakage current, cut-off frequency and maximum oscillation frequency).

[0166] In some embodiments, the method for training a semiconductor device performance prediction model may further include:

[0167] Step F: determining the loss function of the preset neural network model based on the performance prediction target and the correlation between the key parameters and the performance parameters.

[0168] In some embodiments, step F may include the following steps:

[0169] Step F1: Based on the correlation between the key parameters and the performance parameters, determine the key parameters whose correlation with the performance prediction target is within a preset range.

[0170] For more embodiments of step F1 , reference may be made to the relevant embodiments of step D1 , which will not be described in detail here.

[0171] Step F2: assigning weights within a third preset weight range to the error terms corresponding to the key parameters within the preset range.

[0172] Step F3: assigning weights within a fourth preset weight range to the error terms corresponding to the key parameters that are not within the preset degree range.

[0173] The weight within the third preset weight range is greater than the weight within the fourth preset weight range.

[0174] For example, the third preset weight range may be [5, 10], and the fourth preset weight range may be [1, 5]. A value may be randomly selected within the third preset weight range as the weight of the error term corresponding to the key parameter within the preset range, and a value may be randomly selected within the fourth preset weight range as the weight of the error term corresponding to the key parameter not within the preset range.

[0175] By adopting the above embodiment, the key parameters whose correlation with the performance prediction target is within a preset range are determined based on the correlation between the key parameters and the performance parameters, and the error terms corresponding to the key parameters within the preset range are assigned weights within a third preset weight range, and the error terms corresponding to the key parameters not within the preset range are assigned weights within a fourth preset weight range, so that the weights of the error terms corresponding to the key parameters with a higher correlation with the performance prediction target are greater than those of the key parameters with a lower correlation with the performance prediction target, thereby further improving the prediction accuracy of the trained semiconductor device performance prediction model under the performance prediction target.

[0176] The present disclosure also provides a training device for a semiconductor device performance prediction model. Figure 5 The structure diagram of a training device for a semiconductor device performance prediction model consistent with some embodiments of the present disclosure is shown. In some embodiments, the training device T may include:

[0177] The parameter determination module T1 is configured to determine key parameters and performance parameters of a semiconductor device, wherein the key parameters include key dimensional parameters and / or process parameters, and the performance parameters include electrical characteristic parameters of the semiconductor device.

[0178] In some embodiments of the present disclosure, the parameter determination module may be implemented by an integrated circuit. In some embodiments, the parameter determination module may be implemented by a processor, such as a central processing unit (CPU), a microprocessor (microprocessor), or a field programmable gate array (FPGA). In some embodiments, the parameter determination module may be implemented by a combination of an integrated circuit and a processor.

[0179] The sample set establishing module T2 is configured to establish a sample set based on multiple groups of key parameter values and their corresponding performance parameter values.

[0180] In some embodiments of the present disclosure, the sample set establishment module may be implemented by an integrated circuit. In some embodiments, the sample set establishment module may be implemented by a processor, such as a central processing unit (CPU), a microprocessor (microprocessor), or a field programmable gate array (FPGA). In some embodiments, the sample set establishment module may be implemented by a combination of an integrated circuit and a processor.

[0181] The disturbance test module T3 is configured to perturb the key parameter value to determine the degree of correlation between the key parameter and the performance parameter; wherein, after the key parameter value is perturbed, the change in the corresponding performance parameter value is used to indicate the degree of correlation between the key parameter and the performance parameter.

[0182] In some embodiments of the present disclosure, the perturbation test module may be implemented by an integrated circuit. In some embodiments, the perturbation test module may be implemented by a processor, such as a central processing unit (CPU), a microprocessor, or a field programmable gate array (FPGA). In some embodiments, the perturbation test module may be implemented by a combination of an integrated circuit and a processor.

[0183] The model training module T4 is configured to initialize the weights of the preset neural network model based on the performance prediction target and the correlation between the key parameters and the performance parameters; and input at least part of the samples in the sample set into the preset neural network model after weight initialization for training to obtain a semiconductor device performance prediction model.

[0184] In some embodiments of the present disclosure, the model training module may be implemented by an integrated circuit. In some embodiments, the model training module may be implemented by a processor, such as a central processing unit (CPU), a microprocessor (microprocessor), or a field programmable gate array (FPGA). In some embodiments, the model training module may be implemented by a combination of an integrated circuit and a processor.

[0185] By adopting the above-mentioned embodiment, the key parameters and performance parameters of the semiconductor device can be determined by the parameter determination module. The sample set establishment module can be used to establish a sample set based on multiple groups of key parameter values and their corresponding performance parameter values. The perturbation test module is used to perturb the key parameter values to determine the degree of correlation between the key parameters and the performance parameters. The model training module can be used to initialize the weights of the preset neural network model based on the performance prediction target and the degree of correlation between the key parameters and the performance parameters, and to train the preset neural network model after weight initialization by inputting at least part of the samples in the sample set to obtain a semiconductor device performance prediction model. Since the weights of the preset neural network model are initialized according to the degree of correlation between the key parameters and the performance parameters of the semiconductor device, the semiconductor device performance prediction model obtained by training the training device can accurately predict the performance of the semiconductor device.

[0186] In the embodiment of the present disclosure, the training device for the semiconductor device performance prediction model can adopt the training method for the semiconductor device performance prediction model described in any of the aforementioned embodiments to train a semiconductor device performance prediction model. The specific steps can be referred to the aforementioned embodiments and will not be repeated here.

[0187] An embodiment of the present disclosure further provides a storage medium having a computer program stored thereon. When the computer program is executed by a processor, the steps of the method for training a semiconductor device performance prediction model described in any of the above embodiments are executed.

[0188] In some embodiments, the non-volatile computer-readable storage medium may be any suitable computer-readable storage medium such as an optical disk, a mechanical hard disk, or a solid-state drive.

[0189] An embodiment of the present disclosure further provides a computer program product, including a computer program, which, when running, executes the steps of the method for training a semiconductor device performance prediction model described in any of the above embodiments.

[0190] It should be noted that the modules in the embodiments of the present disclosure may be composed of discrete components or implemented by a single electrical chip.

[0191] In the present disclosure, unless otherwise clearly specified and limited, the terms "first", "second", "third", "fourth", etc. in the embodiments of the present disclosure are only used to distinguish the description of different preset weight ranges and are not used to impose any limitations on their specific content, structure or values.

[0192] The terms "or" and "and / or" in this disclosure are used to describe the relationship between associated objects, which indicates non-exclusive inclusion. For example, "A and / or B" and "A or B" can both include: "A alone", "B alone", or "A and B", where "A" and "B" can include a single object or multiple objects. For another example, "A, B and / or C", "A, B or C" and "A, B and C" can both include: "A alone", "B alone", "C alone", "A and B", "A and C", "B and C", or "A, B and C", where "A", "B" and "C" can include a single object or multiple objects. In addition, " / " in this disclosure is used to indicate the "or" relationship between the preceding and following associated objects. In this disclosure, "at least one of A or B" and "one or more of A and B" have the same meaning as "A or B" above, and "one or more of A, B and C" and "at least one of A, B or C" have the same meaning as "A, B or C" above. "One or more of A, B and C" have the same meaning as "A, B or C" above.

[0193] Although the embodiments of the present disclosure are disclosed above, the present invention is not limited thereto. Any person skilled in the art may make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be subject to the scope defined by the claims.

Claims

1. A method for training a semiconductor device performance prediction model, characterized in that: include: Determining key parameters and performance parameters of a semiconductor device, wherein the key parameters include key dimensional parameters and / or process parameters, and the performance parameters include electrical characteristic parameters of the semiconductor device; Establishing a sample set based on multiple sets of key parameter values and their corresponding performance parameter values; Perturbing the key parameter value to determine the degree of correlation between the key parameter and the performance parameter; wherein, after the key parameter value is perturbed, the change in the corresponding performance parameter value is used to indicate the degree of correlation between the key parameter and the performance parameter; Initialize the weights of the preset neural network model based on the performance prediction target and the correlation between the key parameters and the performance parameters; At least part of the samples in the sample set are input into a preset neural network model after weight initialization for training to obtain a semiconductor device performance prediction model.

2. The method according to claim 1, characterized in that The perturbation of the key parameter value to determine the correlation between the key parameter and the performance parameter includes: Obtaining initial performance parameter values corresponding to key parameter values; Adjust the value of the key parameter and obtain the disturbance performance parameter value corresponding to the adjusted key parameter value; Comparing the initial performance parameter value with the disturbed performance parameter value to obtain a change in the performance parameter value before and after the disturbance; Based on the changes, the degree of correlation between the key parameters and the performance parameters is determined; wherein, the greater the change, the higher the degree of correlation.

3. The method according to claim 1, characterized in that Initializing the weights of the preset neural network model based on the performance prediction target and the correlation between the key parameters and the performance parameters includes: Based on the correlation between the key parameters and the performance parameters, determining the key parameters whose correlation with the performance prediction target is within a preset range; Allocating weights within a first preset weight range to the key parameters within the preset degree range; A weight within a second preset weight range is assigned to the key parameters that are not within the preset degree range.

4. The method according to claim 1, wherein Also includes: Based on the performance prediction target and the correlation between the key parameters and the performance parameters, the loss function of the preset neural network model is determined.

5. The method according to claim 4, characterized in that The determining of the loss function of the preset neural network model based on the performance prediction target and the correlation between the key parameters and the performance parameters includes: Based on the correlation between the key parameters and the performance parameters, determining the key parameters whose correlation with the performance prediction target is within a preset range; Assigning a weight within a third preset weight range to the error term corresponding to the key parameter within the preset degree range; A weight within a fourth preset weight range is assigned to the error term corresponding to the key parameter that is not within the preset degree range.

6. The method according to claim 1, characterized in that The semiconductor device includes a drain-extended fin field-effect transistor; and the key parameters of the semiconductor device include at least one of the following: The length of the overlapping area between the field plate and the gate structure; Length of the field plate extension area.

7. The method according to claim 6, characterized in that The key parameters of the semiconductor device also include at least one of the following: Thick gate oxide length; Thin gate oxide length; The length of the overlap between the drift region and the thick gate oxide layer; Field plate structure thickness; channel region doping concentration; doping concentration on the drain side of the drift region; Doping concentration on the channel side of the drift region; Doping concentration of the drain region.

8. The method according to claim 1, characterized in that The performance parameters include at least one of the following: Breakdown voltage; On-resistance per unit area; Threshold voltage; transconductance; Saturation current; Leakage current; Cutoff frequency; Maximum oscillation frequency.

9. The method according to claim 8, characterized in that The performance prediction target includes any of the following: The accuracy of breakdown voltage prediction is prioritized; The prediction accuracy of on-resistance per unit area is prioritized; Threshold voltage prediction accuracy is prioritized; Transconductance prediction accuracy is prioritized; Saturation current prediction accuracy is prioritized; Leakage current prediction accuracy is prioritized; The cutoff frequency prediction accuracy is prioritized; The maximum oscillation frequency prediction accuracy is prioritized.

10. The method according to claim 1, characterized in that The step of establishing a sample set based on multiple sets of key parameter values and their corresponding performance parameter values includes: Randomly generate multiple sets of key parameter values within the preset value range of each key parameter; Obtain the performance parameter values corresponding to each group of key parameter values; A sample set is established based on multiple groups of key parameter values and their corresponding performance parameter values.

11. The method according to claim 10, characterized in that The preset value range is determined according to the design requirements of the semiconductor device.

12. The method according to claim 11, characterized in that The design requirements include: the operating voltage of the semiconductor device meets preset conditions.

13. The method according to claim 10, characterized in that The obtaining of the performance parameter values corresponding to each group of key parameter values includes any of the following: Obtain the performance parameter values corresponding to each group of key parameter values through software simulation; The performance parameter values corresponding to each group of key parameter values are obtained through tape-out.

14. A training device for a semiconductor device performance prediction model, characterized in that: include: a parameter determination module configured to determine key parameters and performance parameters of a semiconductor device, wherein the key parameters include key dimensional parameters and / or process parameters, and the performance parameters include electrical characteristic parameters of the semiconductor device; a sample set establishing module configured to establish a sample set based on a plurality of sets of key parameter values and their corresponding performance parameter values; a perturbation test module configured to perturb the key parameter value to determine the degree of correlation between the key parameter and the performance parameter; wherein, after the key parameter value is perturbed, the change in the corresponding performance parameter value is used to indicate the degree of correlation between the key parameter and the performance parameter; The model training module is configured to initialize the weights of a preset neural network model based on the performance prediction target and the correlation between the key parameters and the performance parameters; and input at least part of the samples in the sample set into the preset neural network model after weight initialization for training to obtain a semiconductor device performance prediction model.

15. A storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the method for training a semiconductor device performance prediction model according to any one of claims 1 to 13 are executed.

16. A computer program product comprising a computer program, characterized in that When the computer program is run, the steps of the method for training a semiconductor device performance prediction model according to any one of claims 1 to 13 are executed.

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