Adaptive control method of phase change memory, phase change memory, medium and electronic equipment

Abstract

The invention discloses an adaptive control method of a phase change memory, the phase change memory, a storage medium and electronic equipment, and belongs to the technical field of semiconductors, and the method comprises the following steps: in a minimum time interval from writing to reading, writing an all-0 data mode into a storage unit; executing a reading operation on the storage unit in the all-0 data writing mode to obtain detection data; according to the detection data, obtaining at least one storage array bit error rate index; and based on a comparison result of the bit error rate index and a preset threshold value, selecting a target voltage gear in a pre-configured voltage gear set so as to adjust the reading voltage of the storage unit to a corresponding reading voltage gear. According to the method, through all-0 mode rapid detection and bit error rate global evaluation under the minimum write-to-read interval, self-adaptive accurate calibration of the read voltage is realized, and the reliability and durability of the memory are remarkably improved while the test efficiency is ensured.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to an adaptive control method of a phase change memory, a phase change memory, a medium, and an electronic device. Background Art

[0002] Phase Change Memory (PCM) faces severe reliability challenges during long-term operation. This problem stems from the irreversible aging characteristics of the phase change material during cyclic write / erase operations. As the number of cycles increases, the threshold voltage (Vt) of the memory cell exhibits significant nonlinear drift: rapidly decreasing at the beginning of its life (BOL) and gradually saturating at the end of its life (EOL). This dynamic change leads to a significant mismatch between the preset read voltage (Vread) and actual requirements. Failure to accurately adjust it in a timely manner will directly lead to two problems:

[0003] First, the Uncorrectable Bit Error Rate (UBER) rises sharply, which may exceed the fault tolerance of the Error Correction Code (ECC); second, it accelerates material degradation and shortens device life. Summary of the Invention

[0004] The main purpose of the present invention is to provide an adaptive control method for phase change memory, phase change memory, medium and electronic equipment, aiming to solve the read voltage mismatch problem caused by nonlinear drift of the phase change memory threshold voltage and improve data reliability and device durability.

[0005] To achieve the above objectives, the present invention proposes an adaptive control method for a phase change memory, wherein the phase change memory includes at least one storage array, and the storage array includes a plurality of storage cells. The method includes:

[0006] writing an all-0 data pattern to the storage unit within a minimum write-to-read time interval;

[0007] Performing a read operation on the storage unit in which the all-0 data pattern is written to obtain detection data;

[0008] Obtaining a bit error rate indicator of the at least one storage array according to the detection data;

[0009] Based on a comparison result between the bit error rate indicator and a preset threshold, a target voltage level is selected from a preconfigured voltage level set to adjust the read voltage of the memory cell to a corresponding read voltage level.

[0010] The present invention further provides a phase change memory, comprising:

[0011] at least one storage array, each storage array comprising a plurality of storage cells;

[0012] A data writing module, configured to write an all-0 data pattern to a storage unit within a minimum write-to-read time interval;

[0013] A data reading module, configured to perform a read operation on the all-0 data pattern to obtain detection data;

[0014] an error analysis module, configured to obtain an error rate indicator of the at least one storage array based on the detection data;

[0015] The voltage adjustment module is configured to select a target voltage level from a preconfigured voltage level set based on a comparison result between the bit error rate indicator and a preset threshold value, so as to adjust the read voltage of the storage unit to the corresponding read voltage level.

[0016] The present invention also provides an electronic device comprising a memory, a processor, and a computer program stored in the memory and running on the processor, wherein the processor implements the steps of the above-mentioned adaptive control method of the phase change memory when executing the computer program.

[0017] The present invention further provides a non-transitory computer-readable storage medium having a computer program stored thereon. When the computer program is executed by a processor, the steps of the adaptive control method of the phase change memory described above are implemented.

[0018] The technical solution of the present invention obtains a bit error rate indicator (including bit error rate (RBER) and fault bit count (FBC)) of at least one storage array by writing an all-0 pattern to a storage cell and then reading test data under the minimum write-to-read time interval condition; and triggers adaptive switching of multiple read voltage levels (R1-Rn) by comparing the bit error rate indicator with a preset threshold.

[0019] Therefore, based on the internal dynamic inspection mechanism of the phase-change memory, the present invention uses dual-index collaborative detection in the all-0 write mode (RBER evaluates the overall bit error rate, and FBC locates the local failure unit) to accurately capture the nonlinear logarithmic drift characteristics of the threshold voltage (Vt) with the number of cycles, realize adaptive voltage gear switching timing decision-making, and effectively avoid the risks of premature switching (waste of ECC redundancy) or delayed switching (bit error rate exceeds the standard) caused by traditional fixed thresholds, thereby accurately compensating for the Vt drift heterogeneity of the phase-change memory, ensuring data reliability while extending the device service life. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on the structures shown in these drawings without paying any creative work.

[0021] Figure 1 Schematic diagram of the phase change memory Vt and Vread changes and the impact of E3 loss;

[0022] Figure 2 The logarithmic relationship between the reset threshold voltage (Reset Vt) and the number of cycles of the phase change memory is shown in FIG.

[0023] Figure 3 This is a graph showing the change of phase change memory reference data with the number of cycles;

[0024] Figure 4 A graph showing the relationship between the bit error rate of a phase change memory and the read voltage setting and the number of cycles limit;

[0025] Figure 5 This is a graph showing the relationship between the reset threshold voltage and the cycle limit of the phase change memory.

[0026] Figure 6 Flowchart of the adaptive control method of the phase change memory according to the first embodiment of the present invention;

[0027] Figure 7 This is a durability-reading voltage correspondence table according to the second embodiment of the present invention;

[0028] Figure 8 is a flow chart of an adaptive control method for a phase change memory according to a second embodiment of the present invention;

[0029] Figure 9 A schematic diagram of the structure of a phase change memory provided by an embodiment of the present invention;

[0030] Figure 10 A schematic structural diagram of an electronic device provided by an embodiment of the present invention.

[0031] The purpose, features and advantages of the present invention will be further described with reference to the accompanying drawings and in conjunction with the embodiments. DETAILED DESCRIPTION

[0032] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. All other embodiments obtained by ordinary technicians in this field based on the embodiments of the present invention without making any creative efforts shall fall within the scope of protection of the present invention.

[0033] In addition, in the present invention, descriptions such as "first" and "second" are for descriptive purposes only and should not be understood as indicating or implying their relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include at least one of such features. In addition, the technical solutions between the various embodiments can be combined with each other, but this must be based on the fact that they can be implemented by ordinary technicians in this field. When the combination of technical solutions is contradictory or cannot be implemented, it should be deemed that such combination of technical solutions does not exist and is not within the scope of protection required by the present invention.

[0034] Please refer to Figure 1 , Figure 1 This diagram illustrates the changes in Vt and Vread of a phase-change memory (PCM) and the impact of E3 loss. The diagram shows the changes in the threshold voltage (Vt) of the PCM during endurance testing and the need to adjust the read voltage (Vread). The diagram presents two sets of waveforms, corresponding to the states of data "1" and "0" at the beginning of life (BOL) and end of life (EOL), respectively. Due to the inherent characteristics of PCM, the threshold voltage (Vt) shifts after endurance testing. Vt decreases more rapidly at the beginning of life (BOL) and then saturates at the end of life (EOL). Furthermore, Vt does not change linearly with the number of cycles, but rather has an approximately linear correlation with the logarithm of the number of cycles. As can be seen in the diagram, the waveform positions corresponding to BOL and EOL in the waveform sets for "1" and "0" are different, reflecting the change in Vt. Furthermore, due to E3 loss, if the read voltage (Vread) is not adjusted, reset failures will be observed after cycling. To ensure that the bit error rate (UBER) meets the requirements at the end of life (EOL), the read voltage (Vread) needs to be adjusted. The figure shows the corresponding read voltages for EOL and BOL (Vread-EOL and Vread-BOL), respectively, showing the change in the required read voltage at different life stages. This shows that as Vt changes, Vread needs to change accordingly to correctly read the stored data.

[0035] Please refer to Figure 2 , Figure 2This is a graph showing the relationship between the reset threshold voltage (Reset Vt) and the logarithm of the number of cycles in a phase-change memory. The graph shows the relationship between the reset threshold voltage (Reset Vt) and the logarithm of the number of cycles (Log(Cycling)) in a phase-change memory. The horizontal axis in the graph represents the logarithm of the number of cycles (Log(Cycling)), indicating that the number of cycles is measured on a logarithmic scale. This is because in the endurance test of phase-change memory, the number of cycles often ranges widely, and the use of a logarithmic scale can more effectively display the data change trend; the vertical axis represents the reset threshold voltage (Reset Vt), which is used to measure the threshold voltage value when the phase-change memory is in the reset state. As can be seen from the oblique line in the graph, the reset threshold voltage (Reset Vt) and the logarithm of the number of cycles (Log(Cycling)) are approximately linearly related. As the logarithm of the number of cycles increases, the reset threshold voltage (Reset Vt) gradually decreases. This reflects the characteristics of phase change memory, that is, as the number of cycles in the endurance test increases, the reset threshold voltage will gradually decrease, that is, the threshold voltage does not change linearly with the number of cycles, but is approximately linearly related to the logarithm of the number of cycles.

[0036] Please refer to Figure 3 , Figure 3 This is a graph showing the change of the reference data of the phase change memory with the number of cycles. The graph shows how the measured values change with the number of cycles (CYC) under different conditions. The horizontal axis in the graph is the number of cycles (CYC), ranging from 1 to 10,000,000. The vertical axis is the measured value of Vt, in millivolts (mV). There are three broken lines of different colors in the graph, blue, green and red, representing different groups of measurement data, and marked with "BOTTOM" (bottom layer) and "TOP" (top layer). Judging from the trend of the broken lines, as the number of cycles increases, the measured values of the three broken lines generally show a downward trend, and there is a more obvious decline or fluctuation at some cycle nodes. This reflects the situation in which the measured values of the phase change memory change with the increase in the number of cycles during the durability test, which is related to the characteristics of the phase change memory such as the threshold voltage drift.

[0037] Please refer to Figure 4 , Figure 4This graph shows the relationship between the phase-change memory bit error rate (BER) and the read voltage setting and cycle limit. The graph shows how the bit error rate (RBER) changes at the minimum write-to-read time interval (minimal w2f delay) for different read voltage settings (Vread1) and cycle limit (CYClimit) for the phase-change memory. Because the threshold voltage (Vt) of the phase-change memory decreases after cycling, different read voltages (Vread) are used based on different R settings (e.g., R1-R5), with Vread values decreasing in the order of R1 → R2 → R3 → R4 → R5. The horizontal axis of the graph represents the Vread1 setting, arranged from R1 to R5, and the vertical axis represents the bit error rate (RBER) at the minimum write delay. The graph includes five curves, corresponding to CYC limit1-CYC limit4, and a gray curve t0, representing the bit error rate as a function of the Vread1 setting under different cycle limit conditions. At both the beginning of life (BOL) and end of life (EOL), the bit error rate decreases as Vread1 changes from R1 to R5. When the number of cycles reaches limit1, it switches from R1 to R2. Otherwise, at the minimum write delay (w2r delay), the bit error rate indicator will exceed the preset threshold (RBER or FBC limit, horizontal dashed line in the figure). However, due to factors such as die-to-die variations, cell-to-cell variations, and wear leveling accuracy, it is difficult to precisely control the Vread switching between different R values in the figure.

[0038] Please refer to Figure 5 , Figure 5 This is a graph showing the relationship between the reset threshold voltage and the cycle limit of the phase change memory. Figure 5 The figure shows the relationship between the reset threshold voltage (Reset Vt) and the cycle limit (CYC limit) in the phase change memory. The figure shows the distribution of the reset threshold voltage under different cycle limit conditions in the form of curves. There are five curves of different colors, corresponding to Figure 4The curves CYC limit1-CYC limit4 and t0 are shown. The t0 curve represents the distribution of the reset threshold voltage at the beginning of the lifespan. From the relative positions of the curves, as the cycle limit increases from CYC limit1 to CYC limit4, the position and shape of the curves change, reflecting that the distribution range and characteristics of the reset threshold voltage change with the increase in the number of cycles. This change is related to the endurance characteristics of the phase change memory, that is, as the cycle operation progresses, the threshold voltage of the storage cell will drift and change. Figure 5 The changing trend of the reset threshold voltage under different cycle limit conditions is shown through an intuitive curve.

[0039] In summary, Figure 1-Figure 5 The performance of phase change memory in endurance testing was demonstrated. Figure 1 This indicates that cycling can cause the threshold voltage (Vt) to change, resulting in E3 loss, which can lead to reset state issues and necessitate adjustment of the read voltage (Vread); Figure 2 It shows that the reset threshold voltage has an approximately linear relationship with the logarithm of the cycle number, revealing the change characteristics of Vt with the cycle number; Figure 3 Presents the degradation of phase change memory reference data as the number of cycles increases; Figure 4 Shows the change in bit error rate under different read voltage settings and cycle number limits and its relationship with the bit error limit; Figure 5 The distribution and change trend of reset threshold voltage under different cycle number limits are presented. Figure 1-Figure 5 It shows that in the endurance test of phase change memory, there are problems such as threshold voltage change, reference data change, bit error rate fluctuation, etc., and factors such as read voltage setting and number of cycles will have a significant impact on its performance, highlighting the necessity of precise control and optimization of relevant parameters to ensure the stability of memory performance.

[0040] Please refer to Figure 6 , Figure 6 This is a flow chart of a method for adaptively controlling a phase change memory according to a first embodiment of the present invention. A method for adaptively controlling a phase change memory, wherein the phase change memory includes at least one memory array, the memory array including a plurality of memory cells, and the method includes:

[0041] S610 , writing an all-0 data pattern into a storage unit within a minimum write-to-read time interval.

[0042] Optionally, the minimum write-to-read interval (e.g., 1µs, 10µs, 25µs, etc.) is the shortest allowable time interval from the end of a write operation to the start of a read operation. This parameter is used to simulate strict read and write timing conditions, allowing the test to expose potential bit errors.

[0043] Alternatively, the all-0 data pattern requires writing a continuous sequence of logic 0 values to all memory cells under test. This pattern is effective for testing the stability of the reset state (high-impedance state) because writing all 0s forces the phase-change material into an amorphous state (reset state). A read anomaly at this time can indicate a bit error.

[0044] S620 , performing a read operation on the storage unit written with the all-0 data pattern to obtain detection data.

[0045] Optionally, a read operation is performed immediately after writing to capture transient errors caused by residual write effects or material relaxation. The test data contains the read states of all memory cells, providing raw data for subsequent bit error rate calculations.

[0046] S630: Obtain a bit error rate indicator of at least one storage array according to the detection data.

[0047] Optionally, the bit error rate indicator includes a bit error rate (RBER) and a fault bit count (FBC). The bit error rate is obtained by counting the ratio of the number of error bits read in the reset state to the total number of bits, reflecting the reliability of the reset state. The fault bit count is obtained by counting the number of cells in at least one storage array that exceed a preset tolerance voltage range, and is used to locate local failure areas; wherein the preset tolerance voltage range represents the safe voltage fluctuation range (i.e., safe operating range) allowed for the storage cell during a read operation. The calculation needs to cover the range of the full phase change memory so that the evaluation results are globally representative.

[0048] S640 , based on a comparison result of the bit error rate indicator and a preset threshold, select a target voltage level from a preconfigured voltage level set to adjust to a corresponding read voltage value.

[0049] Optionally, the dynamic adjustment mechanism includes: if the bit error rate indicator exceeds a preset threshold, gradually increasing the read voltage level of the current storage cell to a target voltage level according to a preconfigured voltage level set (e.g., R1 → R2 → R3, etc.), and each time the read voltage level of the storage cell is increased, re-performing the operation of obtaining test data until the bit error rate indicator is compared with the preset threshold. The adjustment is terminated when the bit error rate indicator is lower than the preset threshold and the read voltage level of the storage cell is within a preset safe operating range (to avoid overvoltage damage).

[0050] Optionally, the durability level association includes: selecting a corresponding gear according to the durability level (such as Limit1-Limit4) of the cumulative number of erase and write times of the phase change memory. For example, when the number of cycles is high, a higher gear is preferably selected (such as R2 rather than R1). Each time the read voltage of the storage unit is switched to a new voltage gear, the read voltage of the storage unit is maintained at the new voltage gear for at least one detection cycle to stabilize the state of the storage unit. Among them, the lower limit of the detection cycle is an integer multiple of the minimum write-to-read time interval, and the specific multiple can be determined according to actual conditions.

[0051] Optionally, the verification and iteration steps include: after each switching of the reading voltage of the storage unit to a new voltage level and the voltage level adjustment, re-executing the operation of obtaining the bit error rate; if the adjusted bit error rate indicator still exceeds the preset threshold, continue switching the reading voltage of the storage unit to the next voltage level, and performing the operation of obtaining the bit error rate until the requirements are met.

[0052] In some embodiments, the frequency of performing the bit error rate acquisition operation is determined according to any one of the following factors:

[0053] The endurance level range of the phase change memory's cumulative erase and write times;

[0054] Continuous use time of the current voltage level;

[0055] The growth rate of the bit error rate indicator relative to historical detection results.

[0056] Specifically, the test frequency is dynamically adjusted based on the erase / write count level, the current gear usage time, or the bit error rate growth rate. For example, high endurance levels (near the end of life) require more frequent testing.

[0057] In summary, the adaptive control method of the phase change memory of the present invention first adopts strict timing control of the minimum write-to-read time interval (minimal w2f delay) to expose potential problems under the most stringent conditions; secondly, by writing an all-0 data pattern, stability detection is specifically performed on the reset state (high impedance state); then a multi-dimensional evaluation system including bit error rate and fault bit count is established to comprehensively monitor the memory status from both macro and micro levels; finally, based on real-time bit error feedback and durability level, a periodic inspection mechanism of the internal multiple R values (such as R1-R6) of the phase change memory is adopted to dynamically determine the Vread switching timing. This periodic inspection mechanism can achieve precise control in the following ways:

[0058] First, dynamic switching timing is determined. The system regularly performs full scan tests on all preset R gears, monitoring the bit error rate trends at each gear. Switching is triggered when the bit error rate at the current voltage gear exceeds a preset threshold. This design avoids the high bit error risk caused by premature switching and prevents excessive error correction capabilities caused by late switching.

[0059] Second, balance durability differences. By independently running the inspection algorithm within each die and introducing durability level ranges, the R switching threshold is dynamically adjusted based on the historical error growth curve of each die (such as Vt drift rate, bit error rate acceleration, etc.). For example, for dies that age faster, switching is triggered when the bit error rate reaches a preset threshold (such as 80%), while for dies that age slowly, the switching is relaxed to a preset threshold (such as 90%). At the module level, by comparing the R value distribution histograms of each module, compensatory intervention is implemented for modules with lagging switching (such as more than 30% of the dies still remain in the low gear), and their test frequency is increased (such as by 2 times).

[0060] The timing control in step S610, the test mode in step S620, the evaluation indicators in step 630, and the voltage level adjustment in step S640 effectively compensate for performance degradation caused by threshold voltage drift, material aging, and cell discreteness. Without compromising ECC error correction capabilities, dies with different endurance performance can complete voltage switching at the optimal time, thereby maintaining stable read reliability throughout the entire life cycle and significantly improving the durability and data integrity of the memory.

[0061] Please refer to Figure 7 , Figure 7 This is a durability-read voltage correspondence table of the second embodiment of the present invention. The table shows the read voltage selections (Vread selections) and read voltage adjustment (Vread adjustment) corresponding to different endurance intervals. The voltage gear set includes the first voltage gear to the sixth voltage gear (such as R1-R6) arranged in ascending order. Each voltage gear corresponds to a pre-configured read voltage value (such as TBD, TBD-50mV, TBD-100mV, TBD-125mV, TBD-150mV, TBD-175mV) and an endurance level interval (such as 0-20k, 2k-40k, 20k-100k, 50k-400k, 200k-1M, 400k-4M). It should be noted that the voltage gear, read voltage value and endurance level interval can be adjusted according to actual conditions and are not limited to the above examples.

[0062] Alternatively, endurance is measured by the number of erase and write cycles, divided into multiple intervals: for 0-20k cycles, the read voltage is selected as R1, and the adjustment is marked as "TBD" (preset value); for 2k-40k cycles, the read voltage is selected as R2, and the adjustment is "TBD-50mV" (preset value and reduced by 50 millivolts); for 20k-100k cycles, the read voltage is selected as R3, and the adjustment is "TBD-100mV"; for 50k-400k cycles, the read voltage is selected as R4, and the adjustment is "TBD-125mV"; for 200k-1M cycles, the read voltage is selected as R5, and the adjustment is "TBD-150mV"; for 400k-4M cycles, the read voltage is selected as R6, and the adjustment is "TBD-175mV". This shows that as the number of erase and write cycles of the memory increases, the endurance changes, and the corresponding read voltage will have different selections and potential reduction adjustments.

[0063] Please refer to Figure 8 , Figure 8 This is a flow chart of a phase change memory adaptive control method according to a second embodiment of the present invention. The read voltage adjustment process includes:

[0064] S810 , setting the read voltage to Vread_R1 .

[0065] S811, set the minimum time interval between writing and reading, and adopt the all-0 data mode.

[0066] S812: Check whether the bit error rate (RBER) and / or the faulty bit count (FBC) exceed corresponding preset thresholds (limits):

[0067] If it does not exceed the preset threshold, it means that the currently set read voltage Vread_R1 is appropriate, and the process ends.

[0068] If it exceeds the preset threshold, it means that Vread_R1 is not appropriate, and the process goes to S813.

[0069] S813, setting the read voltage to Vread_R2.

[0070] S814, setting the minimum write-to-read time interval again, and adopting the all-0 data mode.

[0071] S815: Recheck whether the bit error rate (RBER) or the faulty bit count (FBC) exceeds the corresponding preset threshold (limit):

[0072] If it does not exceed the preset threshold, it indicates that Vread_R2 is a suitable reading voltage and the process ends.

[0073] If it exceeds the preset threshold, it means that Vread_R2 is also inappropriate, and the process goes to S816.

[0074] S816 , setting the read voltage to Vread_R3 .

[0075] S817, set the minimum time interval between writing and reading, and adopt the all-0 data mode.

[0076] S818: Check whether the bit error rate (RBER) or the faulty bit count (FBC) exceeds the corresponding preset threshold (limit):

[0077] If it does not exceed the preset threshold, that is, Vread_R3 is a suitable reading voltage, the process ends.

[0078] If it exceeds the preset threshold, the read voltage is set to the next preset read voltage (if there is a preset read voltage that has not been tested, such as Vread_R4 after Vread_R3; if all preset read voltage options have been traversed, the operation is stopped), and then the minimum write-to-read time interval is set again, and the all-0 data mode is used. Then, the bit error rate (RBER) or fault bit count (FBC) is rechecked to see if it exceeds the corresponding preset threshold. This process is repeated until a read voltage setting is found that satisfies the bit error rate (RBER) or fault bit count (FBC) not exceeding the corresponding preset threshold, or all preset read voltage options are traversed.

[0079] Therefore, the present invention aims at the problem of read voltage mismatch caused by nonlinear drift of threshold voltage in phase change memory, and improves data reliability and device durability through a dynamic hierarchical voltage adjustment mechanism combined with real-time feedback of bit errors. The specific process includes: first, a preset initial read voltage (Vread_R1) is used to test with the minimum write-to-read time interval and the all-0 data mode, and the voltage matching is judged by real-time monitoring of the bit error rate (RBER) or the fault bit count (FBC); if the bit error rate index exceeds the preset threshold, it is switched to a higher-order read voltage (Vread_R2, Vread_R3, etc.) step by step, and each level repeats the process of the minimum write-to-read time interval and the all-0 data mode until a read voltage that can stably meet the bit error tolerance is found. This method not only compensates for the nonlinear mismatch caused by threshold voltage drift through voltage-error coordinated regulation, but also eliminates timing and data interference through the test conditions of the minimum write-to-read time interval and the all-0 data mode, and finally achieves precise voltage matching that is adaptive to the aging state, significantly reducing the bit error rate and extending the life of the device.

[0080] The phase change memory provided by the present invention is described below. The phase change memory described below and the adaptive control method of the phase change memory described above can be referred to each other.

[0081] Please refer to Figure 9 , Figure 9 A schematic diagram of the structure of a phase change memory provided by an embodiment of the present invention is provided. A phase change memory 900 includes at least one storage array 910 , a data writing module 920 , a data reading module 930 , an error analysis module 940 , and a voltage adjustment module 950 .

[0082] Optionally, the storage array 910 includes several storage units.

[0083] Optionally, the data writing module 920 is used to:

[0084] Within the minimum write-to-read time interval, an all-0 data pattern is written to the memory cell.

[0085] Optionally, the data reading module 930 is used to:

[0086] A read operation is performed on the storage unit in which the all-0 data pattern is written to obtain detection data.

[0087] Optionally, the error analysis module 940 is configured to:

[0088] A bit error rate indicator of at least one storage array is obtained according to the detection data.

[0089] Optionally, the voltage adjustment module 950 is configured to:

[0090] Based on a comparison result between the bit error rate indicator and a preset threshold, a target voltage level is selected from a preconfigured voltage level set to adjust the read voltage of the memory cell to a corresponding read voltage level.

[0091] Optionally, the minimum write-to-read time interval refers to the shortest allowed time interval from the end of a write operation to the start of a read operation.

[0092] Optionally, the all-0 data pattern is a pattern of writing a continuous data sequence of logic 0 values into all tested memory cells.

[0093] Optionally, the bit error rate indicator includes a bit error rate and a faulty bit count, and the bit error analysis module 940 is further configured to:

[0094] Determine the bit error rate based on the ratio of the number of error bits read in the reset state to the total number of bits;

[0095] and / or

[0096] The number of memory cells exceeding a preset tolerance voltage range in at least one memory array is counted to obtain a failure bit count.

[0097] Optionally, the voltage adjustment module 950 is further configured to:

[0098] When the bit error rate indicator exceeds a preset threshold, the read voltage level of the current storage unit is increased to a target voltage level in the order of the voltage level set;

[0099] Each time the read voltage level of the storage unit is increased, the operation of obtaining the detection data is performed again until the bit error rate indicator is compared with the preset threshold value, until the bit error rate indicator is lower than the preset threshold value;

[0100] When the bit error rate indicator is lower than the preset threshold,

[0101] The read voltage level of the memory cell is within a preset safe operating range.

[0102] Optionally, the voltage adjustment module 950 is further configured to:

[0103] Start adjusting from the initial voltage level in the voltage level set;

[0104] Selecting a corresponding voltage level from the voltage level set according to the endurance level interval of the cumulative number of erase and write times of the phase change memory, so as to adjust the read voltage of the memory cell;

[0105] Each time the read voltage of the memory cell is switched to a new voltage level, the read voltage of the memory cell is kept at the new voltage level for at least one detection cycle.

[0106] Optionally, the voltage adjustment module 950 is further configured to:

[0107] After each switching of the read voltage of the storage unit to a new voltage level, re-performing the operation of obtaining the bit error rate;

[0108] If the bit error rate indicator still exceeds the preset threshold, the read voltage of the memory cell is continuously switched to the next voltage level, and the operation of obtaining the bit error rate is performed.

[0109] Optionally, the frequency of executing the detection operation is determined according to any of the following factors:

[0110] The endurance level range of the phase change memory's cumulative erase and write times;

[0111] Continuous use time of the current voltage level;

[0112] The growth rate of the bit error rate indicator relative to historical detection results.

[0113] Optionally, the voltage level set includes a first voltage level to a sixth voltage level arranged in ascending order, and each voltage level corresponds to a preconfigured read voltage value and durability level interval.

[0114] Optionally, the voltage adjustment module 950 is further configured to:

[0115] When the bit error rate indicator corresponding to the current voltage level of the storage unit read voltage exceeds the preset threshold, the read voltage of the storage unit is switched to the read voltage corresponding to the next higher voltage level in sequence; after each switching of the storage unit read voltage to the next higher voltage level, it is verified whether the bit error rate indicator simultaneously meets the conditions of being lower than the preset threshold and being in the preset safe operating range, until the conditions are met or all voltage levels in the voltage level set are traversed.

[0116] It should be noted here that the above-mentioned phase change memory provided by the embodiment of the present invention can implement all the method steps implemented by the above-mentioned method embodiment and can achieve the same technical effects. The parts and beneficial effects that are the same as those in the method embodiment will not be described in detail here.

[0117] Figure 10 Schematic diagram of the structure of an electronic device provided by an embodiment of the present invention. Figure 10 As shown, the electronic device may include: a processor (Processor) 1010, a communication interface (Communications Interface) 1020, a memory (Memory) 1030 and a communication bus 1040, wherein the processor 1010, the communication interface 1020, and the memory 1030 communicate with each other via the communication bus 1040. The processor 1010 can call the logic instructions in the memory 1030 to execute the adaptive control method of the phase change memory.

[0118] In addition, the logic instructions in the above-mentioned memory 1030 can be implemented in the form of a software functional unit and can be stored in a computer-readable storage medium when sold or used as an independent product. Based on this understanding, the technical solution of the present invention, or the part that contributes to the prior art, or the part of the technical solution, can be embodied in the form of a software product. The computer software product is stored in a storage medium and includes several instructions for enabling a computer device (which can be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the method described in each embodiment of the present invention. The aforementioned storage medium includes: various media that can store program codes, such as a USB flash drive, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk.

[0119] On the other hand, the present invention also provides a computer program product, which includes a computer program stored on a non-transitory computer-readable storage medium, and the computer program includes program instructions. When the program instructions are executed by a computer, the computer can execute the adaptive control method of the phase change memory provided by the above methods.

[0120] On the other hand, the present invention further provides a non-transitory computer-readable storage medium having a computer program stored thereon, which is used to execute the above-mentioned adaptive control method of the phase change memory when the computer program is executed by a processor.

[0121] An embodiment of the present invention provides an electronic device, a computer program product, and a processor-readable storage medium, on which the computer program stored enables the processor to implement all the method steps implemented in the above-mentioned method embodiment and to achieve the same technical effect. The parts and beneficial effects of this embodiment that are the same as those in the method embodiment will not be described in detail here.

[0122] The phase change memory embodiments described above illustrate that the units may or may not be physically separate, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed across multiple network units. Some or all of the modules may be selected based on actual needs to achieve the purpose of this embodiment. Those skilled in the art can understand and implement the present invention without inventive effort.

[0123] Through the description of the above embodiments, those skilled in the art can clearly understand that each embodiment can be implemented by means of software plus a necessary general hardware platform, or of course, by hardware. Based on this understanding, the essence of the above technical solution or the part that contributes to the existing technology can be embodied in the form of a software product. The computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, a magnetic disk, an optical disk, etc., and includes a number of instructions for enabling a computer device (which can be a personal computer, a server, or a network device, etc.) to execute the methods described in each embodiment or certain parts of the embodiments.

[0124] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the various embodiments of the present invention.

Claims

1. An adaptive control method for a phase change memory, wherein the phase change memory comprises at least one memory array, wherein the memory array comprises a plurality of memory cells, wherein: include: writing an all-0 data pattern to the storage unit within a minimum write-to-read time interval; Performing a read operation on the storage unit in which the all-0 data pattern is written to obtain detection data; Obtaining a bit error rate indicator of the at least one storage array according to the detection data; Based on a comparison result between the bit error rate indicator and a preset threshold, a target voltage level is selected from a preconfigured voltage level set to adjust the read voltage of the memory cell to a corresponding read voltage level.

2. The adaptive control method of phase change memory according to claim 1, characterized in that: The bit error rate indicator includes bit error rate and fault bit count; Obtaining a bit error rate indicator of the at least one storage array includes: Determine the bit error rate based on the ratio of the number of error bits read in the reset state to the total number of bits; and / or, The number of memory cells exceeding a preset tolerance voltage range in the at least one memory array is counted to obtain a failure bit count.

3. The adaptive control method of phase change memory according to claim 1, wherein: The selecting a target voltage level from a preconfigured voltage level set to adjust the read voltage of the memory cell to a corresponding read voltage level includes: When the bit error rate indicator exceeds a preset threshold, the read voltage level of the current storage unit is increased to a target voltage level in the order of the voltage level set; Each time the read voltage level of the storage unit is increased, the operation of obtaining the detection data is performed again until the bit error rate indicator is compared with the preset threshold value, until the bit error rate indicator is lower than the preset threshold value: When the bit error rate indicator is lower than a preset threshold, the read voltage level of the storage unit is in a preset safe operating range.

4. The adaptive control method of phase change memory according to claim 1, wherein: The selecting a target voltage level from a preconfigured voltage level set to adjust the read voltage of the memory cell to a corresponding read voltage level includes: Starting adjustment from an initial gear in the voltage gear set; Selecting a corresponding voltage level from the voltage level set according to the endurance level interval of the cumulative number of erase and write times of the phase change memory, so as to adjust the read voltage of the memory cell; Each time the read voltage of the memory cell is switched to a new voltage level, the read voltage of the memory cell is kept at the new voltage level for at least one detection cycle.

5. The adaptive control method of phase change memory according to claim 4, characterized in that: The method further comprises: After each switching of the read voltage of the storage unit to a new voltage level, re-performing the operation of obtaining the bit error rate; If the bit error rate indicator still exceeds the preset threshold, the read voltage of the memory cell is continuously switched to the next voltage level, and the operation of obtaining the bit error rate is performed.

6. The adaptive control method of phase change memory according to claim 5, characterized in that: The frequency of executing the operation of obtaining the bit error rate is determined according to any one of the following factors: The endurance level range of the phase change memory's cumulative erase and write times; Continuous use time of the current voltage level; The growth rate of the bit error rate indicator relative to historical detection results.

7. The adaptive control method of phase change memory according to claim 1, characterized in that: The voltage gear set includes a first voltage gear to a sixth voltage gear arranged in ascending order, each voltage gear corresponding to a preconfigured read voltage value and durability level interval; The method further comprises: When the bit error rate indicator corresponding to the current voltage level of the memory cell read voltage exceeds a preset threshold, sequentially switching the memory cell read voltage to a read voltage corresponding to a next higher voltage level; After each switching of the read voltage of the storage unit to the next higher voltage level, verify whether the bit error rate indicator simultaneously meets the conditions of being lower than a preset threshold and being in a preset safe operating range, until the conditions are met or all voltage levels in the voltage level set are traversed.

8. A phase change memory, characterized in that: include: at least one storage array, each storage array comprising a plurality of storage cells; A data writing module, configured to write an all-0 data pattern to a storage unit within a minimum write-to-read time interval; A data reading module, configured to perform a read operation on the all-0 data pattern to obtain detection data; an error analysis module, configured to obtain an error rate indicator of the at least one storage array based on the detection data; The voltage adjustment module is configured to select a target voltage level from a preconfigured voltage level set based on a comparison result between the bit error rate indicator and a preset threshold value, so as to adjust the read voltage of the storage unit to the corresponding read voltage level.

9. An electronic device comprising a memory, a processor, and a computer program stored in the memory and running on the processor, characterized in that: When the processor executes the computer program, the steps of the adaptive control method of the phase change memory according to any one of claims 1 to 7 are implemented.

10. A non-transitory computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the adaptive control method for a phase change memory according to any one of claims 1 to 7 are implemented.

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