Low-power-consumption short-wave portable antenna tuner and working method thereof

Abstract

The invention discloses a low-power-consumption short-wave portable antenna tuner and a working method thereof. The antenna tuner comprises a hardware module and a software module. The working method comprises the following steps: when the short-wave radio station works normally, all circuits are in a normal working state; after tuning of the short-wave portable antenna tuner is finished, the FPGA performs zero clearing processing on the control pin of the magnetic latching relay, so that the control pin is in a state of lowest power consumption; when the short-wave portable antenna tuner is in a normal working state, the short-wave portable antenna tuner works normally if receiving a radio station action instruction within a set time, otherwise, the hardware module and the software module enter a dormant state, the FPGA internal logic only keeps a dormant awakening module, and a trigger mechanism of a falling edge is started; and when a radio station sends data to the short-wave portable antenna tuner, the FPGA quickly awakens all hardware modules and software modules in a dormant state, so that the short-wave portable antenna tuner enters a normal working state. The invention has the advantages of low power consumption, simple circuit structure, few discrete components, low cost and 100% localization.

Description

Technical Field

[0001] The present invention relates to the technical field of shortwave communication equipment and communication electronic circuits, and in particular to a low-power shortwave portable antenna tuner and a working method thereof. Background Art

[0002] With the rapid development of shortwave radio technology, the demand for single-person portable shortwave radios and shortwave portable antenna tuners has increased dramatically, with the demand for shortwave portable antenna tuners being even more prominent. The battery life of shortwave portable antenna tuners is one of the most important limiting factors. Reducing the power consumption of shortwave portable antenna tuners in standby mode and under light load conditions can improve their battery life.

[0003] The current conventional methods mainly focus on increasing the capacity of portable energy storage batteries and adopting low-power and low-performance design methods to improve battery life. These methods have the following problems:

[0004] 1. Increasing the battery capacity will greatly increase the weight, which will make the load for one person heavier and not conducive to carrying.

[0005] 2. The low power consumption and low performance design seriously affects the performance of the shortwave portable antenna tuner.

[0006] 3. Key components rely on imports, making it difficult to achieve independent control. Summary of the Invention

[0007] The object of the present invention is to provide a shortwave portable antenna tuner with low power consumption, simple circuit structure, few discrete components, low cost and 100% localization, and its working method.

[0008] The technical solution for achieving the purpose of the present invention is: a low-power shortwave portable antenna tuner, the hardware module of which includes an FPGA, an ADC circuit, a DDS circuit, a crystal oscillator circuit, a power supply circuit, an ASK modulation and demodulation circuit, and a magnetic latching relay circuit;

[0009] The FPGA is the core processor of the shortwave portable antenna tuner, responsible for the control, communication and tuning functions of the shortwave portable antenna tuner; the ADC circuit is responsible for collecting voltage and current signals; the DDS circuit is responsible for providing tuning power; the crystal oscillator circuit is responsible for the system clock of the antenna tuner; the power supply circuit is responsible for the antenna tuner voltage conversion and voltage regulation to ensure the normal operating voltage of the antenna tuner; the ASK modulation and demodulation circuit is responsible for modulating and demodulating the communication data between the radio station and the antenna tuner; and the magnetic latching relay circuit is responsible for adjusting the antenna tuner network parameters.

[0010] A method for operating a low-power shortwave portable antenna tuner comprises the following steps:

[0011] Step 1: When the shortwave radio is working normally, all circuits are in normal working state. When the shortwave portable antenna tuner is tuned, the FPGA clears the control pin of the magnetic latching relay circuit to zero, so that the magnetic latching relay is in the lowest power consumption state. That is, the FPGA sends the SET pin Vset=0 and the RESET pin Vreset=0 of the magnetic latching relay circuit, and the current is I0.

[0012] Step 2: When the shortwave portable antenna tuner is in normal working state, if it receives an action command from the radio station within time t1, it will continue to work normally; if it does not receive any action command from the radio station within time t1, it will enter a dormant state.

[0013] Step 3: The hardware module of the shortwave portable antenna tuner enters the hardware sleep state, and the current saved by the hardware sleep state is I1; the software module enters the software sleep state, and the current saved by the software sleep state is I2;

[0014] Step 4: When the shortwave portable antenna tuner enters the sleep state, the internal logic of the FPGA only retains a PLL system clock module and a sleep wake-up module, ultimately achieving ultra-low power consumption with a current of I0-I1-I2;

[0015] Step 5: Start the falling edge trigger mechanism. When the radio station sends data to the shortwave portable antenna tuner, the FPGA wakes up all the hardware and software modules in the dormant state, so that the shortwave portable antenna tuner enters the normal working state.

[0016] Compared with the prior art, the present invention has the following significant advantages: (1) it adopts power management technology, utilizes the high speed, multi-logic, parallel capabilities of FPGA and software modular parameterized reset and sleep technology to manage the power consumption of the shortwave portable antenna tuner, thereby realizing ultra-low power consumption management; (2) it designs the shortwave portable antenna tuner by selecting configurable, dormant and low-power components, thereby realizing power consumption management of the shortwave portable antenna tuner; (3) it simplifies the circuit structure, reduces the number of discrete components, reduces power consumption and cost and improves the localization rate, and all circuit components of the shortwave portable antenna tuner are completely 100% localized; (4) it adopts efficient, flexible and accurate power management software business processes to realize ultra-low power sleep mode and wake-up mode of the shortwave portable antenna tuner, thereby realizing that the performance of the shortwave portable antenna tuner is not affected and the system performance is fully utilized in the state of having ultra-low power consumption capability. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 The present invention is a structural diagram of a low-power shortwave portable antenna tuner hardware module.

[0018] Figure 2 The present invention is a structural diagram of a low-power shortwave portable antenna tuning software module.

[0019] Figure 3 It is a flow chart of the fast awakening mechanism of the present invention. DETAILED DESCRIPTION

[0020] The present invention provides a low-power shortwave portable antenna tuner, wherein the hardware module of the shortwave portable antenna tuner includes an FPGA, an ADC circuit, a DDS circuit, a crystal oscillator circuit, a power supply circuit, an ASK modulation and demodulation circuit, and a magnetic latching relay circuit;

[0021] The FPGA is the core processor of the shortwave portable antenna tuner, responsible for the control, communication and tuning functions of the shortwave portable antenna tuner; the ADC circuit is responsible for collecting voltage and current signals; the DDS circuit is responsible for providing tuning power; the crystal oscillator circuit is responsible for the system clock of the antenna tuner; the power supply circuit is responsible for the antenna tuner voltage conversion and voltage regulation to ensure the normal operating voltage of the antenna tuner; the ASK modulation and demodulation circuit is responsible for modulating and demodulating the communication data between the radio station and the antenna tuner; and the magnetic latching relay circuit is responsible for adjusting the antenna tuner network parameters.

[0022] Furthermore, the FPGA is provided with software modules, including a sleep and wake-up module, a soft core M1 module, a vector impedance calculation module, a PLL system clock module and an FPGA design module.

[0023] The present invention also provides a method for operating a low-power shortwave portable antenna tuner, comprising the following steps:

[0024] Step 1: When the shortwave radio is working normally, all circuits are in normal working state. When the shortwave portable antenna tuner is tuned, the FPGA clears the control pin of the magnetic latching relay circuit to zero, so that the magnetic latching relay is in the lowest power consumption state. That is, the FPGA sends the SET pin Vset=0 and the RESET pin Vreset=0 of the magnetic latching relay circuit, and the current is I0.

[0025] Step 2: When the shortwave portable antenna tuner is in normal working state, if it receives an action command from the radio station within time t1, it will continue to work normally; if it does not receive any action command from the radio station within time t1, it will enter a dormant state.

[0026] Step 3: The hardware module of the shortwave portable antenna tuner enters the hardware sleep state, and the current saved by the hardware sleep state is I1; the software module enters the software sleep state, and the current saved by the software sleep state is I2;

[0027] Step 4: When the shortwave portable antenna tuner enters the sleep state, the internal logic of the FPGA only retains a PLL system clock module and a sleep wake-up module, ultimately achieving ultra-low power consumption with a current of I0-I1-I2;

[0028] Step 5: Start the falling edge trigger mechanism. When the radio station sends data to the shortwave portable antenna tuner, the FPGA wakes up all the hardware and software modules in the dormant state, so that the shortwave portable antenna tuner enters the normal working state.

[0029] Furthermore, the hardware module described in step 3 enters a hardware dormant state, as follows:

[0030] The FPGA of the shortwave portable antenna tuner sends the sleep command Ven0=0 to the crystal oscillator circuit to put the crystal oscillator into sleep mode;

[0031] Send the 0x01 instruction to the address addre=0x08 of the ADC circuit through the SPI interface to put the ADC into power-off state;

[0032] Send the sleep command Ven1=0 to the power circuit to turn off part of the power supply;

[0033] Send the reset pin Vreset0=0 to the DDS circuit to put the DDS in reset state;

[0034] Ultimately, the hardware of the shortwave portable antenna tuner is in an ultra-low power consumption state.

[0035] Furthermore, the software module described in step 3 enters a software dormant state, as follows:

[0036] The sleep wake-up module of the shortwave portable antenna tuner sends a sleep instruction to the reset pin reset0=1'b1 of the soft core M1 module inside the FPGA to put it in the reset state; where 1'b1 represents 1 bit width, binary system, and number 1;

[0037] The reset pin reset1=1'b1 sent to the vector impedance calculation module puts it in reset state. The vector impedance calculation module includes digital mixing, CIC filtering, down conversion and Cordic;

[0038] The reset pin reset2=1'b1 sent to the PLL system clock module inside the FPGA puts it in reset state;

[0039] The reset pin reset3=1'b1 sent to the FPGA design module puts it in reset state;

[0040] Ultimately, the software of the shortwave portable antenna tuner is in an ultra-low power consumption state.

[0041] Furthermore, the trigger mechanism of the falling edge described in step 5 is as follows:

[0042] When the shortwave portable antenna tuner is in sleep mode, the FPGA receives the serial port command sent by the radio. The modulated serial port information of the radio is demodulated by the ASK demodulation circuit to obtain the serial port information. Based on the characteristics that the first bit of the serial port data is 0 and the last bit is 1, a falling edge trigger mechanism is designed.

[0043] When the radio station sends data to the shortwave portable antenna tuner, a falling edge will occur on the serial port receive pin RX connected to the FPGA. The FPGA's main clock uses a frequency of 100MHz, and the FPGA consistently collects RX signals at a μs-level response speed. When a falling edge occurs, the serial port data of the ASK demodulation circuit is cached for communication.

[0044] Furthermore, in step 2, t1=10s.

[0045] Furthermore, in step 5, the shortwave portable antenna tuner enters a normal working state, that is, the hardware module Ven0=1, Ven1=1, addre=0x08 data is 0x00, Vreset=1; the software module reset0=1'b0, reset1=1'b0, reset2=1'b0, reset3=1'b0, where 1'b0 represents 1 bit width, binary system, and number 0.

[0046] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0047] Example

[0048] like Figure 1 、 Figure 2 As shown, the present invention provides a low-power shortwave portable antenna tuner, including a hardware module and a software module, wherein the hardware module includes an FPGA, an ADC circuit, a DDS circuit, a crystal oscillator circuit, a power supply circuit, an ASK modulation and demodulation circuit, and a magnetic latching relay circuit; the software module includes a sleep and wake-up module, a soft core M1 module, a vector impedance calculation module, a PLL system clock module, and other FPGA design modules.

[0049] The FPGA is the core processor of the shortwave portable antenna tuner, responsible for its control, communication, tuning and other functions; the ADC circuit is responsible for collecting voltage and current signals; the DDS circuit is responsible for providing tuning power; the crystal oscillator circuit is responsible for the antenna tuner's system clock; the power supply circuit is responsible for the antenna tuner's voltage conversion and voltage regulation to ensure normal operating voltage; the ASK modulation and demodulation circuit is responsible for modulating and demodulating the communication data between the radio station and the antenna tuner; and the magnetic latching relay circuit is responsible for adjusting the antenna tuner's network parameters.

[0050] A method for operating a low-power shortwave portable antenna tuner comprises the following steps:

[0051] Step 1: When the shortwave radio is working normally, all circuits are in normal working state. When the shortwave portable antenna tuner is tuned, the FPGA clears the control pin of the magnetic latching relay to zero, so that the magnetic latching relay is in the lowest power consumption state, that is, Vset=0 and Vreset=0, and its current is I0;

[0052] Step 2: When the shortwave portable antenna tuner is in normal working state, if it receives an action command from the radio station within 10 seconds, it will continue to work normally; if it does not receive any action command from the radio station within 10 seconds, it will enter a dormant state.

[0053] Step 3: The hardware module of the shortwave portable antenna tuner enters the hardware sleep state, and the software module enters the software sleep state;

[0054] Step 4: When the shortwave portable antenna tuner enters the sleep state, the internal logic of the FPGA only retains an internal clock module and a wake-up communication module. The final ultra-low power consumption W1=V*, and the current is I0-I1-I2;

[0055] Step 5. Start the falling edge trigger mechanism. When the radio station sends data to the shortwave portable antenna tuner, the FPGA quickly wakes up all dormant hardware and software modules, allowing the shortwave portable antenna tuner to quickly enter normal working state. That is, the hardware Ven0=1, Ven1=1, addre=0x08 data is 0x00, Vreset0=1; the software reset0=1'b0, reset1=1'b0, reset2=1'b0, reset3=1'b0.

[0056] As a specific example, the hardware module described in step 3 enters the hardware sleep state as follows:

[0057] The FPGA of the shortwave portable antenna tuner sends the sleep command Ven0=0 to the crystal oscillator circuit to put the crystal oscillator into sleep mode; sends the 0x01 command to the address addre=0x08 of the ADC circuit through the SPI interface to put the ADC into power-off state; sends Ven1=0 to the power circuit to turn off part of the power supply; sends Vreset0=0 to the reset pin of the DDS circuit to put the DDS into reset state; finally, the hardware of the shortwave portable antenna tuner is put into ultra-low power consumption state, that is, the current saved by hardware sleep is I1.

[0058] As a specific example, the software module described in step 3 enters the software dormant state as follows:

[0059] The sleep and wake-up module of the shortwave portable antenna tuner sends a sleep command to the reset pin reset0=1'b1 of the soft core M1 module inside the FPGA to put it in a reset state; sends it to the reset pin reset1=1'b1 of the digital mixing, CIC filtering, down conversion, and Cordic vector impedance calculation modules to put them in a reset state; sends it to the reset pin reset2=1'b1 of the PLL system clock module inside the FPGA to put it in a reset state; sends it to the reset pin reset3=1'b1 of other FPGA design modules to put them in a reset state; finally, the software of the shortwave portable antenna tuner is put in an ultra-low power consumption state, that is, the current saved by software sleep is I2.

[0060] As a specific example, the trigger mechanism of the falling edge described in step 5 is as follows: Figure 3 As shown, the details are as follows:

[0061] When the shortwave portable antenna tuner is in sleep mode, the FPGA receives serial port commands sent by the radio station. The modulated serial port information of the radio station is demodulated into serial port information through the ASK demodulation circuit. Based on the characteristics that the first bit of the serial port data is 0 and the last bit is 1, a falling edge trigger mechanism is designed. When the radio station sends data to the shortwave portable antenna tuner, the serial port receive pin RX connected to the FPGA will inevitably have a falling edge. Since the FPGA's main clock uses 100MHz, the FPGA will consistently collect RX signals at a μs-level response speed. When a falling edge occurs, the serial port data of the ASK demodulation circuit is cached for communication.

[0062] The above are only preferred embodiments of the present invention. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principles of the present invention. These improvements and modifications should also be regarded as the scope of protection of the present invention.

Claims

1. A low-power shortwave portable antenna tuner, characterized in that: The hardware modules of the shortwave portable antenna tuner include FPGA, ADC circuit, DDS circuit, crystal oscillator circuit, power supply circuit, ASK modulation and demodulation circuit and magnetic latching relay circuit; The FPGA is the core processor of the shortwave portable antenna tuner, responsible for the control, communication and tuning functions of the shortwave portable antenna tuner; the ADC circuit is responsible for collecting voltage and current signals; the DDS circuit is responsible for providing tuning power; the crystal oscillator circuit is responsible for the system clock of the antenna tuner; the power supply circuit is responsible for the antenna tuner voltage conversion and voltage regulation to ensure the normal operating voltage of the antenna tuner; the ASK modulation and demodulation circuit is responsible for modulating and demodulating the communication data between the radio station and the antenna tuner; and the magnetic latching relay circuit is responsible for adjusting the antenna tuner network parameters.

2. The low-power shortwave portable antenna tuner according to claim 1, characterized in that: The FPGA is provided with software modules, including a sleep and wake-up module, a soft core M1 module, a vector impedance calculation module, a PLL system clock module and an FPGA design module.

3. A method for operating a low-power shortwave portable antenna tuner according to claim 1 or 2, characterized in that: The following steps are involved: Step 1: When the shortwave radio is working normally, all circuits are in normal working state. When the shortwave portable antenna tuner is tuned, the FPGA clears the control pin of the magnetic latching relay circuit to zero, so that the magnetic latching relay is in the lowest power consumption state. That is, the FPGA sends the SET pin Vset=0 and the RESET pin Vreset=0 of the magnetic latching relay circuit, and the current is I0. Step 2: When the shortwave portable antenna tuner is in normal working state, if it receives an action command from the radio station within time t1, it will continue to work normally; if it does not receive any action command from the radio station within time t1, it will enter a dormant state. Step 3: The hardware module of the shortwave portable antenna tuner enters the hardware sleep state, and the current saved by the hardware sleep state is I1; the software module enters the software sleep state, and the current saved by the software sleep state is I2; Step 4: When the shortwave portable antenna tuner enters the sleep state, the internal logic of the FPGA only retains a PLL system clock module and a sleep wake-up module, ultimately achieving ultra-low power consumption with a current of I0-I1-I2; Step 5: Start the falling edge trigger mechanism. When the radio station sends data to the shortwave portable antenna tuner, the FPGA wakes up all the hardware and software modules in the dormant state, so that the shortwave portable antenna tuner enters the normal working state.

4. The operating method of the low-power shortwave portable antenna tuner according to claim 3, characterized in that: The hardware module described in step 3 enters the hardware sleep state, as follows: The FPGA of the shortwave portable antenna tuner sends the sleep command Ven0=0 to the crystal oscillator circuit to put the crystal oscillator into sleep mode; Send the 0x01 instruction to the address addre=0x08 of the ADC circuit through the SPI interface to put the ADC into power-off state; Send the sleep command Ven1=0 to the power circuit to turn off part of the power supply; Send the reset pin Vreset0=0 to the DDS circuit to put the DDS in reset state; Ultimately, the hardware of the shortwave portable antenna tuner is in an ultra-low power consumption state.

5. The operating method of the low-power shortwave portable antenna tuner according to claim 4, characterized in that: The software module described in step 3 enters the software dormant state, as follows: The sleep wake-up module of the shortwave portable antenna tuner sends a sleep instruction to the reset pin reset0=1'b1 of the soft core M1 module inside the FPGA to put it in the reset state; where 1'b1 represents 1 bit width, binary system, and number 1; The reset pin reset1=1'b1 sent to the vector impedance calculation module puts it in reset state. The vector impedance calculation module includes digital mixing, CIC filtering, down conversion and Cordic; The reset pin reset2=1'b1 sent to the PLL system clock module inside the FPGA puts it in reset state; The reset pin reset3=1'b1 sent to the FPGA design module puts it in reset state; Ultimately, the software of the shortwave portable antenna tuner is in an ultra-low power consumption state.

6. The operating method of the low-power shortwave portable antenna tuner according to claim 5, characterized in that: The trigger mechanism of the falling edge described in step 5 is as follows: When the shortwave portable antenna tuner is in sleep mode, the FPGA receives the serial port command sent by the radio. The modulated serial port information of the radio is demodulated by the ASK demodulation circuit to obtain the serial port information. Based on the characteristics that the first bit of the serial port data is 0 and the last bit is 1, a falling edge trigger mechanism is designed. When the radio station sends data to the shortwave portable antenna tuner, a falling edge will occur on the serial port receive pin RX connected to the FPGA. The FPGA's main clock uses a frequency of 100MHz, and the FPGA consistently collects RX signals at a μs-level response speed. When a falling edge occurs, the serial port data of the ASK demodulation circuit is cached for communication.

7. The operating method of the low-power shortwave portable antenna tuner according to claim 6, characterized in that: In step 2, t1=10s.

8. The operating method of the low-power shortwave portable antenna tuner according to claim 6, characterized in that: In step 5, the shortwave portable antenna tuner enters normal working state, that is, the hardware module Ven0=1, Ven1=1, addre=0x08 data is 0x00, Vreset=1; the software module reset0=1'b0, reset1=1'b0, reset2=1'b0, reset3=1'b0, where 1'b0 represents 1 bit width, binary system, and number 0.

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