Multi-channel Ethernet and time-triggered TTP data conversion hardware platform

Abstract

The invention discloses a multi-channel Ethernet and TTP data conversion hardware platform. The multi-channel Ethernet and TTP data conversion hardware platform comprises a core processing module, a network data interface module, a TTP data interface module, a configuration and storage module, a power module, a clock module and a monitoring module. According to the invention, a more reliable and more efficient data conversion and transmission hardware platform can be provided for industrial intelligent manufacturing and system-level power management. The core processing module adopts FPGA + ARM isomerism, so that efficient protocol data conversion, high-speed data analysis and calculation and interface type interaction functions can be realized, and high efficiency of operation is ensured; the network interface module and the TTP data interface module can realize multi-channel data transmission of a network layer and a physical layer, so that the reliability of the data is ensured; and the configuration and storage module can realize storage of configuration information and monitoring acquisition data, so that the effectiveness of the information is protected. Compared with a traditional data conversion platform, the data conversion platform has the advantages of reliable protocol conversion, high function expansibility, large storage space, low data processing delay and the like.

Description

Technical Field

[0001] The invention belongs to the field of data converter, network and physical layer information processing, and is a hardware platform for realizing conversion and transmission of network protocol data and time-triggered TTP protocol data through multiple channels. Background Art

[0002] With technological innovation, interconnected devices widely use network communication, but it cannot guarantee the efficient and stable conversion of network data and device physical layer control commands. Sudden changes often occur in protocol conversion or data transmission, resulting in the control program of the upper computer cannot be accurately transmitted to the lower device. At the same time, it also causes the working status of the lower device to not be uploaded to the upper computer in time, and cannot effectively guarantee data transmission and storage, which aggravates the energy consumption of data processing.

[0003] In order to meet the requirements of efficient data protocol conversion and high-speed transmission, and high-reliability interaction from the host computer to the lower devices, the demand for high throughput of data storage and computing equipment, low data processing delay, large storage space capacity, and good compatibility with different systems is more urgent. Summary of the Invention

[0004] The purpose of the present invention is to meet the above-mentioned needs and provide a multi-channel Ethernet and time-triggered TTP data conversion hardware platform. The present invention is based on the intelligent interconnection requirements of devices under the Internet of Things. The core processing module adopts FPGA+ARM heterogeneity, which can realize efficient protocol data conversion, high-speed signal data analysis and calculation, and interface-type human-computer interaction functions to ensure efficient operation; the network and TTP data interface module can realize multi-channel data transmission at the network layer and physical layer to ensure data reliability; the configuration and storage module can realize the storage of device configuration information and monitoring and acquisition data to protect the validity of information. Compared with traditional data conversion platforms, the present invention has the advantages of reliable protocol data conversion, strong functional scalability, large storage space, and low data processing delay.

[0005] The specific technical solution for achieving the purpose of the present invention is:

[0006] A multi-channel Ethernet and time-triggered TTP data conversion hardware platform, which includes a core processing module, a network data interface module, a TTP data interface module, a configuration and storage module, a power module, a clock module and a monitoring module;

[0007] The core processing module is connected to the network data interface module, TTP data interface module, configuration and storage module, power module, clock module and monitoring module, and is used for data reception, storage, forwarding and protocol conversion;

[0008] The network interface module is connected to the core processing module, the power module and the clock module, and is used for transmitting network layer protocol data packets;

[0009] The TTP data interface module is connected to the core processing module, power module, clock module and monitoring signal, and is used for the transmission of physical layer TTP protocol data packets;

[0010] The configuration and storage module is connected to the core processing module, the power module, and the clock module, and is used for solidifying the configuration program of the core processing module and caching data processing;

[0011] The power supply module is connected to the core processing module, network data interface module, TTP data interface module, configuration and storage module, clock module and monitoring module, and is used to provide stable and reliable reference power to each module;

[0012] The clock module is connected to the core processing module, network data interface module, TTP data interface module, configuration and storage module and power module, and provides reference clocks for various chips of the core processing module, network data interface module, TTP data interface module and configuration and storage module;

[0013] The monitoring module is connected to the core processing module, the TTP data interface module and the power module, and is used to monitor the system program running status, power amplitude and startup timing and equipment operating temperature;

[0014] in:

[0015] The core processing module includes an ARM chip (model FS32K144HAT0MLLT) and an FPGA chip (model XCKU9P-2FFVE900E). The ARM and FPGA chips communicate via the SPI protocol, with information configuration and program curing completed via the configuration and storage module. The ARM chip receives information collected by the monitoring module to determine the system's operating status, provides feedback on reset control information, and implements host computer interface configuration. The FPGA chip converts TTP protocol packets into UDP and TCP / IP protocol packets, transmits network-layer data to the host computer via the network data interface module, and transmits physical-layer data to external devices via the TTP data interface module.

[0016] The network data interface module includes an RTL8211E-VB network PHY chip, an RJ45 jack, and a 10G SFP+ optical port. The network PHY chip connects to the RJ45 jack and the core processing module to enable the transmission and reception of 10 / 100 / 1000M network data packets. The 10G SFP+ optical port connects to the core processing module to enable the transmission and reception of 10G optical network data packets.

[0017] The TTP data interface module includes a bus-type TTP interface and a star-type TTP interface. The bus-type TTP interface includes an RS-485 PHY chip model SN75HVD10D, an isolation chip model ADUM120N, and an isolation power chip model DCR010503. The RS-485 PHY chip is connected to the core processing module via the isolation chip to implement a TTP bus-type architecture that complies with the RS-485 standard, and the signal frequency supports 4MHz; the isolation power chip converts the output of the power module into an isolation level to power the RS-485 PHY chip and the isolation chip. The star-type TTP interface includes a PMC connector model 5120525-1. The PMC connector is connected to the core processing module to implement a TTP star architecture, and the signal frequency supports 20MHz.

[0018] The configuration and storage module includes MT40A256M16GE-075E DDR4 chips, MT25QU01GBBB8ESF-0SIT FLASH memory, and MR25H40 MRAM memory. The DDR4 chips are connected to the core processing module, providing storage for the ARM chip and FPGA chip; the FLASH memory is connected to the core processing module and is used for programming the ARM and FPGA chips; and the MRAM memory is connected to the ARM chip, providing non-volatile storage for the device operating status information collected by the monitoring module.

[0019] The power module includes a DC-BUCK power supply chipset (TPS53355, TPS62130, and TPS51200) and a MAX8556 LDO chip. The power module provides power to the other modules, and power-on sequencing is controlled by the power-good pins of the power chips in the module.

[0020] The clock module includes a single-ended crystal oscillator model SiT8103, a differential crystal oscillator model SiT9120, and a frequency divider model HMC7044, providing reference clocks for various chips in the core processing module, network data interface module, TTP data interface module, and configuration and storage module.

[0021] The monitoring module includes a MAX16062 voltage monitoring chip, a MAX1989 temperature monitoring chip, and a MAX706 watchdog chip. These chips monitor the operating status of each module and generate reset signals in response to abnormal conditions. The voltage monitoring chip monitors the voltage levels output by the power module; the temperature monitoring chip monitors the operating temperature of the core processing module; and the watchdog chip monitors the program execution status of the core processing module.

[0022] The ARM chip in the core processing module processes the collected information from the monitoring module and confirms the device's operating status. The FPGA chip connects to the network data interface module via the ETH port and to the TTP data interface module via the HD and LVDS ports, enabling protocol data conversion and high-speed transmission. The ARM chip and FPGA chip communicate via the SPI port, allowing the ARM chip to monitor the FPGA chip's packet protocol conversion and data transmission status and provide feedback on reset signal control instructions to the monitoring module.

[0023] The network data interface module provides a total of 8 independent 10 / 100 / 1000M Ethernet interfaces composed of network port PHY chips and RJ45 sockets. All 8 network ports are connected to the ETH interface of the FPGA chip, which can realize gigabit transmission of network data packets; a total of 10G Ethernet interface composed of 10G SFP+ optical port is provided, and one optical port is connected to the GTH interface of the FPGA chip, which can realize 10G transmission of network data packets.

[0024] The TTP data interface module provides a total of 4 independent bus-type TTP interfaces composed of RS-485 PHY chips, with a signal frequency supporting 4MHz. The 4 bus interfaces are all connected to the HD port of the FPGA chip through an isolation chip. The isolation power chip powers the RS-485 PHY chip and the isolation chip to achieve electrical isolation between the bus-type TTP interface and the core processing module; a total of 10 groups of star-shaped TTP interfaces composed of FPGA chip LVDS ports are provided, with a signal frequency supporting 20MHz, and are connected to external expandable devices through PMC connectors.

[0025] The DDR4 particles in the configuration and storage module use two 4GB 16-bit DDR4 chips with a maximum speed of 2666Mb / s; the FLASH memory is used to configure the programs of the ARM chip and the FPGA chip. The single-chip capacity of the FLASH memory is 512Mb, and the two chips have a total capacity of 1Gb; the MRAM memory provides 4Mb of non-volatile storage for the monitoring information received by the ARM chip.

[0026] The power module can convert the external input 12V 10A DC source into 0.6V, 0.85V, 0.9V, 1.2V, 1.8V, 2.5V and 3.3V outputs, providing corresponding power for each module chip on the platform.

[0027] The clock module uses a single-ended crystal oscillator to generate a single-ended 50MHz, which is used for the FPGA chip to initialize the configuration of the divider, and then uses a differential crystal oscillator to generate a differential 125MHz as the divider input, generating two 125MHz, one 156.25MHz, one 300MHz and one 100MHz clock outputs.

[0028] The monitoring module provides monitoring and reset control of voltage, temperature, and program operation on the platform. The voltage monitoring chip monitors the amplitude and power-on timing of each voltage output by the power module, and determines that the threshold of the voltage output is within the standard 3% tolerance, otherwise it will be reset; the temperature monitoring chip monitors the operating temperature status of the core processing module. By placing a thermistor near the core processing module, the temperature monitoring chip can collect voltage signals that change with temperature, and reset if an abnormality occurs; the watchdog chip monitors the program operation status of the core processing module, and resets if an abnormality occurs. The monitored and collected equipment working information is transmitted to the ARM chip for storage and control on the one hand, and on the other hand, it is transmitted to the FPGA chip through the TTP data interface module. The FPGA chip converts it into a network data packet and uploads it to the host computer.

[0029] This paper uses Vivado, provided by Xilinx, to compile, synthesize, and generate bitstream files for the hardware description language (Verilog / VHDL) used by FPGA chips, fully utilizing the logic units on the FPGA chip to achieve high-speed data storage and forwarding. System configuration, multi-protocol processing, and serial port debugging of the ARM chip are implemented in C language within S32 Design Studio.

[0030] The beneficial effects of the present invention are:

[0031] a. The present invention is a heterogeneous processing system based on FPGA+ARM, which can process a large amount of high-speed data information such as network data packets, TTP data frames, etc. in parallel, and the processing delay can reach the nanosecond level;

[0032] b. The present invention is based on the widespread use of RS-485 protocol in industrial equipment and can support bus-type and star-type system architectures for device interconnection;

[0033] c. The present invention can be equipped with the clock synchronization algorithm, member confirmation algorithm and message scheduling algorithm related to the TTP protocol, supports the universal TTP frame format, and can achieve high reliability of the lower-level device receiving control instructions;

[0034] d. The present invention does not rely on any software platform, and all functional verification is achieved by hardware circuits. It has rich interface types, strong compatibility, and can adapt to complex test environments.

[0035] e. The present invention can provide a safer, more reliable and more efficient data protocol conversion and transmission platform for the network layer and the physical layer, and can also provide a powerful prototype verification platform for related chips required for data transmission and reception, data storage and data processing in various networks. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] Figure 1 It is a structural block diagram of the present invention;

[0037] Figure 2 Schematic diagram of the workflow of the present invention. DETAILED DESCRIPTION

[0038] The present invention will be described in detail below with reference to the accompanying drawings.

[0039] See Figure 1 ,The present invention is a multi-channel data conversion hardware platform based on FPGA+ARM heterogeneous.

[0040] The platform includes a core processing module 1, a network data interface module 2, a TTP data interface module 3, a configuration and storage module 4, a power supply module 5, a clock module 6 and a monitoring module 7.

[0041] The core processing module's ARM chip 11 processes the information collected by the monitoring module and confirms the device's operating status. This information is transmitted to the ARM chip 11 via I2C, and the MRAM storage module provides non-volatile storage for the collected information. The FPGA chip 12 connects to the network data interface module 2 via the ETH port and to the TTP data interface module 3 via the LVDS port, enabling protocol data conversion and high-speed transmission. The ARM chip 11 and FPGA chip 12 communicate via the SPI port, allowing the ARM chip 11 to obtain the operating status of the FPGA chip 12's data packet protocol conversion and data transmission, and to provide feedback to the monitoring module regarding reset signal control instructions.

[0042] The data interface module 2 provides a total of 8 independent 10 / 100 / 1000M Ethernet interfaces consisting of a network port PHY chip 21 and an RJ45 socket 22, which comply with the IEEE 802.3 standard for 10Base-T, 100Base-TX and 1000Base-T. The interface provides all necessary physical layer functions to transmit and receive Ethernet data packets through a CAT.5 UTP cable. All 8 network ports are connected to the ETH interface of the FPGA chip 12, enabling gigabit transmission of network data packets; it provides one independent 10G SFP+ optical port 23, with the interface TD and RD differential pair rates both at 10.3125 Gb / s. One optical port is connected to the GTH interface of the FPGA chip 12, enabling 10G transmission of network data packets.

[0043] The TTP data interface module 3 provides a total of 4 independent bus-type TTP interfaces composed of RS-485 PHY chips 31. The 4 bus interfaces are all connected to the 12 HD ports of the FPGA chip 12 through the isolation chip 32, realizing the conversion of 4 groups of RX, TX, and CTS signals into differential signals that comply with the RS-485 standard, and the signal frequency supports 4MHz; the isolation power chip supplies power to the RS-485 PHY chip and the isolation chip to realize the electrical isolation of the bus-type TTP interface and the core processing module; a total of 10 groups of star-shaped TTP interfaces composed of 12 LVDS ports of the FPGA chip are provided, and the signal frequency supports 20MHz. It can be connected to external expandable devices through the PMC connector 34. The bus interface 34 on the PMC connector can realize stable data transmission with real-time connection.

[0044] The configuration and storage module 4 uses DDR4 particles 41 to provide storage space for the ARM chip 11 and the FPGA chip 12; the FLASH memory 42 is used for program solidification and burning of the ARM chip 11 and the FPGA chip 12; the MRAM memory 43 is connected to the ARM chip 11 to provide non-volatile storage for the device working status information collected by the monitoring module 7.

[0045] The power module 5 can convert the external input 12V 10A DC source into 0.6V, 0.85V, 0.9V, 1.2V, 1.8V, 2.5V and 3.3V reference power outputs, providing corresponding power for each module chip on the platform. The power-on timing control is achieved by the power good pins of each power chip of the module.

[0046] The clock module 6 uses a single-ended crystal oscillator 61 to generate a single-ended 50MHz, which is used for the FPGA chip 12 to initialize the configuration of the divider 63, and then uses a differential crystal oscillator 62 to generate a differential 125MHz as the input of the divider 63, generating 2 125MHz, 1 156.25MHz, 1 300MHz and 1 100MHz clock outputs, providing corresponding reference clocks to the core processing module 1, the network data interface module 2, the TTP data interface module 3, and the configuration and storage module 4.

[0047] The monitoring module 7 provides platform voltage, temperature, and program execution monitoring and reset control. The voltage monitoring chip 71 monitors the voltage levels output by the power module, ensuring that the output voltage threshold is within the standard 3% tolerance. Otherwise, a reset is performed. The temperature monitoring chip 72 monitors the operating temperature of the core processing module. By placing a thermistor near the core processing module, the temperature monitoring chip collects temperature-dependent voltage signals and transmits them to the ARM chip 11. If an anomaly occurs, a reset is performed. The watchdog chip 73 monitors the program execution status of the core processing module and resets it if an anomaly occurs.

[0048] The information that needs to be preprocessed in the present invention is as follows:

[0049] Input the 10 / 100 / 1000M Ethernet interface and 10G SFP+ optical port number to be enabled in the core processing module of the present invention.

[0050] The port number of the TTP interface to be enabled is input into the core processing module of the present invention, and the TTP data frame format is preset.

[0051] The number of bytes and storage type of pre-stored data are input into the configuration and storage module of the present invention.

[0052] In the clock module frequency divider of the present invention, a single-ended 50 MHz and a differential 125 MHz are input and a clock frequency division ratio of 156.25 MHz, 300 MHz and 100 MHz is output.

[0053] The reference power supply standard value, the maximum operating temperature of the device and the watchdog timer are input into the monitoring configuration of the present invention.

[0054] The configuration is now complete.

[0055] See Figure 2 , the present invention works like this:

[0056] The user first powers on the entire hardware platform, converting the external input 12V or 10V DC source into multiple reference power supplies through the power module. The power-on sequence of the reference power supplies is determined by the power good pins of each power chip.

[0057] Next, the ARM chip configures the type and processing method for monitoring data collection and stores this program in MRAM. The data processing programs for the ARM and FPGA chips are stored in FLASH memory. If the configuration is not complete when data is received, the data is discarded. Once the configuration is complete, the device enters normal operating mode.

[0058] The host computer then begins verifying various data from the slave device. There are two operating modes: downlink transmission mode, in which the host computer transmits control information to the slave device; uplink transmission mode, in which the slave device transmits operating status information to the host computer. The following details both operating modes. The information carried in network packets and TTP data frames must be stored and calculated according to configuration requirements. The FPGA chip can use the DDR4 cache module for data storage when processing data.

[0059] In downlink transmission mode, control commands from the host computer are transmitted to the core processing module via a network protocol. These network packets can be transmitted in two ways: via a Gigabit Ethernet port, received via an RJ45 jack, translated by the Ethernet PHY chip, and then sent to the FPGA chip for processing; or via a 10G optical port, sent directly to the FPGA chip via a 10G SFP+ optical port. The FPGA converts network packets into TTP packets, specifically converting UDP and TCP / IP network protocol packets into TTP protocol data frames. After data conversion, TTP data frames are transmitted to the downstream device in two ways: In a bus-type interconnection architecture, data is output from the FPGA chip's HD port to the RS-485 PHY through a bus-type TTP interface, where it is translated and then sent to the downstream device. In a star-type interconnection architecture, data is output from the FPGA chip's LVDS port via a PMC connector to the downstream device.

[0060] In uplink transmission mode, the monitoring module collects the operating status information of lower-level devices and transmits it to the core processing module. This information is then transferred to the ARM chip for storage and reset control. Similarly to the TTP data frame transmission mode in uplink transmission mode, the operating status information is uploaded to the FPGA chip using a bus-type or star-type TTP interface. The FPGA then converts the TTP frames into network packets. Once the data conversion is complete, similar to the network packet transmission mode in uplink transmission mode, the FPGA uploads the network packets to the host computer via the Gigabit Ethernet port or 10G optical port.

Claims

1. A multi-channel Ethernet and time-triggered TTP data conversion hardware platform, characterized in that: The platform includes a core processing module (1), a network data interface module (2), a TTP data interface module (3), a configuration and storage module (4), a power module (5), a clock module (6) and a monitoring module (7); in: The core processing module (1) includes an ARM chip (11) of model FS32K144HAT0MLLT and an FPGA chip (12) of model XCKU9P-2FFVE900E; the ARM chip (11) and the FPGA chip (12) can communicate with each other through the SPI protocol port, and complete information configuration and solidification program through the configuration and storage module (4); the ARM chip (11) receives the collected information of the monitoring module (7) to judge the working state of the system, feedback reset control information, and realize the upper computer interface configuration; the FPGA chip (12) is used to realize the conversion of TTP protocol and UDP, TCP / IP protocol data packets, and can complete network layer data transmission to the upper computer through the network data interface module (2), and complete physical layer data transmission to the external device through the TTP data interface module (3); The network data interface module (2) includes a network port PHY chip (21) of model RTL8211E-VB, an RJ45 socket (22) and a 10G SFP+ optical port (23); the network port PHY chip (21) is connected to the RJ45 socket (22) and the core processing module (1) to realize the transmission and reception of 10 / 100 / 1000M network data packets; the 10G SFP+ optical port (23) is connected to the core processing module (1) to realize the transmission and reception of 10G optical network data packets; The TTP data interface module (3) includes a bus-type TTP interface and a star-type TTP interface; the bus-type TTP interface includes an RS-485 PHY chip (31) with a model number of SN75HVD10D, an isolation chip (32) with a model number of ADUM120N, and an isolation power chip (33) with a model number of DCR010503, wherein the RS-485 PHY chip (31) is connected to the core processing module (1) through the isolation chip (32) to realize a TTP bus-type architecture that complies with the RS-485 electrical standard, and the signal frequency supports 4MHz; the isolation power chip (33) converts the output of the power module (5) into an isolation level to power the RS-485 PHY chip (31) and the isolation chip (32); the star-type TTP interface includes a PMC connector (34) with a model number of 5120525-1, and the PMC connector (34) is connected to the core processing module (1) to realize a TTP star-type architecture, and the signal frequency supports 20MHz; The configuration and storage module (4) includes a DDR4 particle (41) of model MT40A256M16GE-075E, a FLASH memory (42) of model MT25QU01GBBB8ESF-0SIT, and an MRAM memory (43) of model MR25H40; the DDR4 particle (41) is connected to the core processing module (1) to provide storage space for the ARM chip (11) and the FPGA chip (12); the FLASH memory (42) is connected to the core processing module (1) to be used for program solidification and burning of the ARM chip (11) and the FPGA chip (12); the MRAM memory (43) is connected to the ARM chip (11) to provide non-volatile storage for the device working status information collected by the monitoring module (7); The power supply module (5) includes a DC-BUCK power supply chipset (51) of model TPS53355, TPS62130, and TPS51200 and an LDO chip (52) of model MAX8556; the power supply module (5) supplies power to the other modules, and power-on timing control is achieved by the power good pins of the power supply chips of the module; The clock module (6) includes a single-ended crystal oscillator (61) of model SiT8103, a differential crystal oscillator (62) of model SiT9120, and a frequency divider (63) of model HMC7044, which provide reference clocks for various chips of the core processing module, the network data interface module, the TTP data interface module, and the configuration and storage module; The monitoring module (7) includes a voltage monitoring chip (71) of model MAX16062, a temperature monitoring chip (72) of model MAX1989, and a watchdog chip (73) of model MAX706, which monitor the working status of each module and generate a reset signal corresponding to an abnormal situation; the voltage monitoring chip (71) monitors the voltages of each level output by the power module (5); the temperature monitoring chip (72) monitors the working temperature status of the core processing module (1); and the watchdog chip (73) monitors the program running status of the core processing module (1).

2. The multi-channel Ethernet and time-triggered TTP data conversion hardware platform according to claim 1, characterized in that: The ARM chip (11) of the core processing module (1) realizes the collected information processing and storage control of the monitoring module (7) and confirms the working status of the equipment; the FPGA chip (12) is connected to the network data interface module (2) through the ETH / GTH port and is connected to the TTP data interface module (3) through the HD / LVDS port to realize protocol data conversion and high-speed transmission functions; the ARM chip (11) and the FPGA chip (12) communicate through the SPI port to obtain the working status of the data packet protocol conversion and data transmission of the FPGA chip (12), and feedback the control instruction of the reset signal to the monitoring module (7).

3. The multi-channel Ethernet and time-triggered TTP data conversion hardware platform according to claim 1, characterized in that: The network data interface module (2) provides a total of 8 independent 10 / 100 / 1000M Ethernet interfaces composed of a network port PHY chip (21) and an RJ45 socket (22), and all 8 network interfaces are connected to the ETH interface of the FPGA chip (12), thereby realizing gigabit transmission of network data packets; and provides a total of 10G Ethernet interface composed of a 10G SFP+ optical port (23), and one optical port is connected to the GTH interface of the FPGA chip (12), thereby realizing 10G transmission of network data packets.

4. The multi-channel Ethernet and time-triggered TTP data conversion hardware platform according to claim 1, characterized in that: The TTP data interface module (3) provides a total of 4 bus-type TTP interfaces independently composed of RS-485 PHY chips (31), with a signal frequency supporting 4 MHz. The 4 bus interfaces are all connected to the FPGA chip (12) through the isolation chip (32). The isolation power chip (33) supplies power to the RS-485 PHY chip (31) and the isolation chip (32), thereby realizing electrical isolation between the bus-type TTP interface and the core processing module (1). A total of 10 groups of star-shaped TTP interfaces composed of LVDS ports of the FPGA chip (12) are provided, with a signal frequency supporting 20 MHz, and are connected to external expandable devices through the PMC connector (34).

5. The multi-channel Ethernet and time-triggered TTP data conversion hardware platform according to claim 1, characterized in that: The configuration and storage module (4) uses two 4GB 16-bit DDR4 chips as the DDR4 particles (41), with a maximum speed of 2666Mb / s; The FLASH memory (42) is used to configure the programs of the ARM chip (11) and the FPGA chip (12). The capacity of a single FLASH memory chip is 512Mb, and the total capacity of the two chips is 1Gb; The MRAM memory (43) provides 4Mb of non-volatile storage for the monitoring information received by the ARM chip (11).

6. The multi-channel Ethernet and time-triggered TTP data conversion hardware platform according to claim 1, characterized in that: The power supply module (5) can convert an external input 12V 10A DC source into 0.6V, 0.85V, 0.9V, 1.2V, 1.8V, 2.5V and 3.3V reference power outputs, providing corresponding reference power for each module chip on the platform.

7. The multi-channel Ethernet and time-triggered TTP data conversion hardware platform according to claim 1, characterized in that: The clock module (6) uses a single-ended crystal oscillator (61) to generate a single-ended 50 MHz, which is used for the FPGA chip (12) to initialize the configuration of the divider (63), and then uses a differential crystal oscillator (62) to generate a differential 125 MHz as the input of the divider (63), generating two 125 MHz, one 156.25 MHz, one 300 MHz and one 100 MHz clock outputs.

8. The multi-channel Ethernet and time-triggered TTP data conversion hardware platform according to claim 1, characterized in that: The monitoring module (7) provides monitoring and reset control of voltage, temperature, and program operation, and transmits the working information to the ARM chip (11) for storage and control on the one hand, and transmits it to the FPGA chip (12) through the TTP data interface module (3) on the other hand. The FPGA chip (12) converts it into a network data packet and uploads it to the host computer; the voltage monitoring chip (71) monitors the voltage amplitude and power-on timing of each level output by the power module (5), and determines that the voltage output threshold is within the standard 3% tolerance, otherwise it is reset; the temperature monitoring chip (72) monitors the working temperature state of the core processing module (1), and by placing a thermistor near the core processing module (1), the temperature monitoring chip (72) collects the voltage signal that changes with temperature, and resets if an abnormality occurs; the watchdog chip (73) monitors the program operation of the core processing module (1), and resets if an abnormality occurs.

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