HEMT (High Electron Mobility Transistor) power device based on single field plate and preparation method

Abstract

The invention relates to an HEMT (High Electron Mobility Transistor) power device based on a single field plate and a preparation method. The HEMT power device based on the single field plate comprises a substrate; an epitaxial layer; a source ohmic contact electrode; a drain ohmic contact electrode; an insulating layer or a first gate layer; a gate passivation layer; the grid opening penetrates through the grid passivation layer to reach the insulating layer or the first grid layer; the gate field plate is arranged on the gate passivation layer; wherein the gate passivation layer is formed by arranging SiN and / or SiO2 on the barrier layer through a low-pressure chemical vapor deposition method or an inductively coupled plasma-chemical vapor deposition method. According to the HEMT power device, the compactness of the gate passivation layer is better, and the surface passivation effect is better, so that more uniform electric field distribution can be obtained in a single field plate structure jointly formed by the gate opening and the gate field plate, the obtained HEMT power device based on the single field plate has a better voltage withstanding result, and meanwhile, the HEMT power device based on the single field plate is simple in process, low in manufacturing cost and easy to popularize. And the reliability is higher.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor devices, and in particular to a HEMT power device based on a single field plate and a preparation method thereof. Background Art

[0002] In recent years, GaN high electron mobility transistors (GaN HEMTs) have been able to change power systems due to their high efficiency and miniaturization. Their wide bandgap and high electron drift rate give them an excellent Baliga quality factor, which enables GaN HEMT power devices to operate at high voltage, high frequency switching, and high temperature, and can provide low on-resistance and switching losses. They have good application prospects in consumer electronics, industrial, automotive and other fields.

[0003] High-voltage GaN HEMT power devices can simplify the topology of power supply systems, reduce the number of components, and thus increase power density. This increased withstand voltage reduces the risk of device failure under high-voltage transients and effectively suppresses device degradation caused by overshoot voltage. To increase the withstand voltage, multi-layer field plate technology is often used in GaN HEMT power devices to optimize the electric field distribution and reduce electric field spikes, thereby increasing the withstand voltage. In applications with a withstand voltage of 650V and above, GaN HEMT power devices generally use a three-field plate design, resulting in a withstand voltage that significantly exceeds the voltage across the device during application. This higher withstand voltage margin allows for a shorter gate-drain spacing in the design, thereby reducing device area and lowering costs. The process for HEMT power devices with a multi-field plate structure needs further simplification. Summary of the Invention

[0004] In view of this, the present invention provides a HEMT power device based on a single field plate and a preparation method thereof, aiming to simplify the process of HEMT power devices based on a multi-field plate structure and reduce manufacturing costs.

[0005] To achieve the above objectives, in a first aspect, the present invention provides a HEMT power device based on a single field plate, comprising:

[0006] substrate;

[0007] an epitaxial layer, comprising a buffer layer, a channel layer, and a barrier layer sequentially arranged on the substrate in a direction away from the substrate;

[0008] a source ohmic contact electrode, disposed on the channel layer and forming a source ohmic contact with the two-dimensional electron gas between the barrier layer and the channel layer;

[0009] a drain ohmic contact electrode, disposed on the channel layer and forming a drain ohmic contact with the two-dimensional electron gas between the barrier layer and the channel layer;

[0010] an insulating layer or a first gate layer, disposed on the barrier layer, wherein the first gate layer is spaced apart from the source ohmic contact electrode and the drain ohmic contact electrode;

[0011] a gate passivation layer, disposed on the insulating layer or covering the gate layer;

[0012] A gate opening is formed by etching the gate passivation layer;

[0013] a gate field plate, disposed on the gate passivation layer and located between the source ohmic contact electrode and the drain ohmic contact electrode, the gate field plate covering and filling the gate opening and forming a Schottky contact with the gate passivation layer, and an end of the gate field plate close to the drain ohmic contact electrode exceeding an end of the gate opening close to the drain ohmic contact electrode;

[0014] The gate passivation layer is formed by disposing SiN and / or SiO2 on the barrier layer by low pressure chemical vapor deposition or inductively coupled plasma-chemical vapor deposition.

[0015] In one embodiment, the contact resistance of the source ohmic contact electrode and the drain ohmic contact electrode is less than 1 ohm*mm; and / or

[0016] The distance between the gate opening and the barrier layer is 10 nm to 60 nm; and / or

[0017] The length of the end of the gate field plate close to the drain ohmic contact electrode beyond the end of the gate opening close to the drain ohmic contact electrode is 2 μm-10 μm.

[0018] In one embodiment, the HEMT power device based on a single field plate further includes a device isolation region, which is arranged outside the active area. The formation of the device isolation region includes injecting F ions or N ions into the epitaxial layer by ion implantation, or etching the epitaxial layer.

[0019] In one embodiment, the ion implantation depth or etching depth of the device isolation region reaches the buffer layer.

[0020] In one embodiment, the single field plate-based HEMT power device further includes a passivation layer, which is disposed on the gate passivation layer and covers the source ohmic contact electrode, the drain ohmic contact electrode, the gate field plate, and the device isolation region.

[0021] In one embodiment, the thickness of the passivation layer is 100 nm-6000 nm; and / or

[0022] The HEMT power device based on a single field plate further includes:

[0023] a source via hole, the source via hole penetrating the passivation layer and the gate passivation layer to reach a surface of the source ohmic contact electrode;

[0024] a drain via hole, the drain via hole penetrating the passivation layer and the gate passivation layer to reach a surface of the drain ohmic contact electrode;

[0025] a source interconnect metal electrode, disposed on the passivation layer and electrically connected to the source ohmic contact electrode through the source via hole;

[0026] The drain interconnect metal electrode is disposed on the passivation layer and is electrically connected to the drain ohmic contact electrode through the drain via hole.

[0027] In one embodiment, the material and forming method of the insulating layer are the same as those of the gate passivation layer, or SiN is formed by in situ growth; and / or

[0028] The material of the substrate includes Si, SiC or sapphire; and / or

[0029] The material of the buffer layer includes one or more of AlN, GaN and AlGaN; and / or

[0030] The material of the channel layer includes one or more of AlN, GaN, InGaN, InAlN, InAlGaN and AlGaN; and / or

[0031] The material of the barrier layer includes one or more of AlGaN, AlN, InAlN and InAlGaN; and / or

[0032] The material of the passivation layer includes one or more of SiN, SiO2 and SiON, or one or more of AlN, Al2O3 and AlON; and / or

[0033] The material of the source interconnect metal electrode includes one or more of Ti, Al, Au, TiN, Ta, TaN, Cu and AlCu; and / or

[0034] The material of the source ohmic contact electrode includes one or more of Ti, Al and TiN, or one or more of Ti, Al, Ni, Au and Mo, or one or more of Ta, Al and TaN; and / or

[0035] The material of the gate field plate includes one or more of Ti, Al, AlCu, TiN, Ni, Pt, Au, Ir, Ru, Ta, TaN, W, Zr, Mo, Rh, Pd, Pb, Os, Cu, Ag and ITO; and / or

[0036] The material of the drain ohmic contact electrode includes one or more of Ti, Al and TiN, or one or more of Ti, Al, Ni, Au and Mo, or one or more of Ta, Al and TaN; and / or

[0037] The material of the drain interconnect metal electrode includes one or more of Ti, Al, Au, TiN, Ta, TaN, Cu and AlCu.

[0038] In a second aspect, the present invention provides a method for preparing a HEMT power device based on a single field plate, comprising:

[0039] Providing a substrate and a buffer layer material, a channel layer material, and a barrier layer material, and sequentially disposing the buffer layer material, the channel layer material, and the barrier layer material on the substrate to form a buffer layer, a channel layer, and a barrier layer;

[0040] Providing a source ohmic contact electrode material and a drain ohmic contact electrode material, respectively disposed on the barrier layer to form a source ohmic contact electrode and a drain ohmic contact electrode, wherein the source ohmic contact electrode and the drain ohmic contact electrode form ohmic contact with the two-dimensional electron gas between the barrier layer and the channel layer;

[0041] Providing an insulating layer material or p-type doped PGaN, disposed on the barrier layer to form an insulating layer, wherein the gate layer is spaced apart from the source ohmic contact electrode and the drain ohmic contact electrode;

[0042] Providing SiN and / or SiO2, and disposing the SiN and / or SiO2 on the insulating layer or covering the first gate layer by low pressure chemical vapor deposition or inductively coupled plasma-chemical vapor deposition to form a gate passivation layer;

[0043] Etching the gate passivation layer to form a gate opening;

[0044] A gate field plate material is provided and disposed on the gate passivation layer to form a gate field plate between the source ohmic contact electrode and the drain ohmic contact electrode. The gate field plate covers and fills the gate opening and forms a Schottky contact with the gate passivation layer.

[0045] In one embodiment, the providing of the insulating layer material, disposed on the barrier layer (203) to form the insulating layer (401), comprises:

[0046] Providing SiN and / or SiO2, disposing the SiN and / or SiO2 on the barrier layer by low pressure chemical vapor deposition (LPCVD) or inductively coupled plasma chemical vapor deposition (ICPCVD), or disposing the SiN on the barrier layer by in-situ growth to form an insulating layer; and / or

[0047] The preparation method further comprises:

[0048] Providing F ions or N ions, and implanting the F ions or N ions into the buffer layer, the channel layer, and the barrier layer outside the active area to form a device isolation region; or

[0049] The buffer layer, the channel layer and the barrier layer are etched to form a device isolation region.

[0050] In one embodiment, it further includes:

[0051] Providing a passivation layer material, disposed on the gate passivation layer to form a passivation layer, wherein the passivation layer covers the source ohmic contact electrode, the drain ohmic contact electrode, the gate field plate and the device isolation region;

[0052] Etching the passivation layer and the gate passivation layer to form a source via hole and a drain via hole, wherein the source via hole and the drain via hole penetrate the passivation layer and the gate passivation layer and reach the surfaces of the source ohmic contact electrode and the drain ohmic contact electrode respectively;

[0053] A source interconnect metal electrode material and a drain interconnect metal electrode material are provided, respectively arranged on the passivation layer, and form a source interconnect metal electrode and a drain interconnect metal electrode, respectively. The source interconnect metal electrode is electrically connected to the source ohmic contact electrode through the source via, and the drain interconnect metal electrode is electrically connected to the drain ohmic contact electrode through the drain via.

[0054] In the present invention, the gate passivation layer is formed by forming SiN and / or SiO2 by low-pressure chemical vapor deposition (LPCVD) or inductively coupled plasma-chemical vapor deposition (ICPCVD), so that the gate passivation layer can have better compactness and surface passivation effect, thereby enabling a more uniform electric field distribution to be obtained in a single field plate structure (FP1) formed by a gate opening and a gate field plate, so that the obtained HEMT power device based on the single field plate has a better withstand voltage result, and at the same time, the process is simple, the manufacturing cost is low, and the reliability is higher. BRIEF DESCRIPTION OF THE DRAWINGS

[0055] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative work.

[0056] Figure 1 1 is a schematic structural diagram of a HEMT power device based on a single field plate provided in Example 1 of the present invention;

[0057] Figure 2 1 is a schematic structural diagram of a HEMT power device based on a single field plate provided in Example 2 of the present invention;

[0058] Figure 3 1 is a schematic structural diagram of a HEMT power device based on a single field plate provided in Comparative Example 1 of the present invention;

[0059] Figure 4 The results of the off-state withstand voltage test of the HEMT devices of Example 1 and Comparative Example 1 of the present invention are shown in FIG. Figure 4 (a) is the off-state withstand voltage test result of the HEMT device of Example 1, Figure 4 (b) is the turn-off withstand voltage test result of the HEMT device of Comparative Example 1.

[0060] Explanation of the accompanying drawings: substrate-1; epitaxial layer-2; buffer layer-201; channel layer-202; barrier layer-203; gate passivation layer-301; passivation layer-302; source interconnect metal electrode-303; source via-304; source ohmic contact electrode-305; gate opening-306; first gate layer-307; gate field plate-308; drain interconnect metal electrode-309; drain via-310; drain ohmic contact electrode-311; device isolation region-312; second gate field plate-313; third gate field plate-314. DETAILED DESCRIPTION

[0061] The technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without making creative work are within the scope of protection of the present invention. In addition, it should be understood that the specific embodiments described herein are only used to illustrate and explain the present invention and are not used to limit the present invention.

[0062] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the art to which this invention pertains. The terms used herein in the specification of the present invention are for the purpose of describing specific embodiments only and are not intended to limit the present invention. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0063] In this disclosure, unless otherwise indicated, directional terms such as "upper" and "lower" generally refer to the upper and lower positions of a device in actual use or operation, specifically in the directions of the drawings in the accompanying drawings; whereas "inner" and "outer" refer to the outline of the device. Furthermore, in the description of this disclosure, the term "including" means "including but not limited to." Terms such as first, second, and third are used merely as labels and do not impose numerical requirements or establish a sequential order.

[0064] In the present invention, "and / or" describes the association relationship between associated objects, indicating that three relationships can exist. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. A and B can be singular or plural.

[0065] In the present invention, "at least one" means one or more, and "plurality" means two or more. "One or more", "at least one of the following" or similar expressions refer to any combination of these items, including any combination of single or plural items. For example, "at least one of a, b, or c", or "at least one of a, b, and c" can all mean: a, b, c, ab (i.e., a and b), ac, bc, or abc, where a, b, and c can be single or plural, respectively.

[0066] Various embodiments of the present invention may be presented in the form of a range; it should be understood that the description in a range format is only for convenience and brevity and should not be construed as an inflexible limitation on the scope of the invention; therefore, the range description should be considered to have specifically disclosed all possible subranges and single numerical values within the range. For example, the description of a range from 1 to 6 should be considered to have specifically disclosed subranges such as from 1 to 3, from 1 to 4, from 1 to 5, from 2 to 4, from 2 to 6, from 3 to 6, etc., as well as single numbers within the range, such as 1, 2, 3, 4, 5, and 6, regardless of the range. In addition, whenever a numerical range is indicated herein, it is intended to include any cited numeral (fractional or integer) within the indicated range.

[0067] The technical solutions of the present invention are as follows:

[0068] First, see Figure 1-Figure 2The present invention provides a HEMT power device based on a single field plate, comprising:

[0069] Substrate 1;

[0070] The epitaxial layer 2 includes a buffer layer 201, a channel layer 202, and a barrier layer 203 sequentially arranged on the substrate in a direction away from the substrate 1;

[0071] a source ohmic contact electrode 305 , disposed on the channel layer 202 and forming a source ohmic contact with the two-dimensional electron gas between the barrier layer 203 and the channel layer 202 ;

[0072] a drain ohmic contact electrode 311 , disposed on the channel layer 202 and forming a drain ohmic contact with the two-dimensional electron gas between the barrier layer 203 and the channel layer 202 ;

[0073] An insulating layer 401 or a first gate layer 307 is provided on the barrier layer 203, and the first gate layer is spaced apart from the source ohmic contact electrode (305) and the drain ohmic contact electrode (311);

[0074] A gate passivation layer 301 is disposed on the insulating layer 401 or covers the gate layer 307;

[0075] A gate opening 306 is formed by etching the gate passivation layer 301;

[0076] a gate field plate 308 disposed on the gate passivation layer 301 and located between the source ohmic contact electrode 305 and the drain ohmic contact electrode 311 ; the gate field plate 308 covers and fills the gate opening 306 and forms a Schottky contact with the gate passivation layer 301 ; an end of the gate field plate 308 close to the drain ohmic contact electrode 311 extends beyond an end of the gate opening 306 close to the drain ohmic contact electrode 311 ;

[0077] The gate passivation layer 301 is formed by depositing SiN and / or SiO 2 on the barrier layer 203 by low pressure chemical vapor deposition or inductively coupled plasma-chemical vapor deposition.

[0078] In the present invention, the gate passivation layer 301 is formed by forming SiN and / or SiO2 by low-pressure chemical vapor deposition (LPCVD) or inductively coupled plasma-chemical vapor deposition (ICPCVD), so that the gate passivation layer 301 can have better density and surface passivation effect, thereby enabling a more uniform electric field distribution to be obtained in the single field plate structure (FP1) formed by the gate opening 306 and the gate field plate 308, so that the HEMT power device based on the single field plate has better voltage resistance. At the same time, the process is simple, the manufacturing cost is low, and the reliability is higher.

[0079] In the present invention, ICPCVD has a low-temperature characteristic, which can prevent damage to the material surface.

[0080] The HEMT power device with a single field plate structure (FP1) in the present invention is more convenient than the HEMT power device with a multi-field plate structure (such as Figure 3 The GaN HEMT power device (FP1 / FP2 / FP3) has the same withstand voltage as the GaN HEMT power device with a simpler structure and is easier to implement. Therefore, compared with the GaN HEMT power device with a multi-field plate structure, the HEMT power device based on the single field plate structure of the present invention simplifies the process and reduces the manufacturing cost. At the same time, due to fewer film layers and a simpler structure, its reliability can also be improved, and it has the prospect of large-scale industrial mass production.

[0081] In one embodiment, the contact resistance between the source ohmic contact electrode 305 and the drain ohmic contact electrode 311 is less than 1 ohm*mm, thereby improving device performance and practicality.

[0082] In one embodiment, the distance between the gate opening 306 and the barrier layer 203 is 10 nm-60 nm, for example, 10 nm, 15 nm, 20 nm, 25 nm, 30 nm, 35 nm, 40 nm, 45 nm, 50 nm, 55 nm, 60 nm, etc. The distance between the gate opening 306 and the barrier layer 203 refers to the distance between the side of the gate opening 306 closer to the insulating layer 401 and the side of the barrier layer 203 closer to the insulating layer 401, that is, the surface-to-surface distance.

[0083] In one embodiment, the length of the gate field plate 308 protruding from the gate opening 306 proximate to the drain ohmic contact electrode 311 is 2 μm to 10 μm, for example, 2 μm, 3 μm, 4 μm, 5 μm, 6 μm, 7 μm, 8 μm, 9 μm, 10 μm, etc. In this way, the field plate structure can achieve uniform electric field distribution.

[0084] In one embodiment, the HEMT power device based on a single field plate further includes a device isolation region 312, which is disposed outside the active region. The formation of the device isolation region 312 includes implanting F ions or N ions into the epitaxial layer 2 by ion implantation, or etching the epitaxial layer 2.

[0085] In one embodiment, the ion implantation depth or etching depth of the device isolation region 312 reaches the buffer layer 201 .

[0086] In one embodiment, the single field plate-based HEMT power device further includes a passivation layer 302 , which is disposed on the gate passivation layer 301 and covers the source ohmic contact electrode 305 , the drain ohmic contact electrode 311 , the gate field plate 308 , and the device isolation region 312 .

[0087] In one embodiment, the thickness of the passivation layer 302 is 100 nm-6000 nm, for example, 100 nm, 300 nm, 500 nm, 700 nm, 1000 nm, 2000 nm, 3000 nm, 4000 nm, 5000 nm, 6000 nm, etc.

[0088] In one embodiment, the HEMT power device based on a single field plate further includes:

[0089] a source via hole 304 , the source via hole 304 penetrating the passivation layer 302 and the gate passivation layer 301 to reach the surface of the source ohmic contact electrode 305 ;

[0090] a drain via hole 310 , the drain via hole 310 penetrating the passivation layer 302 and the gate passivation layer 301 to reach the surface of the drain ohmic contact electrode 311 ;

[0091] A source interconnect metal electrode 303 is disposed on the passivation layer 302 and is electrically connected to the source ohmic contact electrode 305 through the source via 304;

[0092] The drain interconnect metal electrode 309 is disposed on the passivation layer 302 and is electrically connected to the drain ohmic contact electrode 311 through the drain via 310 .

[0093] In one embodiment, the material and formation method of the insulating layer 401 are the same as those of the gate passivation layer 301 , or SiN is formed by in situ growth.

[0094] In one embodiment, the substrate 1 is made of Si, SiC or sapphire.

[0095] In one embodiment, the material of the buffer layer 201 includes one or more of AlN, GaN and AlGaN.

[0096] In one embodiment, the material of the channel layer 202 includes one or more of AlN, GaN, InGaN, InAlN, InAlGaN and AlGaN.

[0097] In one embodiment, the material of the barrier layer 203 includes one or more of AlGaN, AlN, InAlN and InAlGaN.

[0098] In one embodiment, the material of the passivation layer 302 includes one or more of SiN, SiO 2 and SiON, or one or more of AlN, Al 2 O 3 and AlON.

[0099] The material of the source interconnection metal electrode 303 includes one or more of Ti, Al, Au, TiN, Ta, TaN, Cu and AlCu.

[0100] In one embodiment, the material of the source ohmic contact electrode 305 includes one or more of Ti, Al, and TiN, or one or more of Ti, Al, Ni, Au, and Mo, or one or more of Ta, Al, and TaN.

[0101] In one embodiment, the material of the gate field plate 308 includes one or more of Ti, Al, AlCu, TiN, Ni, Pt, Au, Ir, Ru, Ta, TaN, W, Zr, Mo, Rh, Pd, Pb, Os, Cu, Ag and ITO.

[0102] In one embodiment, the material of the drain ohmic contact electrode 311 includes one or more of Ti, Al, and TiN, or one or more of Ti, Al, Ni, Au, and Mo, or one or more of Ta, Al, and TaN.

[0103] In one embodiment, the material of the drain interconnect metal electrode 309 includes one or more of Ti, Al, Au, TiN, Ta, TaN, Cu and AlCu.

[0104] In a second aspect, the present invention provides a method for preparing a HEMT power device based on a single field plate, comprising:

[0105] Providing a substrate 1 and a buffer layer material, a channel layer material, and a barrier layer material, and sequentially disposing the buffer layer material, the channel layer material, and the barrier layer material on the substrate 1 to form a buffer layer 201, a channel layer 202, and a barrier layer 203;

[0106] Providing a source ohmic contact electrode material and a drain ohmic contact electrode material, respectively disposed on the barrier layer 203 to form a source ohmic contact electrode 305 and a drain ohmic contact electrode 311, wherein the source ohmic contact electrode 305 and the drain ohmic contact electrode 311 form ohmic contacts with the two-dimensional electron gas between the barrier layer 203 and the channel layer 202;

[0107] Providing an insulating layer material or a first gate layer material, and disposing it on the barrier layer 203 to form an insulating layer 401 or a first gate layer 307, wherein the first gate layer is spaced apart from the source ohmic contact electrode (305) and the drain ohmic contact electrode (311);

[0108] Providing SiN and / or SiO2, and disposing the SiN and / or SiO2 on the insulating layer 401 or covering the gate layer 307 by low pressure chemical vapor deposition (LPCVD) or inductively coupled plasma chemical vapor deposition (ICPCVD) to form a gate passivation layer 301;

[0109] Etching the gate passivation layer 301 to form a gate opening 306;

[0110] A gate field plate material is provided and disposed on the gate passivation layer 301 to form a gate field plate 308 between the source ohmic contact electrode 305 and the drain ohmic contact electrode 311 . The gate field plate 308 covers and fills the gate opening 306 and forms a Schottky contact with the gate passivation layer 301 .

[0111] In one embodiment, the insulating layer material is provided on the barrier layer 203 to form the insulating layer 401, including:

[0112] Provide SiN and / or SiO2, and set the SiN and / or SiO2 on the barrier layer 203 by low pressure chemical vapor deposition (LPCVD) or inductively coupled plasma-chemical vapor deposition (ICPCVD), or set the SiN on the barrier layer 203 by in-situ growth to form an insulating layer 401.

[0113] In one embodiment, the gate-first layer 307 is p-type doped PGaN or metal.

[0114] In one embodiment, it further includes:

[0115] Providing F ions or N ions, and implanting the F ions or N ions into the buffer layer 201, the channel layer 202, and the barrier layer 203 outside the active area to form a device isolation region 312; or

[0116] The buffer layer 201 , the channel layer 202 and the barrier layer 203 are etched to form a device isolation region 312 .

[0117] In one embodiment, it further includes:

[0118] Providing a passivation layer material, disposed on the gate passivation layer 301 to form a passivation layer 302, wherein the passivation layer 302 covers the source ohmic contact electrode 305, the drain ohmic contact electrode 311, the gate field plate 308 and the device isolation region 312;

[0119] Etching the passivation layer 302 and the gate passivation layer 301 to form a source via hole 304 and a drain via hole 310 , wherein the source via hole 304 and the drain via hole 310 penetrate the passivation layer 302 and the gate passivation layer 301 and reach the surfaces of the source ohmic contact electrode 305 and the drain ohmic contact electrode 311 , respectively;

[0120] A source interconnect metal electrode material and a drain interconnect metal electrode material are provided and respectively arranged on the passivation layer 302 to form a source interconnect metal electrode 303 and a drain interconnect metal electrode 309, respectively. The source interconnect metal electrode 303 is electrically connected to the source ohmic contact electrode 305 through the source via 304, and the drain interconnect metal electrode 309 is electrically connected to the drain ohmic contact electrode 311 through the drain via 310.

[0121] The materials used in the method for preparing the HEMT power device based on a single field plate of the present invention are as described above.

[0122] Example 1

[0123] A HEMT power device based on a single field plate (such as Figure 1 As shown) and a preparation method thereof, comprising the following steps:

[0124] (1) growing an epitaxial layer 2 on a substrate 1, wherein the epitaxial layer 2 includes a buffer layer 201 (buffer layer), a channel layer 202 (channel layer), and a barrier layer 203 (barrier layer) in a direction away from the substrate 1;

[0125] (2) depositing a source ohmic contact electrode 305 and a drain ohmic contact electrode 311 on the epitaxial layer 2, and forming an ohmic contact between the source ohmic contact electrode 305 and the drain ohmic contact electrode 311 and the two-dimensional electron gas between the barrier layer 203 and the channel layer 202;

[0126] (3) Providing SiN and forming an insulating layer 401 on the barrier layer 203 (barrier layer) by in situ growth;

[0127] (4) providing SiN, and disposing the SiN on the barrier layer 203 by inductively coupled plasma-chemical vapor deposition (ICP-CVD) to form a gate passivation layer 301 with a thickness of 150 nm;

[0128] (5) etching the gate passivation layer 301 to form a gate opening 306. The depth of the gate opening 306 (from the gate passivation layer 301 to the substrate 1) is 120 nm. The gate opening 306 is located close to the insulating layer 401 and is 30 nm away from the barrier layer 203 close to the insulating layer 401.

[0129] (6) A gate field plate 308 is deposited on the gate passivation layer 301, and the metal material of the gate field plate 308 covers and fills the gate opening 306. The gate field plate 308 is close to one end of the drain ohmic contact electrode 311 (corresponding to Figure 1 The right end in FIG) extends beyond the gate opening 306 and is close to the end of the drain ohmic contact electrode 311 (corresponding to Figure 1 The length of the right end in ( ) is 5.5 μm;

[0130] (7) F ions are implanted into the epitaxial layer 2 by ion implantation to form a device isolation region 312;

[0131] (8) depositing a passivation layer 302 on the gate passivation layer 301 , wherein the passivation layer 302 covers the source ohmic contact electrode 305 , the drain ohmic contact electrode 311 , the gate field plate 308 and the device isolation region 312 ;

[0132] (9) etching the passivation layer 302 and the gate passivation layer 301 to form a source via 304 and a drain via 310, respectively, wherein the source via 304 and the drain via 310 reach the surfaces of the source ohmic contact electrode 305 and the drain ohmic contact electrode 311, respectively;

[0133] (10) A source interconnect metal electrode 303 and a drain interconnect metal electrode 309 are deposited on the passivation layer 302 . The source interconnect metal electrode 303 is electrically connected to the source ohmic contact electrode 305 through the source via 304 . The drain interconnect metal electrode 309 is electrically connected to the drain ohmic contact electrode 311 through the drain via 310 .

[0134] Example 2

[0135] like Figure 2 As shown, this embodiment is basically the same as embodiment 1, except that, in this embodiment, the insulating layer 401 is eliminated, and a gate layer 307 (made of p-type doped PGaN or metal) is formed on the barrier layer 203, and the gate layer is spaced apart from the source ohmic contact electrode and the drain ohmic contact electrode, and the gate field plate 308 is close to one end of the drain ohmic contact electrode 311 (corresponding to Figure 1 The right end in FIG) exceeds the first gate layer 307 close to the drain ohmic contact electrode 311 (corresponding to Figure 1 on the right side of the image).

[0136] Comparative Example 1

[0137] like Figure 3 As shown, this comparative example is substantially the same as Example 1, except that a second gate field plate 313 ( FP2 ) and a third gate field plate 314 ( FP3 ) are further formed in the passivation layer 302 in this comparative example.

[0138] Test Case

[0139] The HEMT devices of Example 1 and Comparative Example 1 were subjected to a turn-off withstand voltage test (the gate-source voltage was less than the threshold voltage, and a bias of 0-3000V was applied to the gate-drain voltage). The test results are shown in FIG. Figure 4 As shown, Figure 4 (a) is the off-state withstand voltage test result of the HEMT device of Example 1, wherein Figure 4 (b) is the turn-off withstand voltage test result of the HEMT device of Comparative Example 1.

[0140] from Figure 4 It can be seen that the HEMT device with a single field plate structure (FP1) of the present invention has the same level of withstand voltage as the HEMT device with a three-field plate structure (FP1 / FP2 / FP3) in Comparative Example 1, but its structure is simpler and easier to implement.

Claims

1. A HEMT power device based on a single field plate, characterized in that: include: substrate (1); An epitaxial layer (2), comprising a buffer layer (201), a channel layer (202), and a barrier layer (203) sequentially arranged on the substrate in a direction away from the substrate (1); A source ohmic contact electrode (305) is provided on the channel layer (202) and forms a source ohmic contact with the two-dimensional electron gas between the barrier layer (203) and the channel layer (202); A drain ohmic contact electrode (311) is provided on the channel layer (202) and forms a drain ohmic contact with the two-dimensional electron gas between the barrier layer (203) and the channel layer (202); An insulating layer (401) or a first gate layer (307) is provided on the barrier layer (203), and the first gate layer is spaced apart from the source ohmic contact electrode (305) and the drain ohmic contact electrode (311); A gate passivation layer (301) is disposed on the insulating layer (401) or covers the gate layer (307); A gate opening (306) is formed by etching the gate passivation layer (301); a gate field plate (308) disposed on the gate passivation layer (301) and located between the source ohmic contact electrode (305) and the drain ohmic contact electrode (311); the gate field plate (308) covers and fills the gate opening (306) and forms a Schottky contact with the gate passivation layer (301); an end of the gate field plate (308) close to the drain ohmic contact electrode (311) exceeds an end of the gate opening (306) close to the drain ohmic contact electrode (311); The gate passivation layer (301) is formed by arranging SiN and / or SiO2 on the barrier layer (203) by low pressure chemical vapor deposition (LPCVD) or inductively coupled plasma-chemical vapor deposition (ICPCVD).

2. The HEMT power device based on a single field plate according to claim 1, characterized in that: The contact resistance of the source ohmic contact electrode (305) and the drain ohmic contact electrode (311) is less than 1 ohm*mm; and / or The distance between the gate opening (306) and the barrier layer (203) is 10 nm to 60 nm; and / or The length of one end of the gate field plate (308) close to the drain ohmic contact electrode (311) extending beyond one end of the gate opening (306) close to the drain ohmic contact electrode (311) is 2 μm-10 μm.

3. The HEMT power device based on a single field plate according to claim 1, characterized in that: The HEMT power device based on a single field plate further comprises a device isolation region (312), wherein the device isolation region (312) is arranged outside the active region, and the formation of the device isolation region (312) comprises implanting F ions or N ions into the epitaxial layer (2) by ion implantation, or etching the epitaxial layer (2).

4. The HEMT power device based on a single field plate according to claim 3, characterized in that: The ion implantation depth or etching depth of the device isolation region (312) reaches the buffer layer (201).

5. The HEMT power device based on a single field plate according to claim 3, characterized in that: The single field plate-based HEMT power device further comprises a passivation layer (302), wherein the passivation layer (302) is arranged on the gate passivation layer (301) and covers the source ohmic contact electrode (305), the drain ohmic contact electrode (311), the gate field plate (308) and the device isolation region (312).

6. The HEMT power device based on a single field plate according to claim 5, characterized in that: The thickness of the passivation layer (302) is 100 nm-6000 nm; and / or The HEMT power device based on a single field plate further includes: a source via hole (304), the source via hole (304) penetrating the passivation layer (302) and the gate passivation layer (301) to reach the surface of the source ohmic contact electrode (305); a drain via hole (310), the drain via hole (310) penetrating the passivation layer (302) and the gate passivation layer (301) to reach the surface of the drain ohmic contact electrode (311); A source interconnect metal electrode (303) is provided on the passivation layer (302) and is electrically connected to the source ohmic contact electrode (305) through the source via hole (304); A drain interconnect metal electrode (309) is provided on the passivation layer (302) and is electrically connected to the drain ohmic contact electrode (311) through the drain via hole (310).

7. The HEMT power device based on a single field plate according to claim 6, characterized in that: The material and forming method of the insulating layer (401) are the same as those of the gate passivation layer (301), or SiN is formed by in-situ growth; and / or The material of the substrate (1) includes Si, SiC or sapphire; and / or The material of the buffer layer (201) includes one or more of AlN, GaN and AlGaN; and / or The material of the channel layer (202) includes one or more of AlN, GaN, InGaN, InAlN, InAlGaN and AlGaN; and / or The material of the barrier layer (203) includes one or more of AlGaN, AlN, InAlN and InAlGaN; and / or The material of the passivation layer (302) includes one or more of SiN, SiO2 and SiON, or one or more of AlN, Al2O3 and AlON; and / or The material of the source interconnect metal electrode (303) includes one or more of Ti, Al, Au, TiN, Ta, TaN, Cu and AlCu; and / or The material of the source ohmic contact electrode (305) includes one or more of Ti, Al and TiN, or one or more of Ti, Al, Ni, Au and Mo, or one or more of Ta, Al and TaN; and / or The material of the gate field plate (308) includes one or more of Ti, Al, AlCu, TiN, Ni, Pt, Au, Ir, Ru, Ta, TaN, W, Zr, Mo, Rh, Pd, Pb, Os, Cu, Ag and ITO; and / or The material of the drain ohmic contact electrode (311) includes one or more of Ti, Al and TiN, or one or more of Ti, Al, Ni, Au and Mo, or one or more of Ta, Al and TaN; and / or The material of the drain interconnect metal electrode (309) includes one or more of Ti, Al, Au, TiN, Ta, TaN, Cu and AlCu.

8. A method for preparing a HEMT power device based on a single field plate, characterized in that: include: Providing a substrate (1) and a buffer layer material, a channel layer material, and a barrier layer material, and sequentially arranging the buffer layer material, the channel layer material, and the barrier layer material on the substrate (1) to form a buffer layer (201), a channel layer (202), and a barrier layer (203); Providing a source ohmic contact electrode material and a drain ohmic contact electrode material, respectively arranged on the barrier layer (203) to form a source ohmic contact electrode (305) and a drain ohmic contact electrode (311), and forming an ohmic contact between the source ohmic contact electrode (305) and the drain ohmic contact electrode (311) and the two-dimensional electron gas between the barrier layer (203) and the channel layer (202); Providing an insulating layer material or p-type doped PGaN, arranged on the barrier layer (203) to form an insulating layer (401) or a first gate layer (307), wherein the first gate layer is spaced apart from the source ohmic contact electrode (305) and the drain ohmic contact electrode (311); Providing SiN and / or SiO2, and arranging the SiN and / or SiO2 on the insulating layer (401) or covering the first gate layer (307) by low pressure chemical vapor deposition (LPCVD) or inductively coupled plasma chemical vapor deposition (ICPCVD) to form a gate passivation layer (301); Etching the gate passivation layer (301) to form a gate opening (306); A gate field plate material is provided and arranged on the gate passivation layer (301), forming a gate field plate (308) between the source ohmic contact electrode (305) and the drain ohmic contact electrode (311), wherein the gate field plate (308) covers and fills the gate opening (306) and forms a Schottky contact with the gate passivation layer (301).

9. The method for preparing a HEMT power device based on a single field plate according to claim 8, characterized in that: Providing the insulating layer material, and disposing it on the barrier layer (203) to form an insulating layer (401), comprising: Providing SiN and / or SiO2, disposing the SiN and / or SiO2 on the barrier layer (203) by low pressure chemical vapor deposition (LPCVD) or inductively coupled plasma chemical vapor deposition (ICPCVD), or disposing the SiN on the barrier layer (203) by in situ growth to form an insulating layer (401); and / or The preparation method further comprises: Providing F ions or N ions, and implanting the F ions or N ions into the buffer layer (201), the channel layer (202), and the barrier layer (203) outside the active region to form a device isolation region (312); or The buffer layer (201), the channel layer (202) and the barrier layer (203) are etched to form a device isolation region (312).

10. The method for preparing a HEMT power device based on a single field plate according to claim 9, characterized in that: Also includes: Providing a passivation layer material, and arranging it on the gate passivation layer (301) to form a passivation layer (302), wherein the passivation layer (302) covers the source ohmic contact electrode (305), the drain ohmic contact electrode (311), the gate field plate (308) and the device isolation region (312); Etching the passivation layer (302) and the gate passivation layer (301) to form a source via hole (304) and a drain via hole (310), wherein the source via hole (304) and the drain via hole (310) penetrate the passivation layer (302) and the gate passivation layer (301) and reach the surfaces of the source ohmic contact electrode (305) and the drain ohmic contact electrode (311), respectively; A source interconnect metal electrode material and a drain interconnect metal electrode material are provided and respectively arranged on the passivation layer (302), and form a source interconnect metal electrode (303) and a drain interconnect metal electrode (309), respectively. The source interconnect metal electrode (303) is electrically connected to the source ohmic contact electrode (305) through the source via hole (304), and the drain interconnect metal electrode (309) is electrically connected to the drain ohmic contact electrode (311) through the drain via hole (310).

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