2.5 D substrate packaging method and packaging structure

Abstract

The invention provides a 2.5 D substrate packaging method and packaging structure. The 2.5 D substrate packaging method comprises the following steps: providing a substrate with a groove; wherein the groove is a step groove; the grooves comprise a first groove and a second groove which are communicated with each other, and the depth of the first groove is greater than that of the second groove. A conductive pillar is formed in a substrate. Etching the substrate to expose the conductive pillars; forming a first insulating layer on one side, where the conductive columns are exposed, of the substrate in an ion implantation mode; the first insulating layer covers the surface of the substrate and the end face and the side wall of the exposed part of the conductive column. Grinding the first insulating layer to expose the end surface of the conductive column; forming a dielectric layer with a wiring layer on one side, far away from the substrate, of the first insulating layer; the wiring layer is electrically connected with the conductive column. The bonding force between the conductive column and the substrate can be improved, the conductive column is prevented from being broken or layered with the substrate in the grinding process, and the transmission performance of the conductive column is improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor packaging technology, and in particular to a 2.5D substrate packaging method and packaging structure. Background Art

[0002] With the rapid development of the semiconductor industry, chiplet technology has adopted a new design approach, packaging small chips with different functions together to form a heterogeneous integrated chip packaging structure. As chip input and output densities continue to increase, and the number of chips integrated into a single package has significantly increased, various 2.5D and 3D packaging technologies are being used as multi-chip packaging solutions to connect adjacent chip pads within a single package. Therefore, through-silicon via (TSV) technology has been proposed to form a heterogeneous integrated packaging structure, enabling multi-chip integration while reducing package volume and the number of wiring layers.

[0003] Currently, through-silicon-via (TSV) technology is used on substrates to achieve vertical interconnection between chips. Conventional technology typically uses etching or laser drilling technology to form a through hole in the substrate, then deposits a metal layer by electroplating to form a conductive pillar, and then polishes the conductive pillar to expose the conductive pillar. The exposed height of the conductive pillar is usually on the micron level. When the surface of the conductive pillar is polished, due to lateral stress pulling, it is easy to cause poor bonding between the conductive pillar and the inner wall of the substrate. In particular, during polishing, the conductive pillar and the inner wall of the substrate are poorly bonded, resulting in delamination and fracture around the conductive pillar and the polishing contact surface, affecting the transmission performance of the conductive pillar. Summary of the Invention

[0004] The object of the present invention is to provide a 2.5D substrate packaging method and packaging structure, which can prevent the conductive pillars from breaking during grinding, effectively protect the conductive pillars, and improve the transmission performance of the conductive pillars.

[0005] In a first aspect, the present invention provides a 2.5D substrate packaging method, comprising: A substrate having a groove is provided; wherein the groove is a step groove; the groove includes a first groove and a second groove connected to each other, and the depth of the first groove is greater than the depth of the second groove; forming a conductive pillar in the substrate; etching the substrate to expose the conductive pillars; A first insulating layer is formed on the side of the substrate where the conductive pillar is exposed by ion implantation; the first insulating layer covers the surface of the substrate and the end surface and side wall of the exposed portion of the conductive pillar; grinding the first insulating layer to expose the end surface of the conductive pillar; A dielectric layer having a wiring layer is formed on a side of the first insulating layer away from the substrate; the wiring layer is electrically connected to the conductive pillar.

[0006] In an optional embodiment, in the step of etching the substrate to expose the conductive pillar, the substrate is etched until it is flush with the bottom of the second groove.

[0007] In an optional embodiment, before or after the step of grinding the first insulating layer to expose the end surface of the conductive pillar, the method further includes: forming a second insulating layer on a side of the first insulating layer away from the substrate; grinding the second insulating layer to expose the end surface of the conductive pillar; In the step of forming a dielectric layer having a wiring layer on a side of the first insulating layer away from the substrate: A first dielectric layer having a wiring layer is formed on a side of the second insulating layer away from the substrate.

[0008] In an optional embodiment, a buffer layer is further formed in the first groove.

[0009] In an optional embodiment, the substrate includes a first surface and a second surface disposed opposite to each other; and the step of forming a conductive column in the substrate includes: forming a seed layer on the first surface of the substrate; A first carrier is attached to the side where the seed layer is provided; forming a through hole on the substrate that passes through the first surface and the second surface; The conductive pillar is formed by electroplating metal in the through hole; wherein the seed layer serves as an electroplating lead.

[0010] In an optional embodiment, before the step of forming a seed layer on the first surface of the substrate, the method further includes: forming the groove on the first surface; forming the seed layer on the groove bottom, groove wall and the first surface of the groove; In the step of attaching the first carrier to the side where the seed layer is provided: The first carrier covers the notch of the groove to form a first cavity structure; the first cavity structure serves as a flow channel for electroplating solution.

[0011] In an optional embodiment, the step of electroplating metal in the through hole to form the conductive pillar includes: A bottom metal layer is formed in the first cavity structure.

[0012] In an optional embodiment, after the step of electroplating metal in the through hole to form the conductive pillar, the method further includes: A communication hole is provided on the base, wherein the communication hole is used to connect the first grooves on both sides of the base; An edge metal column is formed in the communication hole.

[0013] In an optional embodiment, after the step of forming a conductive pillar in the substrate, the method further includes: attaching a second carrier to the second surface; removing the first carrier and the seed layer; etching the substrate from the first surface so that the conductive pillars are exposed from the first surface; forming a first insulating layer on the first surface by ion implantation; The first insulating layer is ground to expose end surfaces of the conductive pillars.

[0014] In an optional embodiment, after the step of grinding the first insulating layer to expose the end surface of the conductive pillar, the method further includes: Testing the electrical properties of the conductive pillars and the wiring layer; Among them, the negative pole of the test probe is connected to the first insulating layer in the first groove, and the positive pole of the test probe is connected to the conductive column, and a voltage is applied between the negative and positive poles of the test probe to detect the current change; the multiple conductive columns are detected one by one according to the Ohm's law formula R=U / I; since the resistance R is a constant; according to the voltage and current change curves, it is judged whether the electrical performance of the manufactured conductive columns and the wiring layer meets the requirements.

[0015] In an optional embodiment, the method further includes: forming solder balls electrically connected to the wiring layer on the surface of the dielectric layer; Electronic components are mounted on the solder balls.

[0016] In an optional embodiment, the method further includes: Before or after the step of mounting electronic components on the solder balls, cutting the substrate into individual products; And / or, plastic-sealing the electronic components.

[0017] In a second aspect, the present invention provides a packaging structure, comprising: A substrate; the substrate comprises a first surface and a second surface disposed opposite to each other; A plurality of conductive pillars are provided on the substrate; each of the conductive pillars partially protrudes from the first surface and the second surface; A first insulating layer and a second insulating layer are formed on the first surface and the second surface of the substrate in sequence in a direction away from the substrate; the first insulating layer protects the sidewalls of the protruding portion of the conductive column; A first dielectric layer; provided on a side of the second insulating layer away from the first insulating layer, the first dielectric layer having a wiring layer electrically connected to the conductive pillar; A second dielectric layer; provided on a side of the first dielectric layer away from the second insulating layer; Solder balls; the solder balls are protruding from the second dielectric layer and are electrically connected to the wiring layer; an electronic component electrically connected to the solder ball; A plastic package body is provided on the base and covers the electronic component.

[0018] In an optional embodiment, the plastic package exposes a surface of the electronic component away from the substrate.

[0019] In an optional embodiment, a circuit board and a metal ring are further included, the solder balls on the substrate are electrically connected to the circuit board, and the metal ring is connected to the circuit board and is arranged around the periphery of the substrate.

[0020] In a third aspect, the present invention provides a packaging structure prepared using the 2.5D substrate packaging method described in any one of the aforementioned embodiments.

[0021] The 2.5D substrate packaging method provided by an embodiment of the present invention uses ion implantation to form a first insulating layer on the side of the substrate where the conductive column is exposed; the first insulating layer covers the surface of the substrate and the end faces and side walls of the exposed portion of the conductive column. During subsequent grinding, the first insulating layer can effectively protect the conductive column to prevent breakage. In addition, the first insulating layer formed by ion implantation has a better bonding force with the substrate and the conductive column, respectively, which is beneficial to prevent delamination or cracking of the substrate and the conductive column, thereby improving the transmission performance of the conductive column. In addition, a step groove is provided on the substrate, which can be used to control the grinding depth and improve the grinding quality and efficiency.

[0022] The packaging structure provided by the embodiment of the present invention is manufactured using the above-mentioned 2.5D substrate packaging method, which can improve the bonding strength between the conductive pillar and the substrate, prevent the conductive pillar from breaking or delaminating from the substrate during the grinding process, and thus improve the transmission performance of the conductive pillar. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] In order to more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the specific embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0024] Figure 1A schematic diagram of forming a groove on the first surface of a substrate in a 2.5D substrate packaging method provided by an embodiment of the present invention; Figure 2 for Figure 1 A partial enlarged schematic diagram of point A in the middle; Figure 3 A schematic diagram of forming a seed layer and mounting a first carrier in a 2.5D substrate packaging method provided by an embodiment of the present invention; Figure 4 A schematic diagram of forming a groove on the second surface of a substrate in a 2.5D substrate packaging method provided by an embodiment of the present invention; Figure 5 A schematic diagram of a process for forming a conductive pillar in a substrate and exposing a portion of the conductive pillar in a 2.5D substrate packaging method provided by an embodiment of the present invention; Figure 6 A schematic diagram of forming a buffer layer in a groove of a substrate in a 2.5D substrate packaging method provided by an embodiment of the present invention; Figure 7 A schematic diagram of the process of forming a first insulating layer and a second insulating layer on a substrate and polishing to expose the end surface of a conductive pillar in a 2.5D substrate packaging method provided by an embodiment of the present invention; Figure 8 for Figure 7 A partial enlarged schematic diagram of point B in the middle; Figure 9 for Figure 7 A partial enlarged schematic diagram of point C in the middle; Figure 10 A schematic diagram of a process for forming a wiring layer and solder balls on a substrate in a 2.5D substrate packaging method provided by an embodiment of the present invention; Figure 11 A schematic diagram of a process for removing a seed layer on a substrate in a 2.5D substrate packaging method provided by an embodiment of the present invention; Figure 12 A schematic diagram of completing the preparation of the first surface of a substrate in the 2.5D substrate packaging method provided by an embodiment of the present invention; Figure 13 A schematic diagram of the process of cutting and separating chips into individual products after mounting them in the 2.5D substrate packaging method provided by an embodiment of the present invention; Figure 14 A schematic diagram of the process of cutting and separating the substrate into individual substrates and then mounting the chip in the 2.5D substrate packaging method provided by an embodiment of the present invention; Figure 15 A schematic diagram of the process of mounting a chip, then plastic-sealing it, and then cutting it into individual products in the 2.5D substrate packaging method provided by an embodiment of the present invention; Figure 16A schematic diagram of the distribution of conductive pillars and grooves on a substrate in a 2.5D substrate packaging method provided by an embodiment of the present invention; Figure 17 A schematic diagram of forming a second insulating layer and a second cavity structure by laminating in a 2.5D substrate packaging method provided by an embodiment of the present invention; Figure 18 A schematic diagram of a first packaging structure provided by an embodiment of the present invention; Figure 19 A schematic diagram of a second packaging structure provided by an embodiment of the present invention; Figure 20 A schematic diagram of a third packaging structure provided by an embodiment of the present invention; Figure 21 This is a schematic diagram of a fourth packaging structure provided by an embodiment of the present invention.

[0025] Icons: 110-substrate; 111-first surface; 112-second surface; 113-groove; 114-first groove; 115-second groove; 116-through hole; 117-connecting hole; 118-buffer layer; 120-conductive column; 121-seed layer; 122-first carrier; 123-bonding glue; 124-first cavity structure; 125-bottom metal layer; 130-edge metal column; 140-first insulating layer; 141-third groove; 142-second insulating layer; 143-second cavity structure; 151-first dielectric layer; 152-graphic layer opening; 153-wiring layer; 154-second dielectric layer; 155-bump; 156-solder ball; 161-second carrier; 170-chip; 171-protective glue; 180-plastic package; 210-circuit board; 220-metal ring; 230-bottom glue. DETAILED DESCRIPTION

[0026] To make the objectives, technical solutions, and advantages of the embodiments of the present invention more clear, the technical solutions of the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Generally, the components of the embodiments of the present invention described and shown in the drawings herein can be arranged and designed in various different configurations.

[0027] Therefore, the following detailed description of the embodiments of the present invention provided in the accompanying drawings is not intended to limit the scope of the invention as claimed, but rather merely represents selected embodiments of the present invention. All other embodiments derived by persons of ordinary skill in the art based on the embodiments of the present invention without creative effort shall fall within the scope of protection of the present invention.

[0028] It should be noted that similar reference numerals and letters denote similar items in the following drawings, and therefore, once an item is defined in one drawing, it does not need to be further defined or explained in subsequent drawings.

[0029] In the description of the present invention, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer" and the like indicate positions or locations based on the positions shown in the accompanying drawings, or the positions or locations in which the inventive product is typically placed when in use. These terms are intended solely to facilitate the description of the present invention and to simplify the description, and are not intended to indicate or imply that the devices or components referred to must have a specific orientation, be constructed, or operate in a specific orientation. Therefore, they should not be construed as limitations on the present invention. Furthermore, the terms "first," "second," and "third," etc., are used solely to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0030] Furthermore, terms such as "horizontal," "vertical," and "overhanging" do not necessarily imply that a component must be absolutely horizontal or overhanging, but rather that it can be slightly tilted. For example, "horizontal" simply means that its direction is more horizontal than "vertical," and does not mean that the structure must be completely horizontal, but rather that it can be slightly tilted.

[0031] In the description of the present invention, it should also be noted that, unless otherwise expressly specified or limited, the terms "disposed," "installed," "connected," and "connected" should be understood in a broad sense. For example, they may refer to fixed connections, detachable connections, or integral connections; they may refer to mechanical connections or electrical connections; they may refer to direct connections or indirect connections through an intermediate medium; and they may refer to internal communication between two components. Those skilled in the art will understand the specific meanings of the above terms in the present invention based on the specific circumstances.

[0032] The following embodiments of the present invention are described in detail with reference to the accompanying drawings. In the absence of conflict, the following embodiments and features in the embodiments may be combined with each other.

[0033] A 2.5D substrate packaging method proposed in an embodiment of the present invention can improve the bonding force between the conductive pillar 120 and the substrate 110, prevent the conductive pillar 120 from breaking or delaminating from the substrate 110 during the grinding process, and thus improve the transmission performance of the conductive pillar 120.

[0034] Combine Figure 1 and Figure 2 The 2.5D substrate packaging method generally includes the following steps: S1. Provide a substrate 110 having a groove 113 ; wherein the groove 113 is a step groove; the groove 113 includes a first groove 114 and a second groove 115 that are connected to each other, and the depth of the first groove 114 is greater than the depth of the second groove 115 .

[0035] Optionally, the substrate 110 is made of a silicon-based or germanium-based substrate material, including but not limited to silicon oxide, phosphosilicate glass, fluorine-containing glass or glass. The thickness of the substrate 110 is 600um to 1500um.

[0036] The substrate 110 includes a first surface 111 and a second surface 112 that are opposite to each other along the thickness direction thereof. The groove 113 can be formed on at least one of the first surface 111 and the second surface 112 by dry etching or chemical etching. In this embodiment, the groove 113 is first etched on the first surface 111. The groove 113 is stepped. The first groove 114 has a depth H1 and a width W1; the second groove 115 has a depth H2, and the sum of the widths of the first groove 114 and the second groove 115 is W2. Optionally, H1 is 21um to 50um; H2 is 2um to 20um; W1 is 50um to 200um; and W2 is 200um to 600um.

[0037] It can be understood that in the subsequent etching and grinding process, the first groove 114 and the second groove 115 can also play a role in depth control and serve as a positioning reference to improve the preparation accuracy of the conductive column 120 and the height uniformity of multiple conductive columns 120, thereby improving the yield of the packaging structure.

[0038] Please combine Figure 3 , S2, forming a conductive pillar 120 in the substrate 110. The process includes steps S21 to S24.

[0039] S21 , forming a seed layer 121 on the first surface 111 .

[0040] Optionally, the seed layer 121 can be any conductive metal, such as copper or other metals. The thickness of the seed layer 121 is about 1um to 5um. The formation method of the seed layer 121 includes but is not limited to any one of the vapor deposition processes PVD, CVD, MOCVD, ALD, LPCVD or PECVD. The seed layer 121 can be used as the electroplating lead for the subsequent formation of the conductive column 120. The seed layer 121 covers the first surface 111 and the bottom and wall of the groove 113. The groove 113 can enhance the bonding force of the edge of the electroplating lead, which is beneficial to improving the uniformity and stability of the subsequent electroplating process.

[0041] S22 , placing a first carrier 122 on the side where the seed layer 121 is provided.

[0042] Optionally, a layer of bonding adhesive 123 is coated on the surface of the first carrier 122, and the bonding adhesive 123 can be separated by irradiating ultraviolet light or laser debonding. It is understood that due to the presence of the groove 113, the first carrier 122 covers the notch of the groove 113 to form a first cavity structure 124 at the groove 113; the first cavity structure 124 can serve as a flow channel for the electroplating solution, which is conducive to improving the efficiency and quality of electroplating.

[0043] S23 , forming a through hole 116 on the substrate 110 , the through hole 116 penetrating the first surface 111 and the second surface 112 .

[0044] Please combine Figure 4 Optionally, the second surface 112 is first ground to reduce the thickness of the substrate 110. The grinding thickness can be set according to actual needs. In this embodiment, after grinding, the thickness of the substrate 110 is approximately 80 μm to 300 μm. The grinding process is beneficial for reducing the thickness of the substrate 110 and reducing stress.

[0045] A groove 113 structure is formed on the second surface 112 . The structure of the groove 113 on the second surface 112 and the forming method of the groove 113 are respectively consistent with the structure of the groove 113 on the first surface 111 and the forming method of the groove 113 .

[0046] Combine Figure 5 A through hole 116 penetrating the first surface 111 and the second surface 112 is formed on the substrate 110 by dry etching. Of course, the through hole 116 can also be formed by laser drilling or other methods.

[0047] Optional, combined Figure 6 Buffering glue can be filled into the first groove 114 to form a buffer layer 118. The buffering glue is filled to a position flush with the bottom of the second groove 115. This can improve the buffering performance of the substrate 110 and mitigate warping deformation during subsequent packaging processes. Of course, in some embodiments, the buffer layer 118 can also be omitted.

[0048] S24 , electroplating metal in the through hole 116 to form a conductive pillar 120 ; wherein the seed layer 121 serves as a plating lead.

[0049] It can be understood that a first cavity structure 124 is formed at the groove 113 of the first surface 111, which can be used as a plating solution flow channel in the electroplating process, and the substrate 110 can be hung in the plating solution, and the seed layer 121 is used as an electroplating lead for current plating. Since the electroplating solution is in direct contact with the seed layer 121 at the first cavity structure 124, the seed layer 121 is connected to each through hole 116 respectively, which can improve the uniformity and consistency of the height of the porous electroplated conductive column 120. And the seed layer 121 is located at the bottom of the substrate 110 as an electroplating lead, and the electroplating current enters the through hole 116 from one side of the seed layer 121 along the electroplating lead to form a conductive column 120. This is conducive to improving the density of metal filling during the electroplating process and preventing the occurrence of voids and the like. The material of the conductive column 120 is copper or other metals.

[0050] It is understood that when electroplating to form the conductive pillars 120, the first cavity structure 124 can also be filled with metal to form a bottom metal layer 125. The bottom metal layer 125 helps to improve the structural strength and edge support performance of the substrate 110 and improve the deformation of the substrate 110 during subsequent grinding.

[0051] Optionally, after forming the conductive pillar 120, a connecting hole 117 is opened on the substrate 110 to connect the groove 113 on the first surface 111 with the groove 113 on the second surface 112. The hole opening method can be laser opening or etching.

[0052] Optionally, electroplating is used to form edge metal pillars 130 within the communication holes 117. It should be noted that a double electroplating process is used for the conductive pillars 120 and edge metal pillars 130. By controlling the current parameters in the electroplating process and the height of the edge metal pillars 130, the grooves 113 on the side of the substrate 110 away from the seed layer 121 are not filled by electroplating.

[0053] It should be noted that the first cavity structure 124 can later serve as an electrical test point for the conductive pillars 120 and the wiring layer 153 to ensure that the electrical performance of the conductive pillars 120 and the wiring layer 153 meets the requirements, thereby improving the transmission performance and quality of the conductive pillars 120 and the wiring layer 153. The formation of the edge metal pillars 130 helps to improve the support of the edge of the substrate 110, and also helps to increase the strength of the substrate 110, prevent warping and deformation, and improve the heat dissipation performance of the packaging structure.

[0054] Of course, in some embodiments, the preparation of the connecting holes 117 and the edge metal pillars 130 may be omitted, which is not specifically limited here.

[0055] S3 , etching the substrate 110 to expose the conductive pillars 120 .

[0056] Optionally, a portion of the substrate 110 is removed from the second surface 112 by etching, exposing the conductive pillars 120 from the second surface 112. Alternatively, the substrate 110 is etched until it is flush with the bottom of the second groove 115. The thickness of the substrate 110 sacrificed during etching is the depth of the second groove 115. That is, the depth of the second groove 115 serves as a sacrificial layer in the etching process, which helps control the consistency of the exposed height of the conductive pillars 120. In other words, the exposed height of the conductive pillars 120 is the depth of the second groove 115.

[0057] It should be noted that, in some embodiments, the substrate 110 is silicon-based. After forming the through-hole 116 on the substrate 110, the substrate 110 can be placed in a high-temperature environment. After the silicon base is oxidized at high temperature, a silicon oxide film can be formed on the surface of the substrate 110 and the wall of the through-hole 116. Subsequently, the conductive pillar 120 is formed by electroplating, which is conducive to improving the bonding strength between the conductive pillar 120 and the substrate 110, as well as improving the insulation between the conductive pillar 120 and the substrate 110. In the step of etching the substrate 110 to expose the conductive pillar 120, the silicon oxide film on the surface of the substrate 110 away from the seed layer 121 will be removed.

[0058] Combine Figures 7 to 9 S4. Ion implantation is used to form a first insulating layer 140 on the side of the substrate 110 where the conductive pillars 120 are exposed. The first insulating layer 140 covers the second surface 112 of the substrate 110 and the exposed end surfaces and sidewalls of the conductive pillars 120. Third grooves 141 are formed in the first insulating layer 140 between adjacent conductive pillars 120.

[0059] Optionally, an ion implantation process is used to ionize the atoms of the first insulating layer 140 into ions and implant them into the first surface 111 of the substrate 110 and the sidewalls and end faces of the conductive pillars 120. Optionally, the thickness of the first insulating layer 140 is less than or equal to half the exposed height H2 of the conductive pillars 120. Utilizing the ion implantation process, the material properties of the surface of the substrate 110 and the exposed surface of the conductive pillars 120 can be modified to provide better bonding strength. The first insulating layer 140 can protect the sidewalls of the conductive pillars 120 and improve the bonding strength between the conductive pillars 120 and the substrate 110.

[0060] It is easy to understand that the thickness of the first insulating layer 140 can be designed according to actual needs. The surface of the first insulating layer 140 away from the substrate 110 can be a concave-convex structure, such as the surface between adjacent conductive pillars 120 is lower than the surface of the first insulating layer 140 located at the head of the conductive pillar 120, or the surface of the first insulating layer 140 away from the substrate 110 can be a planar structure, which is not specifically limited here.

[0061] It is worth noting that conventional processes often first roughen the surface before forming a thick insulating layer on the second surface of the substrate using spin coating or vapor deposition. In this embodiment, the ion implantation process eliminates the need for surface roughening and provides improved bonding strength. Furthermore, the ion implantation process can implant ions into the interior of the substrate 110, resulting in a thinner, more compact, and smaller overall thickness.

[0062] In addition, the provision of the first groove 114 on the surface of the substrate 110 is also beneficial for improving the bonding force between the first insulating layer 140 and the substrate 110 .

[0063] S5 , grinding the first insulating layer 140 to expose the end surfaces of the conductive pillars 120 .

[0064] Optionally, chemical polishing is used to remove the first insulating layer 140 covering the end face of the conductive pillar 120. In this process, the notch of the first groove 114 (the top surface of the groove wall of the first groove 114) can be used as a positioning reference to polish the first insulating layer 140 on the surface of the conductive pillar 120 until it is flush with the notch of the first groove 114. During the polishing process, the groove wall of the first groove 114 of the second surface 112 plays a supporting role, improving the edge support and preventing the edge from collapsing after polishing, which is beneficial to improving the overall flatness of the second surface 112 after polishing. In addition, the bottom metal layer 125 and the edge metal pillar 130 at the first cavity structure 124 further improve the edge support of the substrate 110 and prevent the edge of the substrate 110 from collapsing or deforming during the polishing process. In addition, the first insulating layer 140 protects the sidewalls of the conductive pillar 120 to prevent the conductive pillar 120 from breaking or separating from the substrate 110 due to polishing stress.

[0065] Optionally, chemical polishing is used to polish the second surface 112 of the substrate 110 using a polishing liquid such as ammonia, hydrofluoric acid or citric acid under the pressure of a polishing pad and centrifugal force to expose the heads of the conductive pillars 120 .

[0066] S6 , forming a second insulating layer 142 on a side of the first insulating layer 140 away from the substrate 110 ; and grinding the second insulating layer 142 to expose end surfaces of the conductive pillars 120 .

[0067] A second insulating layer 142 is formed on the first insulating layer 140 by spin coating or vapor deposition. The second insulating layer 142 covers the first insulating layer 140 and the exposed end surfaces of the conductive pillars 120. It is understood that the second insulating layer 142 completely fills the first and second recesses 114 and 115, thereby enhancing the bonding strength between the first and second insulating layers 140 and 142. It is understood that if the second recess 115 was previously filled with the buffer layer 118, the second insulating layer 142 will fill the remaining space in the second recess 115.

[0068] Chemical polishing is used to remove the second insulating layer 142 covering the end faces of the conductive pillars 120, exposing the end faces of the conductive pillars 120. The second insulating layer 142 is polished until it is flush with the openings of the first grooves 114. This allows the walls of the first grooves 114 to control the polishing depth and provide edge support, improving polishing accuracy and increasing the consistency of the exposed height of the conductive pillars 120. Furthermore, the top surface of the walls of the first grooves 114 is flush with the end faces of the conductive pillars 120, distributing the forces acting on the conductive pillars 120 during polishing and protecting them from breakage.

[0069] It is understood that grinding can be performed separately after forming the first insulating layer 140 and the second insulating layer 142, i.e., performing two grindings, specifically: forming the first insulating layer 140, performing the first grinding, forming the second insulating layer 142, and performing the second grinding. Alternatively, the grinding after forming the first insulating layer 140 can be omitted. After forming the first insulating layer 140 on the substrate 110, the second insulating layer 142 is subsequently formed, and then grinding is performed again to remove the second insulating layer 142 and the first insulating layer 140 on the end faces of the conductive pillars 120, thereby exposing the end faces of the conductive pillars 120.

[0070] Combine Figure 10 , S7, forming a first dielectric layer 151 having a wiring layer 153 on a side of the second insulating layer 142 away from the substrate 110.

[0071] Optionally, a first dielectric layer 151 is formed on the second insulating layer 142 using a spin coating process. A photomask is placed over the first dielectric layer 151, and an exposure and development process is performed to form a patterned layer opening 152 in the first dielectric layer 151. The patterned layer opening 152 exposes the end faces of the conductive pillars 120. An electroplating process is then used to form a wiring layer 153 within the patterned layer opening 152, electrically connecting the wiring layer 153 to the conductive pillars 120. The wiring layer 153 can be formed using any process, such as sputtering, electroless plating, physical vapor deposition (PVD), chemical vapor deposition (CVD), metal organic chemical vapor deposition (MOCVD), atomic layer deposition (ALD), low pressure chemical vapor deposition (LPCVD), or plasma enhanced chemical vapor deposition (PECVD).

[0072] S8 , forming bumps 155 connected to the wiring layer 153 , and planting balls on the bumps 155 .

[0073] Optionally, a second dielectric layer 154 is formed on a side of the first dielectric layer 151 away from the substrate 110. The molding method and material of the second dielectric layer 154 are consistent with the molding method and material of the first dielectric layer 151. An opening is formed in the first dielectric layer 151 through an exposure and development process, and the opening is filled with metal to form a bump 155. The bump 155 can be formed by any process including, but not limited to, electroplating, sputtering, chemical plating, physical vapor deposition (PVD), chemical vapor deposition (CVD), metal-organic chemical vapor deposition (MOCVD), atomic layer deposition (ALD), low-pressure chemical vapor deposition (LPCVD), or plasma-enhanced chemical vapor deposition (PECVD).

[0074] Solder balls 156 are formed on the bumps 155 by electroplating or printing.

[0075] In this embodiment, the first insulating layer 140 and the second insulating layer 142 are made of the same material, which can be at least one of silicon oxide, silicon dioxide, silicon nitride, aluminum oxide, silicon oxynitride, and an organic dielectric material.

[0076] The first dielectric layer 151 and the second dielectric layer 154 are made of the same material, and are made of any one or more of polyimide and benzocyclobutene.

[0077] Combine Figure 11 S9: Mount the second carrier 161 on the side where the solder balls 156 are provided. The second carrier 161 is coated with bonding glue 123, which can be separated by irradiating ultraviolet light or laser debonding.

[0078] The first carrier 122 on one side of the first surface 111 is removed by debonding.

[0079] S10 , etching and removing the seed layer 121 .

[0080] Optionally, the product is flipped over, with the first surface 111 facing upward and the second carrier 161 positioned underneath. The seed layer 121 is removed using a micro-etching method, including but not limited to dry etching or chemical etching. It should be noted that when the seed layer 121 is removed, the bottom metal layer 125 in the first cavity structure 124 is also removed.

[0081] Combine Figure 12 , repeat the above steps S3 to S10 to complete the production of the first surface 111 of the substrate 110.

[0082] The substrate 110 is removed from the first surface 111 by etching, so that the other end of the conductive pillar 120 is exposed from the first surface 111. The exposed height of the conductive pillar 120 can be set according to actual needs. In this embodiment, the exposed height of the conductive pillar 120 is equal to the depth of the second groove 115 on the first surface 111.

[0083] Ion implantation is used to form a first insulating layer 140 and a second insulating layer 142 on the first surface 111. The second insulating layer 142 and the first insulating layer 140 are then ground to expose the end faces of the conductive pillars 120. A first dielectric layer 151, a wiring layer 153, a second dielectric layer 154, bumps 155, and solder balls 156 are then formed.

[0084] Combine Figure 13 Optionally, electronic components are mounted on one side of the first surface 111. The electronic components are electrically connected to the solder balls 156. The electronic components include at least one of a chip 170 and a component. In this embodiment, a chip 170 is mounted on one side of the first surface 111, and the pads on the chip 170 are soldered to the solder balls 156 on the bumps 155 to achieve electrical connection. The protective glue 171 is scratched on the bottom of the chip 170. The second carrier 161 is debonded and removed. The chips are cut and separated into single products.

[0085] Optionally, at least one of a chip 170 and components may be mounted on one side of the second surface 112 to improve integration.

[0086] It is understandable that after the chip 170 or components are mounted, the chip 170 or components can be selectively encapsulated to form a plastic package 180 .

[0087] Combine Figure 14 Optionally, after the solder balls 156 on both sides of the substrate 110 are formed, the substrate 110 can be cut and separated while retaining the second carrier 161. The cutting depth is to the second carrier 161, wherein the second carrier 161 is not cut. In this way, the second carrier 161 plays a supporting role and prevents the substrate 110 from being deformed during cutting. The chip 170 or components can then be mounted on the single substrate 110. In this way, the cutting process is completed before the chip 170 is mounted, which can prevent the welding structure of the chip 170 and the solder balls 156 from being affected by the cutting stress and cracking.

[0088] Combine Figure 15 Optionally, if the chip 170 needs to be plastic-encapsulated, the chip 170 can be plastic-encapsulated to form a plastic-encapsulated body 180 after being attached, and the second carrier 161 can be removed and cut into individual products.

[0089] Optionally, in this embodiment, after the second surface 112 of the substrate 110 is fabricated, the product is flipped over to remove the seed layer 121. After ion implantation is performed on the first surface 111 to form the first insulating layer 140, the electrical performance of the conductive pillars 120 and the wiring layer 153 on the second surface 112 can be tested. The testing principle is as follows: The negative electrode of the test probe is connected to the first insulating layer 140 at the groove 113, and the positive electrode of the test probe is connected to the conductive pillar 120. A voltage is applied between the positive and negative electrodes to measure the current change. Each conductive pillar 120 is tested in turn. According to Ohm's law R = U / I; since the resistance R is a constant, the voltage-current curve can be used to test the conductivity of the conductive pillar 120 and the wiring layer 153, and determine whether the electrical performance of the manufactured conductive pillar 120 and wiring layer 153 meets the requirements.

[0090] The first insulating layer 140 can also improve insulation performance and prevent leakage during electrical testing. During testing or subsequent use, the conductive pillars 120 and other components will generate heat, and the edge metal pillars 130 can also effectively dissipate heat.

[0091] It should be noted that electrical testing can also be performed after polishing the second insulating layer 142. In this case, the negative electrode of the test probe is connected to the second insulating layer 142 at the first groove 114, achieving similar technical effects. Alternatively, if the first insulating layer 140 and the second insulating layer 142 are polished twice, electrical testing can be performed after each polishing.

[0092] Combine Figure 16 A plurality of conductive pillars 120 are formed on the substrate 110, and grooves 113 structures are arranged on the periphery of the conductive pillars 120. The grooves 113 structures serve as electrical test points to facilitate timely detection of the electrical performance of the conductive pillars 120 and the wiring layer 153.

[0093] Combine Figure 17 Optionally, in some embodiments, in the step of forming the second insulating layer 142, the second insulating layer 142 can be formed by a coating method, so that the notch of the groove 113 is covered in the second insulating layer 142, and a second cavity structure 143 is formed between the second insulating layer 142 and the first insulating layer 140. Optionally, a filler is subsequently poured into the second cavity structure 143 through a microchannel design to fill the second cavity structure 143. The filler can be the same material as the second insulating layer 142. In this way, it is beneficial to improve the support and heat dissipation, and has a certain buffering property, which can reduce the plastic packaging stress and alleviate the warping deformation.

[0094] An embodiment of the present invention further provides a packaging structure, which is prepared using the above method.

[0095] Combine Figure 18The package structure includes a substrate 110 and a conductive pillar 120 extending through the substrate 110. A first insulating layer 140, a second insulating layer 142, a first dielectric layer 151 having a wiring layer 153, a second dielectric layer 154, and solder balls 156 are formed on the first surface 111 and the second surface 112 of the substrate 110, respectively, in a direction away from the substrate 110. The first insulating layer 140 protects the sidewalls of the conductive pillars 120 that are exposed from the substrate 110. Optionally, a third groove 141 is provided in the first insulating layer 140, the groove walls of which protect the sidewalls of the conductive pillars 120 that are exposed from the substrate 110. The second insulating layer 142 fills the third groove 141. A chip 170 is attached to one or both sides of the substrate 110; or the chip 170 is attached to one side and components are attached to the other side; or the chip 170 and components are attached to the same side, without specific limitation.

[0096] Optionally, the chip 170 is a flip chip, and the pads of the chip 170 are soldered to the solder balls 156 of the substrate 110 and protected by a protective adhesive 171 .

[0097] Combine Figure 19 , the chip 170 is plastic-encapsulated to form a plastic-encapsulated body 180 .

[0098] Combine Figure 20 When the substrate 110 is cut and separated into individual substrates, the grooves 113 on the first surface 111 and the second surface 112 remain in the individual substrates 110. After the chip 170 is mounted, the chip 170 is plastic-encapsulated to form a plastic encapsulation body 180. The plastic encapsulation body 180 completely fills the grooves 113 on the same side as the chip 170, thereby enhancing the bonding strength between the plastic encapsulation body 180 and the substrate 110. It will be appreciated that in this embodiment, the first wiring layer 153 and the second wiring layer 153 are formed while avoiding the grooves 113 on the side of the substrate 110 where the chip 170 is mounted.

[0099] Combine Figure 21 Optionally, the plastic package 180 can be thinned to expose the surface of the chip 170 to improve heat dissipation.

[0100] Optionally, the package structure further includes a circuit board 210 and a metal ring 220. The solder balls 156 on the substrate 110 are electrically connected to the circuit board 210, and the metal ring 220 is connected to the circuit board 210 and disposed around the periphery of the substrate 110. Specifically, the solder balls 156 on the substrate 110 are soldered to the circuit board 210, and the solder balls 156 are secured and protected by a primer 230. The metal ring 220 is fixedly connected to the circuit board 210 and serves to dissipate heat and prevent warping.

[0101] In some embodiments, the grooves 113 on both sides of the substrate 110 may be removed when the substrate 110 is cut into individual substrates 110 or individual products.

[0102] It should be noted that in this embodiment, a first insulating layer 140 and a second insulating layer 142 are provided between the surface of the substrate 110 and the second wiring layer 153. The first insulating layer 140 can protect the conductive column 120, and the first insulating layer 140 and the second insulating layer 142 can also prevent electromigration.

[0103] The 2.5D substrate packaging method and packaging structure provided by the embodiments of the present invention have the following beneficial effects: By setting the groove 113, it can play the role of positioning, improving edge support and edge bonding, and the first insulating layer 140 and the second insulating layer 142 can protect the conductive column 120, reduce the stress during the grinding process, avoid the conductive column 120 from breaking or separating from the substrate 110, and improve the insulation performance, prevent leakage during electrical testing, etc. By designing the seed layer 121 on one side, it can be used as an electroplating lead to improve the uniformity of the electroplating forming of the conductive column 120, and the groove 113 structure can be used as a plating liquid flow channel and an electrical test point, which is beneficial to improve the packaging quality and packaging efficiency. The first insulating layer 140 is formed by an ion implantation process, which can simplify the process, improve the bonding force, and change the surface properties of the material, resulting in better insulation.

[0104] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the above embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the above embodiments, or make equivalent replacements for some or all of the technical features therein. Any modifications, equivalent replacements, improvements, etc. made should be included in the scope of protection of the present invention.

Claims

1. A 2.5D substrate packaging method, characterized in that: include: A substrate having a groove is provided; wherein the groove is a step groove; the groove includes a first groove and a second groove connected to each other, and the depth of the first groove is greater than the depth of the second groove; forming a conductive pillar in the substrate; etching the substrate to expose the conductive pillars; A first insulating layer is formed on the side of the substrate where the conductive pillar is exposed by ion implantation; the first insulating layer covers the surface of the substrate and the end surface and side wall of the exposed portion of the conductive pillar; grinding the first insulating layer to expose the end surface of the conductive pillar; A dielectric layer having a wiring layer is formed on a side of the first insulating layer away from the substrate; the wiring layer is electrically connected to the conductive pillar.

2. The 2.5D substrate packaging method according to claim 1, wherein: In the step of etching the substrate to expose the conductive pillar, the substrate is etched until it is flush with the bottom of the second groove.

3. The 2.5D substrate packaging method according to claim 1, wherein: Before or after the step of grinding the first insulating layer to expose the end surface of the conductive pillar, the method further includes: forming a second insulating layer on a side of the first insulating layer away from the substrate; grinding the second insulating layer to expose the end surface of the conductive pillar; In the step of forming a dielectric layer having a wiring layer on a side of the first insulating layer away from the substrate: A first dielectric layer having a wiring layer is formed on a side of the second insulating layer away from the substrate.

4. The 2.5D substrate packaging method according to claim 1, wherein: The method further includes forming a buffer layer in the first groove.

5. The 2.5D substrate packaging method according to claim 1, wherein: The substrate includes a first surface and a second surface opposite to each other; and the step of forming a conductive column in the substrate includes: forming a seed layer on the first surface of the substrate; A first carrier is attached to the side where the seed layer is provided; forming a through hole on the substrate that passes through the first surface and the second surface; The conductive pillar is formed by electroplating metal in the through hole; wherein the seed layer serves as an electroplating lead.

6. The 2.5D substrate packaging method according to claim 5, characterized in that: Before the step of forming a seed layer on the first surface of the substrate, the method further includes: forming the groove on the first surface; forming the seed layer on the groove bottom, groove wall and the first surface of the groove; In the step of attaching the first carrier to the side where the seed layer is provided: The first carrier covers the notch of the groove to form a first cavity structure; the first cavity structure serves as a flow channel for electroplating solution.

7. The 2.5D substrate packaging method according to claim 6, wherein: The step of electroplating metal in the through hole to form the conductive pillar includes: A bottom metal layer is formed in the first cavity structure.

8. The 2.5D substrate packaging method according to claim 6, wherein: After the step of electroplating metal in the through hole to form the conductive pillar, the method further includes: A communication hole is provided on the base, wherein the communication hole is used to connect the first grooves on both sides of the base; An edge metal column is formed in the communication hole.

9. The 2.5D substrate packaging method according to claim 6, wherein: After the step of forming a conductive column in the substrate, the method further includes: attaching a second carrier to the second surface; removing the first carrier and the seed layer; etching the substrate from the first surface so that the conductive pillars are exposed from the first surface; forming a first insulating layer on the first surface by ion implantation; The first insulating layer is ground to expose end surfaces of the conductive pillars.

10. The 2.5D substrate packaging method according to claim 9, wherein: After the step of grinding the first insulating layer to expose the end surface of the conductive pillar, the method further includes: Testing the electrical properties of the conductive pillars and the wiring layer; Among them, the negative pole of the test probe is connected to the first insulating layer in the first groove, and the positive pole of the test probe is connected to the conductive column, and a voltage is applied between the negative and positive poles of the test probe to detect the current change; the multiple conductive columns are detected one by one according to the Ohm's law formula R=U / I; since the resistance R is a constant; according to the voltage and current change curves, it is judged whether the electrical performance of the manufactured conductive columns and the wiring layer meets the requirements.

11. The 2.5D substrate packaging method according to any one of claims 1 to 10, characterized in that: Also includes: forming solder balls electrically connected to the wiring layer on the surface of the dielectric layer; Electronic components are mounted on the solder balls.

12. The 2.5D substrate packaging method according to claim 11, wherein: Also includes: Before or after the step of mounting electronic components on the solder balls, cutting the substrate into individual products; And / or, plastic-sealing the electronic components.

13. A packaging structure, characterized in that: include: substrate; The substrate includes a first surface and a second surface disposed opposite to each other; A plurality of conductive pillars are provided on the substrate; each of the conductive pillars partially protrudes from the first surface and the second surface; A first insulating layer and a second insulating layer are formed on the first surface and the second surface of the substrate in sequence in a direction away from the substrate; the first insulating layer protects the sidewalls of the protruding portion of the conductive column; a first dielectric layer; The first dielectric layer is provided on a side of the second insulating layer away from the first insulating layer, and the first dielectric layer has a wiring layer electrically connected to the conductive pillar; a second dielectric layer; Located on a side of the first dielectric layer away from the second insulating layer; Solder balls; The solder ball is protruded from the second dielectric layer and is electrically connected to the wiring layer; an electronic component electrically connected to the solder ball; A plastic package body is provided on the base and covers the electronic component.

14. The packaging structure according to claim 13, wherein: The plastic package exposes a surface of the electronic component away from the substrate.

15. A packaging structure, characterized in that: It is prepared using the 2.5D substrate packaging method according to any one of claims 1 to 12.

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