Enhanced restart of nodes after interruption

Abstract

The present disclosure relates to methods for recovering the time of a clock in a first node after a service interruption, and systems for performing these methods. A second node may hold a time during a downtime of the first node and transmit synchronization pulses to the first node, which may be used to estimate a time error that may be used to adjust a clock of the first node.

Description

Technical Field

[0001] The present disclosure relates to methods for restarting nodes in a communication system requiring time synchronization. More particularly, the present disclosure relates to methods for restoring the time of a clock in a node after a service interruption, and systems for performing these methods. Background Art

[0002] Nodes that communicate with other nodes in a network need to be synchronized for efficient communication, for example by keeping their internal clocks synchronized with the internal clocks of the other nodes. This can be achieved through various synchronization or time transfer processes. Nodes sometimes need to be temporarily shut down or restarted, for example during an upgrade. After the upgrade, the internal clocks will be interrupted and out of sync, and the time transfer or synchronization process will need to be repeated to restore the clocks. It may take approximately 1000 seconds (s) for node synchronization to stabilize and for the node to be able to transfer time again. During this period, the performance of the node will be impaired. Therefore, there is a need for methods and systems for enhancing node synchronization after downtime. Summary of the Invention

[0003] The present disclosure provides methods and systems for mitigating, alleviating, or eliminating the aforementioned deficiencies and shortcomings in the art, either individually or in any combination. This object is achieved by a method for recovering a local clock of a first node (e.g., recovering a time including a time count of the local clock) after a service interruption of the first node in a system, the system comprising a memory, a second node, and one or more frequency oscillators, each oscillator being coupled to one or both of the first node and the second node.

[0004] According to one aspect, the method optionally includes continuously receiving an oscillator signal from one of the one or more oscillators in the first node and the second node, wherein the oscillator signal is used to maintain a local clock in the first node and the second node. The method further includes: receiving a first synchronization pulse from the second node in the first node; obtaining first data related to the first synchronization pulse in the first node; timestamping the received first synchronization pulse in the first node with a timestamp t1, the timestamp t1 being related to a time when the first synchronization pulse was received in the first node relative to the local clock; storing the timestamped first synchronization pulse and the obtained first data in a memory of the system; interrupting service of the first node; and restarting service of the first node.

[0005] On the one hand, restarting the service of the first node includes: retrieving information from the memory in the first node, the information including the first synchronization pulse and its timestamp t1 and the obtained first data; receiving a second synchronization pulse from the second node in the first node; obtaining second data related to the second synchronization pulse in the first node, wherein the first data and the second data enable the first node to estimate the time that has passed between the second synchronization pulse and the first synchronization pulse; in the first node, timestamping the received second synchronization pulse with a timestamp t2, which is related to the time when the synchronization pulse is received in the first node relative to the local clock; in the first node, estimating the time error E of the local clock of the first node based on the retrieved information, the timestamp t2 of the second synchronization pulse and the second data; and using the estimated time error to adjust the internal clock of the first node to restore the time of the local clock.

[0006] In an embodiment, the method includes: after timestamping the received second synchronization pulse, evaluating in the first node based on the retrieved information and the second data whether it is possible to synchronize the local clock of the first node based on the second synchronization pulse and the second data; and under the condition that synchronization based on information related to the second synchronization pulse is not possible, recovering the internal clock of the first node using a conventional clock recovery process (such as a conventional time transfer or synchronization process from an external system).

[0007] According to some aspects, the present disclosure further includes a system for implementing local clock recovery in a first node after a service interruption at the first node, the system comprising: a first node, the first node comprising a local clock, a communication interface that may include a transceiver, and a processing circuit; a second node, the second node comprising a local clock, a communication interface that may include a transceiver, and a processing circuit; one or more frequency oscillators, each of the one or more oscillators being connected to one or both of the first node and the second node; and a memory, wherein the system is configured to perform the above-mentioned and following methods.

[0008] Other objects and advantages will become apparent to those skilled in the art from a reading of the ensuing detailed description and the appended claims, wherein the detailed description proceeds with reference to the following illustrative drawings.

[0009] In general, unless otherwise expressly defined herein, all terms used in the claims should be interpreted according to their ordinary meaning in the art. Further, herein, the use of the terms "first," "second," and "third," etc. does not denote any order, quantity, or importance, but is used to distinguish one element from another. Unless otherwise expressly stated, all references to "a / an / the [element, device, component, means, step, etc.]" are open to interpretation as referring to at least one instance of the element, device, component, means, step, etc. Unless expressly stated otherwise, the steps of any method disclosed herein do not have to be performed in the exact order disclosed. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] The above and additional objects, features and advantages of the present invention will be better understood through the following illustrative and non-limiting detailed description of different embodiments of the present invention with reference to the accompanying drawings, in which:

[0011] Figure 1 An embodiment of the present invention is illustrated, comprising a system including a first node, a second node, a first oscillator and a second oscillator, and a memory.

[0012] Figure 2 An embodiment of the invention is illustrated in which an external approximate time source is used to approximate the time error used to adjust the time of clock C1.

[0013] Figure 3 An embodiment of the invention is illustrated in which metadata associated with the synchronization pulse is used to approximate a time error for adjusting the timing of clock C1.

[0014] Figure 4 An embodiment is illustrated wherein one oscillator provides an oscillator signal to both the first node and the second node.

[0015] Figure 5 An example of an embodiment of controlling a clock rate of a first node is illustrated.

[0016] Figure 6 An example of a system according to certain embodiments is illustrated.

[0017] Figure 7 An example of a system according to a general embodiment is illustrated.

[0018] Figure 8 is a block diagram illustrating a first node according to an embodiment.

[0019] Figure 9 is a block diagram illustrating a second node according to an embodiment.

[0020] Figure 10is a flowchart of a method of recovering time of a local clock of a first node according to an embodiment.

[0021] Figure 11 is a flowchart of a method for restarting a first node and restoring the time of a local clock of the first node according to an embodiment.

[0022] The figures are not necessarily drawn to scale and generally only show parts which are necessary in order to elucidate the inventive concept, wherein other parts may be omitted or merely suggested. DETAILED DESCRIPTION

[0023] The various aspects of the present disclosure will be described more fully below with reference to the accompanying drawings. However, the systems and methods disclosed herein can be implemented in many different forms and should not be interpreted as being limited to the aspects set forth herein. Throughout the text, the same reference numerals in the accompanying drawings refer to the same elements.

[0024] The terms used herein are for the purpose of describing particular aspects of the present disclosure only and are not intended to limit the present disclosure. Unless the context clearly indicates otherwise, as used herein, the singular forms "a / kind", "an / kind" and "the" are intended to include the plural forms as well.

[0025] In some embodiments, the non-limiting term "node" or "network node" is used. It should be understood that this term refers to any type of node that can send and / or receive information (such as data and control information) through a network. A physical node is typically an electronic device attached to a network and is capable of creating, receiving or transmitting information through a communication channel. The node can be data communication equipment (DCE) (such as a modem, hub, bridge, router or switch), or data terminal equipment (DTE) (such as a digital telephone handset, printer, server or main computer). It can refer to an integrated circuit (IC), such as a field programmable gate array (FPGA) or an application specific integrated circuit (ASIC). In one example, a node can be a computer terminal connected to a network such as a local area network (LAN), a wide area network (WAN) or the Internet. In another example, a node can be a synchronization device, such as a boundary clock or a global master clock (grandmaster) connected to a network.

[0026] The term "network" refers to any type of network (such as a local area network (LAN), a wide area network (WAN), or the Internet) through which network nodes can communicate. The network can use different network technologies, such as Ethernet, SDH, SONET, PDH, ATM, DTM, or IP. For example, the network can be called an Internet Protocol (IP) network, that is, a communication network that uses IP to send and receive messages between one or more nodes or computers that can be implemented in, for example, an Internet network, a WAN, a LAN, and an enterprise network. The service network can be used for mobile networks, such as 2G / 3G / 4G / 5G / 6G networks, power networks, financial technology (fintech) networks, or single frequency networks (SFNs), or media networks including digital television (DTV) or digital radio distribution networks.

[0027] The term "reset" in the context of resetting a node or system refers to any type of restart, readjustment, or restoration to a desired value. This includes rebooting a node or system.

[0028] The term "reboot" in the context of rebooting a node or system means restarting the node or system, which typically involves shutting down and restarting the node or system. Rebooting means reloading the computer's operating system, that is, restarting the computer. Booting means starting the computer's operating system, so rebooting refers to starting the computer for the second or third time.

[0029] The term "outage," as used in a node's "service outage," refers to an event that temporarily shuts down a node's normal operations (such as communication with other nodes) and its internal features (such as the processor, memory, and local clock), resulting in node downtime. "Downtime" refers to the time a machine (e.g., a computer) is inoperative or unavailable for use. Downtime refers to the time a node / system is not functioning properly, while uptime refers to the time a node / system is functioning properly.

[0030] A network node is a connection point in a communication network, such as a computer network. A node can refer to the basic unit of a data structure, such as a linked list or tree data structure, where a node contains data and can also be linked to other nodes, and can often be arranged in a tree structure. Each node is an endpoint for data transmission or redistribution. Nodes are programmed or engineered to recognize, process, and forward transmissions to other network nodes. Examples of nodes include bridges, switches, hubs, and modems that connect to other computers, printers, servers, clients, and peer devices. One of the most common forms of a node is a host computer, often called an Internet node. In telecommunications, node-to-node data transfer refers to the movement of data from one node to the next in a network. In the OSI model, this is handled by the bottom two layers: the data link layer and the physical layer.

[0031] Bipolar junction transistors, diodes, and field-effect transistors are commonly used electronic components in electronic circuits. These components, along with the necessary resistors and capacitors, are interconnected to form an electronic circuit. This type of circuit is called a discrete circuit because each component can be separated from the circuit when needed. It has become common to produce electronic circuits by permanently fabricating multiple diodes, transistors, and capacitors on a semiconductor wafer. This type of electronic circuit is called an integrated circuit (IC) because the components in this type of electronic circuit cannot be separated but are instead integrated on the semiconductor wafer. ICs are also commonly referred to as chips or microchips. Therefore, an integrated circuit (also called IC, chip, or microchip) is a group of electronic circuits on a small, flat piece (or "die") of semiconductor material, usually silicon. An IC is a semiconductor wafer with millions of tiny resistors, capacitors, and other components. ICs can be used for a variety of purposes, including amplifiers, video processors, computer memory, switches, and microprocessors.

[0032] Examples of integrated circuits include field programmable gate arrays (FPGAs) and application-specific integrated circuits (ASICs). The basic FPGA architecture consists of thousands of basic elements called configurable logic blocks (CLBs) surrounded by a programmable interconnect system called the fabric that routes signals between the CLBs. Input / output (I / O) blocks interface between the FPGA and external devices. Depending on the manufacturer, CLBs may also be called logic blocks (LBs), logic elements (LEs), or logic cells (LCs). More powerful FPGAs include functional blocks dedicated to specific functions, such as clock management components, phase-locked loops (PLLs), high-speed serializers and deserializers, Ethernet MACs, PCI Express controllers, and high-speed transceivers. FPGAs are used not only in telecommunications and networking applications, but also in consumer, automotive, and industrial applications.

[0033] FPGAs employ several blocks or flip-flops that operate in parallel across different interconnect paths and can operate at different frequencies. A clock enables the various flip-flops within a single FPGA to transition to new states at the clock's speed, allowing the FPGA to perform high-speed calculations or bit manipulation. A clock is a signal within any digital circuit that determines the operating speed of a flip-flop (or group of flip-flops). The clock signal connects to all flip-flops and RAM blocks and activates them based on the clock frequency. The faster the clock, the faster the design will run, and therefore, an FPGA with a higher clock speed will execute any desired function faster than one with a lower clock speed. A typical FPGA consists of several clock signals, allowing different areas of the FPGA to operate at different speeds. A single FPGA system will employ at least one clock, which generates a wave of a certain frequency that is distributed across the FPGA to synchronize the responses of all flip-flops involved in the design. An external oscillator placed on the circuit board generates a square wave or clock signal of a certain frequency and enters the FPGA system through a single physical connection pin. The clock signal is distributed along interconnects or wires called global routing or global lines, so that the signal is distributed and received simultaneously by every flip-flop. If the signal arrives at different flip-flops at different times, the time difference between the receipt of the clock pulses is called skew and can interfere with the performance of the system.

[0034] A single clock domain can be used to generate waves of multiple frequencies and run different components using the FPGA's PLL (phase-locked loop). The PLL takes a reference clock and multiplies it to generate very high frequencies in the gigahertz range, depending on the clock required by the equipment. That is, the code can be manipulated to change the frequency at which the clock enabler is pulsed, thereby determining the frequency of the resulting signal wave. Instead of using a dedicated clock for each component, a clock with a certain wave frequency (e.g., 50 MHz) is used and then pulsed periodically (every few cycles) to obtain a custom clock with a variable frequency.

[0035] In many cases, it's desirable to generate new clock signals and distribute them efficiently throughout the system. To this end, FPGAs utilize dedicated clock management blocks. Clock management blocks can generate new clock signals by performing clock multiplication and division, and may be able to apply programmable phase shifts to the generated clocks or even adjust the clock's duty cycle. These blocks can eliminate skew not only in clock signals distributed within the FPGA, but also in clocks distributed from the FPGA to other devices on the FPGA board. One application of the programmable phase shift feature is synchronizing clock signals with incoming data.

[0036] The local clock of the first node can be absolute, that is, corresponding to the time that the current wall clock, time of day, or conventional clock would display at the time instance in that particular place in the world. Instead of an absolute clock, a monotonic clock can be used in the first node. A monotonic clock is a time source that never jumps forward or backward (not affected by NTP or daylight saving time updates, etc.). Monotonic time represents the absolute past wall clock time since some arbitrary fixed point in the past and is not affected by changes in the system's time of day clock, where time is typically reported as a number of units (typically microseconds or nanoseconds) since some arbitrary moment. A monotonic clock increases monotonically over time. For example, a monotonic clock in an FPGA has a monotonic time whose rate is digitally controlled and starts from zero when the FPGA starts. Therefore, a monotonic clock includes a counter that counts the time from the previous moment to the current time, and restoring a monotonic clock involves restoring the clock to the count it would have had if no interruption had occurred. For example, if the local clock of the first node is a monotonic clock, then by knowing the number of synchronization pulses that passed during the downtime and the time between each synchronization pulse (the pulse interval), the time that passed during the downtime can be calculated, and the clock time can be recovered and the clock continues to run at the correct time.

[0037] In the classical context, the term synchronization (or synch for short) means the adjustment of the rhythm of self-sustaining periodic oscillators due to their weak interactions, which can be described in terms of phase locking and frequency capture. Phase synchronization refers to the process by which two or more cyclic signals tend to oscillate in a repeating sequence of relative phase angles. Phase synchronization is typically applied to two waveforms with the same frequency and the same phase angle per cycle. Synchronization measurements can include phase measurements, phase deviations, and analysis of phase time interval error, fractional frequency offset, maximum time interval error (MTIE), and time deviation (TDEV) taking into account a reference signal. The time of the local clock of a node in the present disclosure is typically maintained by using an oscillator signal continuously received from one of the oscillators (which can be the same or different). These oscillator signals can also be referred to as output or output signals.

[0038] Nodes that communicate with other nodes in the network need to be synchronized for efficient communication, such as distributed clocks. Time transfer in the network, such as for network synchronization (synchronization between nodes in the network), is critical to the functionality of the network. For example, many networks, such as packet-based networks, require frequency and time synchronization (phase alignment) between nodes for successful operation and packet delivery, and many applications and services require the network to distribute accurate time and frequency to their nodes, such as mobile base stations, radio and TV transmitters, sensors, etc. Operators can also provide synchronization services to their customers for use in applications such as servers or machines or in self-driving cars. Synchronization in distributed systems is achieved via clocks. Physical clocks are used to adjust the time of nodes. Each node in the system can share its local time with other nodes in the system. The network synchronization task is to distribute reference signals from a primary reference clock (PRC) to all network elements that need to be synchronized. The method used to propagate reference signals in the network is typically a master-slave approach (also known as controller-responder, primary-replica, and leader-follower approaches), i.e., a hierarchical model in which a slave or responding clock must be subordinate to (must respond to) a clock of greater (or equal) stability. Synchronization information is transmitted through the network via synchronization network connections. Synchronization network connections are typically unidirectional and often point-to-multipoint. A centralized timing network architecture or a distributed timing network architecture (e.g., using a Global Navigation Satellite System (GNSS)) can be used.

[0039] Time (relative and absolute) and frequency transfer describe mechanisms for comparing time and frequency measurements from one location to another. Time transfer is a scheme where multiple sites share a precise reference time. Various techniques have been developed to transfer reference clock synchronization from one point to another, often over long distances. Time transfer can be used to synchronize time between different entities or nodes in a network, which is critical to the network's functionality. Packet-based frequency allocation from a reference clock to a recovered clock involves the steps of signal generation, packet transfer, including transmission of the packets over a packet network, and signal recovery.

[0040] Technologies for synchronizing network nodes without GPS include, for example, the Network Time Protocol (NTP), which can be used to synchronize the clocks of network nodes to a master or reference clock using timestamps. The Precision Time Protocol (PTP) is a protocol for synchronizing clocks throughout a computer network, also known as IEEE 1588. IEEE 1588-2019 includes a profile concept, also known as a default profile or standard profile, that defines PTP operating parameters and options. Several profiles have been defined for applications including telecommunications, power distribution, and audio-visual. The earlier IEEE 1588-2008 introduced clocks associated with network equipment used to transmit PTP messages. There are five basic types of PTP devices ("clocks"): ordinary clocks (master or slave), boundary clocks ("master and slave"), end-to-end transparent clocks, peer-to-peer transparent clocks, and management nodes. All five types implement one or more aspects of the PTP protocol. Transparent clocks modify PTP messages as they pass through devices. The timestamps in the messages are corrected for the time taken to traverse the network equipment. The scheme improves allocation accuracy by compensating for delivery variability across the network.PTP messages may be transmitted using User Datagram Protocol over Internet Protocol (UDP / IP).

[0041] In some cases, the node will be unavailable and will not receive any oscillator signals or synchronization messages. When a node is shut down or temporarily unavailable (such as restarting due to being upgraded), the node will have to start the time recovery or synchronization process from the beginning, and node synchronization may typically take about 1000s to stabilize and the node can pass time again. During this startup period, the functionality of the node or system will be impaired. Therefore, an object of the present disclosure is to minimize the time it takes for a node or system to recover the correct time after an interruption (such as a reset or reboot).

[0042] Therefore, an enhanced method for recovering the time of a local clock after a service interruption (such as a reset or reboot) is provided, wherein the node time is maintained in a secondary node during the reboot. This recovery includes correcting the clock based on the estimated time error. This recovery of the correct time or maintenance of the clock can be considered as synchronization or "resynchronization" of the node in some cases. In an example, the operation of a first FPGA (such as a primary FPGA) is interrupted, for example, due to a reset or reboot, and it will require clock recovery to return to service after the interruption. During the interruption, the node time is maintained in a secondary node (such as a secondary FPGA), rather than performing clock recovery or synchronization from scratch (which takes a long time). For example, during a reboot, the secondary FPGA maintains the node time while the rest of the system reboots. When the primary FPGA is put back into use, it resumes maintaining the node time.

[0043] This means that the local clock or node synchronization will effectively enter a holdover state, but the clock and node synchronization will not be available during the reboot. However, after the reboot, its recovery speed will be much faster than a full (cold) start. For example, the length of the holdover state can be about 100 seconds (depending on the oscillator performance), which may be acceptable to the end user (e.g., 5G base station).

[0044] Therefore, the present disclosure enables the time of the local clock of the first node to be restored after a service interruption by adjusting the time after the restart based on the approximate time error, i.e., maintained as if no downtime had been experienced. The clock can be monotonic or absolute, and the time error can be approximated in different ways depending on the type of clock.

[0045] As an example, a running clock is monotonic or absolute and can be maintained aligned with an external time or frequency, for example, by using time transfer. For some reason, a first node's service is interrupted, such as when the clock needs to be restarted or a power outage forces a restart. When the clock is restarted, operation must be resumed. If the clock is monotonic, it must resume counting from the last time it was operational. A naive approach is to store the clock value before the reboot and then start from that value upon reboot. This results in a time error equal to the duration of the downtime. This could be seconds, minutes, or even longer, which is unacceptable for many applications. If the clock is absolute and uses time transfer, using conventional time transfer to reestablish time has disadvantages. This is because time transfer requires some time to establish and converge, which can cause the clock to be unavailable for longer than necessary. Minimizing downtime is highly desirable. Therefore, the present disclosure aims to restore operation and the time of a local clock in a node, with the error not exceeding the error caused by the oscillator's inherent frequency drift during the interruption. Typically, a high-quality oscillator can drift by 0.1 ppb during a 100-second reboot. Therefore, the error introduced by the redirection will be less than 10ns.

[0046] Thus, in one embodiment of the presently disclosed method, a first node continuously receives an oscillator signal from one of one or more oscillators, wherein the time of the first node's local clock can be maintained based on the oscillator signal, and wherein execution of the first node can be clocked by the one oscillator. Correspondingly, a second node also continuously receives an oscillator signal from one of the one or more oscillators, wherein the time of the second node's local clock can be maintained based on the oscillator signal. The oscillators can be the same, i.e., the first node and the second node receive the oscillator signal from the same oscillator, or they can be different, such that the first node and the second node receive the oscillator signal from two different oscillators.

[0047] A first node and a second node and one or more oscillators are present in the system. A synchronization pulse is transmitted from the second node to the first node. The synchronization pulse can be transmitted irregularly, on request or repeatedly at a constant interval, called the synchronization pulse interval or simply the pulse interval. Depending on the application, the frequency of such repeatedly transmitted synchronization pulses may be low, such as having a pulse interval of seconds or minutes, and thus much lower than the frequency of the continuously transmitted oscillator pulses. The frequency of the synchronization pulses can also be higher, such as one million pulses per second. The first node knows the pulse interval, which can be stored in a memory in the system for retrieval by the first node, or it can be sent from the second node to the first node in the synchronization pulse or in a separate transmission. Thus, the first node will obtain information about the pulse interval p, for example by retrieving it from a memory or by receiving said information. iv Each synchronization pulse will be timestamped in the first node, where the timestamp is relative to the time when the synchronization pulse was received in the first node relative to its local clock. Therefore, when the first node is in service and its local clock is running, the time between two timestamps should be equal to the pulse interval. However, when the service of the first node is interrupted, the timestamps of the last synchronization pulse received before the interruption (the first synchronization pulse) and the first synchronization pulse received after the interruption (the second synchronization pulse) will be longer, and the clock must be adjusted accordingly to restore the correct time.

[0048] Each synchronization pulse will have data associated with it, which is obtained in the first node. This data can be sent in the same transmission as the synchronization pulse, or separated from the transmission, such as sent in a separate transmission. The timestamp of the received synchronization pulse and its associated data can be stored in a memory in the system, wherein the memory can be within the first node or located elsewhere in the system. Therefore, the first node will store the last received synchronization pulse (first synchronization pulse) and its associated data (first data) in the memory before the service interruption, and can then retrieve this information upon restart. Therefore, after the interruption, when the first node and its local clock are restarted, the first node will receive a synchronization pulse (second synchronization pulse). The elapsed time perceived in the first node can be obtained by using synchronization pulses with timestamps, but the actual elapsed time in the second node is more difficult to determine. This can be performed in different ways as shown below.

[0049] If the local clock of the first node keeps monotonic time, the data will include so-called metadata d, which includes information about the synchronization pulse count for each corresponding synchronization pulse. Thus, the metadata enables the first node to determine which pulse count the current synchronization pulse has, and thus to use two such metadata to determine the number of pulses that have passed between the two pulses. Optionally, the data will also include the pulse interval p iv , or the pulse interval can be obtained by the first node in other ways. Therefore, the time error for adjusting the local clock in the first node between the synchronization pulse received before the service interruption and the synchronization pulse received after the service interruption can be determined based on the metadata and the timestamps of the corresponding synchronization pulses. Therefore, the time error for adjusting the local clock to restore the time of the local clock of the first node can be calculated as E=e2-e1, where E is the time error. e1 is the apparent elapsed time in the first node, that is, the time elapsed between the two synchronization pulses in the first node, which is determined / calculated based on the timestamp t1 of the first synchronization pulse received before the interruption and the timestamp t2 of the second synchronization pulse received after the interruption, where e1=t2-t1. e2 is the apparent elapsed time in the second node, that is, the pulse count elapsed between the two synchronization pulses in the second node, which is determined / calculated based on the metadata (synchronization pulse count for each corresponding synchronization pulse), d1 is the metadata of the first synchronization pulse received before the interruption, and d2 is the metadata of the second synchronization pulse received after the interruption, where e2=(d2-d1)*p iv , where p iv is the pulse interval.

[0050] If the local clock of the first node keeps absolute time, the data will include the approximate absolute time a related to the approximate absolute time when the first synchronization pulse or the second synchronization pulse, respectively, was received in the first node. Optionally, it will also include the pulse interval p iv, or the pulse interval can be obtained by the first node in other ways. Therefore, the time error for adjusting the local clock in the first node between the synchronization pulse received before the service interruption and the synchronization pulse received after the service interruption can be determined based on the data and the timestamps of the corresponding synchronization pulses. Therefore, the time error for adjusting the local clock to restore the time of the local clock of the first node can be calculated as E=e2-e1, where E is the time error. e1 is the apparent elapsed time in the first node, that is, the time elapsed between the two synchronization pulses in the first node, which is determined based on the timestamp t1 of the first synchronization pulse received before the interruption and the timestamp t2 of the second synchronization pulse received after the interruption, where e1=t2-t1. e2 is the apparent elapsed time in the second node, i.e. the absolute time elapsed between the two synchronization pulses in the second node, which is determined / calculated based on the data (the approximate absolute times a of the respective synchronization pulses), a1 is the approximate time for the transmission of the first synchronization pulse received in the first node before the interruption, and a2 is the approximate time for the transmission of the second synchronization pulse received in the first node after the interruption, i.e. a2-a1, wherein the pulse interval can be used to round e2 to the interval length p iv The closest multiple of , thus giving e2 = round (a2 - a1, p iv ).

[0051] In the method of the present invention, at least two synchronization pulses are required: one before the interruption and one after the interruption. As long as the timestamp and related data are known, the time error can be determined. In some embodiments, the second node repeatedly transmits synchronization pulses before the service interruption, wherein one synchronization pulse before the interruption (typically the last received synchronization pulse) can be used as the first synchronization pulse in the time error estimate. In another embodiment, information related to several synchronization pulses before the interruption is used and averaged to obtain a better estimate.

[0052] Figure 1The diagram illustrates an embodiment of the present invention, including a system comprising a first node N1 with a local clock C1, a second node N2, a first oscillator O1 that provides an oscillator signal to the first node, a second oscillator O2 that provides an oscillator signal to the second node, and memory connected to the first node. During normal operation, synchronization pulses are repeatedly sent from the second node to the first node. In this case, C1 is the clock that is desired to be restarted. N2 is a secondary system. N2 can be connected or disconnected from N1. It is crucial that N2 does not shut down / restart when N1 restarts. If it does shut down / restart, this must be detected in some way so that N1 knows it cannot trust the data coming from it. The synchronization pulse from N2 is timestamped by N1. Before restarting, N1 remembers the last synchronization pulse and stores it in memory. After restarting, N1 reads back the timestamp of the last stored synchronization pulse. It waits for the next synchronization pulse from N2 and timestamps it. It can now compensate its own clock C1 so that the elapsed time between the stored timestamp and the current timestamp equals the elapsed time on N2. This compensation / adjustment will be performed differently depending on the type of time C1 is maintained, as described above.

[0053] In the simplest case, the synchronization pulse has no external information. If it is set to occur at fixed intervals (say 10 seconds), the elapsed time will be known in multiples of at most 10 seconds. This ambiguity can be resolved in a number of ways.

[0054] Figure 2 The diagram shows Figure 1 An embodiment of the present invention in a similar system. In this embodiment, an external approximate time source is used to approximate the time error used to adjust the time of clock C1. N1 can query some external source, which does not need to be accurate compared to the synchronization pulse from N2. For example, an NTP server or a battery-powered RTC (real time clock) clock can be used. The difference in the approximate time a when the synchronization pulse before and after the restart is received can be rounded to a multiple of the synchronization pulse interval, which information can be previously known to N1 (such as using a fixed interval of 10s) or can be retrieved from a memory or sent from N2 to N1. The estimated time error can then be calculated as E=e2-e1, where e2 is based on using p iv Round a2-a1, as above.

[0055] Figure 3 The diagram shows Figure 1An embodiment of the present invention in a similar system. In this embodiment, metadata d associated with the synchronization pulse is used to approximate the time error used to adjust the time of clock C1. If N2 can signal metadata associated with the synchronization pulse, the ambiguity can be eliminated without an external source. For example, a pulse count can be used, which can be signaled externally via some data channel from N2 to N1. The pulse count can also be encoded into the synchronization pulse as a pulse train. The leading edge is the synchronization pulse, and the rest of the pulse train encodes the message containing the pulse count. Encoding the signal into the synchronization pulse itself makes it possible to have very short intervals between synchronization pulses, which allows for faster restarts. The estimated time error can then be calculated as E=e2-e1, where e2 is d2-d1, as described above.

[0056] Therefore, the basic principles of the above embodiment can be summarized in the following steps: 1. N1 stores the timestamp t1 when the synchronization pulse from N2 arrives and the metadata d1 or approximate time a1 about the synchronization pulse. This is stored in an external (or internal) memory. 2. N1 restarts. 3. N1 waits for the next synchronization pulse from N2. 4. N1 stores the timestamp t2 of the synchronization pulse and the metadata d2 or approximate time a2. 5. The apparent elapsed time on N1 is e1 = t2 - t1. 6. The apparent elapsed time e2 on N2 is determined based on d1 and d2 or a1 and a2; i) If pulse counting is used: e2 = pulse count difference multiplied by the pulse interval length d2 - d1*p iv ii) If NTP is used, the NTP time difference at a1 and a2 is rounded to the nearest multiple of the interval length, e2 = rounded (up or down) the approximate time difference a2-a1, that is, e2 = round(a2-a1, p iv By stepping time e2 - e1 to compensate for the time at N1, clock C1 is adjusted to restore C1's accurate time. This is the basic principle. In practice, accuracy can be improved by using more than two pulses and using an estimate of the frequency error of the oscillator(s). Therefore, by averaging several pulses, a more accurate result can be obtained.

[0057] In the above examples, the first node and the second node receive oscillator signals from different oscillators. However, it is also possible to use only the same oscillator. Figure 4 As shown in FIG, in an embodiment, the system includes a first node N1, a second node N2, a memory, and an oscillator that provides an oscillator signal to both N1 and N2. This reduces costs. Furthermore, N1 can benefit from having a better model of oscillator drift, which can be used to refine the estimate of the time elapsed on N2.

[0058] In order for the time error correction to work, the time / operation of N2 must be maintained during the downtime of N1. Therefore, in order for normal recovery to occur, N2 must not be out of service / restarted when N1 restarts. This could happen, for example, if there is a power outage. There are several possible ways to detect that N2 has also experienced downtime. One way to detect this is for N2 to choose a random token on each startup and pass it along with the metadata channel with each sync pulse. N1 stores the token and timestamp. If N2 experienced downtime, it will therefore choose a new token on restart. N1 can check the token of the first pulse received after restart and if it matches the stored token (before restarting the first node), it ensures that N2 has not restarted.

[0059] In another embodiment, Figure 5 As shown in Figure 1, the clock rate of N1 is controlled. This is the case if N1 uses time transfer and is frequency and / or time synchronized with some external system. All oscillators have errors and drift. N1 can use an estimate of the frequency error of its oscillator to improve the accuracy of its estimate of the time elapsed on N2. The clock C1 in N1 can be digital and controlled, while the external oscillator is fixed. Another possibility is that the oscillator is frequency manipulated. In both cases, it is possible to adjust for frequency error when estimating the time elapsed on N2.

[0060] In some embodiments, a Figure 6 A system for recovering the time of a local clock after a service interruption. The system includes a first node (10), a master FPGA having a local clock, a second node (20), a slave FPGA transmitting a synchronization pulse to the first node, and an oscillator (115) transmitting an oscillator signal to the first node and the second node.

[0061] exist Figure 7In another illustrated embodiment, a system (100) is provided for enabling time recovery of a local clock (15) in a first node (10) after a service interruption in the first node (10), the system comprising: a first node (10), the first node comprising a local clock (15), a communication interface (11), and a processing circuit (12); a second node (20), the second node comprising a local clock (25), a communication interface (21), and a processing circuit (22); one or more frequency oscillators (115A, B), each of the one or more oscillators (115A, B) being connected to one or both of the first node (10) and the second node (20); a memory (35A, B, C), wherein the memory may be part of the first node (35A), separate from the first node but located within the system (35B), or located external to the system, such as in a cloud (35C); wherein the system is configured to perform the above and following methods. Figure 8 and Figure 9 , a block diagram of a respective first node and a second node is depicted, wherein the first node (10) comprises a local clock (15), a communication interface (11) and a processing circuit (12), and optionally a memory (35A), and the second node (20) comprises a local clock (25), a communication interface (21) and a processing circuit (22).

[0062] System requirements (hardware requirements) include connections from an oscillator to both nodes, and a connection from the second node to the first node (carrying the synchronization pulse on this connection). In some aspects, the firmware of the first node (also referred to as the primary FPGA) should timestamp the synchronization pulse with the timestamp t, just as it timestamps, for example, the PPS (pulse per second) with t. The firmware of the second node (also referred to as the secondary FPGA) should disable the synchronization output during boot. Therefore, the first node and the second node can include a first FPGA and a second FPGA, respectively, which can be referred to as the primary FPGA and the secondary FPGA. There should be no spurious synchronization pulses during boot. The value of N can be set within a reasonable range.

[0063] In some aspects, the system includes: i) a fixed frequency oscillator, which is assumed to be on throughout the restart / reboot period; ii) a first node (e.g., a master FPGA) whose execution is clocked by the oscillator; and a digital clock in the master FPGA with monotonic time, whose rate is digitally controlled (e.g., within +-10 ppm) and which starts from zero when the FPGA starts; iii) a second node (e.g., a slave FPGA) connected to the oscillator, which may or may not be clocked by the oscillator; iv) a connection between the two FPGAs such that the slave FPGA can signal the master FPGA by raising its output, and the master FPGA can accurately capture the time with a timestamp t; v) a control process ("synchronization application") that, in addition to calculating control signals for the digital clock, maintains a clock offset that is added to t to yield the absolute time when the nodes are synchronized; and vi) a memory for persistent storage of data. The synchronization application can be executed by processing circuitry in the first node.

[0064] After a restart, the master FPGA and the synchronization application, the time count will start again from zero. Then, NTP or another mechanism with absolute time capability can be used to obtain an approximately correct time offset. When the synchronization pulse comes in, its absolute time is obtained by using tgi (the exact value) and the offset (the approximate value at this time).

[0065] In a practical implementation, the synchronization pulse is observed using the same mechanism used to estimate the frequency input. This smooths the discretization error. After a restart / reboot, the control signal is set to a sane value (the estimated frequency error, with the opposite sign). This reduces the impact of observation / control signal delays. Several synchronization pulse values ​​are observed to smooth the discretization error. It will temporarily be treated as an absolute time source like the PPS, but adjustments will be made as errors in the frequency oscillator must be compensated.

[0066] The present disclosure relates to the case where only the first node of the system is restarted (the second node is not restarted). For a complete reboot or cold start of the system (wherein the second node also experiences downtime), time cannot be maintained. During the restart, at least the oscillator and the second node need to run uninterrupted. If the second node needs to be updated and rebooted, this operation can be performed from the perspective of the synchronization application. The first node will continue to operate normally. The synchronization pulse between the two nodes is only used during the restart of the first node. Therefore, the present disclosure relates to a method for enhanced restart of a node after an interruption. The service interruption of the first node may be sudden and unplanned, or it may be planned. Therefore, in an embodiment, before the system interrupts the service of the first node and restarts, the first node indicates to the upper layer that it is ready to restart. In this case, the synchronization pulse transmission can start just before the planned downtime.

[0067] In some embodiments, the synchronization application is aware of the reboot and establishes that necessary conditions are in place, such as that node time is stable, absolute time (or pulse count) is known, and the estimated uncertainty of the oscillator drift model is low enough to be trustworthy. The synchronization application can instruct the second node (slave FPGA) to output a pulse to the first node (master FPGA) every N clock cycles of the oscillator. N can be chosen large enough to correctly distinguish pulses from each other. N is chosen small to minimize latency and to average out sampling discretization errors (FPGA actions occur in clock cycles). A reasonable value for N will produce values ​​similar to 1Hz pulses. The master FPGA sends observations of the synchronization pulse, timestamped with tgi, to memory associated with the synchronization application. When the synchronization application is satisfied with the observations, it stores its state in persistent storage, including the uncertainty of the absolute time, the estimated oscillator drift parameters (including at least the current frequency error), and the phase of the synchronization pulse as tgi + tgoffs. The synchronization application then signals to higher layers that it is ready to reboot itself and the master FPGA. The master FPGA reboots, and the synchronization application is started by higher layer control (such as the system or similar system). This includes, for example, i) the master FPGA starts counting, which will count tgi from zero; ii) the control signal of the digital clock will be zero; iii) the synchronization application reads from the memory (persistent storage device) and finds that it may have data to perform an enhanced restart; iv) assuming that the slave FPGA has not been rebooted, it will still send synchronization pulses to the master FPGA, and the master FPGA will record these pulses and send them as observations to the synchronization application; v) the synchronization application queries the slave FPGA for the pulse count or by using a rough time from NTP; vi) the synchronization application uses the stored information together with the most recent synchronization pulse observations to find out whether all conditions for recovery time are met (for example, the enhanced restart / reboot time must be within reasonable limits and the synchronization pulse observations must be within a reasonable range), and if not, a normal restart / boot occurs instead; vii) the initial state of control is calculated using a combination of the stored information and the most recent synchronization pulse observations, where the most important parts of the state are the clock signals and tgoffs, where control is started using these values; viii) when the initial control has converged (essentially treating the synchronization pulses as an absolute time source), the synchronization application can switch to normal control.

[0068] Now refer to Figure 10 and Figure 11 The proposed method is described in more detail. It should be understood that Figure 10 and Figure 11The diagram includes some operations and modules illustrated with solid borders and some operations and modules illustrated with dashed borders. The operations and modules illustrated with solid borders are operations included in the broadest example embodiment. The operations and modules illustrated with dashed borders are example embodiments, which may be included in or part of the operations and modules of the broader example embodiment, or may be further embodiments that can be adopted in addition to the operations and modules of the broader example embodiment. It should be understood that the operations do not need to be performed in order. In addition, it should be understood that not all operations need to be performed.

[0069] Figure 10 A method for recovering the time of a local clock of a first node after a service interruption of the first node in a system is illustrated, the system comprising a memory, a second node and one or more frequency oscillators, each oscillator being connected to one or both of the first node and the second node, the method comprising: optionally, continuously receiving (S0) an oscillator signal from one of the one or more oscillators in the first node and the second node, wherein the clock oscillator signal is used to maintain the local clock in the first node and the second node; and wherein these oscillator signals received in the first node and the second node, respectively, are from the same frequency oscillator or from different frequency oscillators. The method further includes receiving (S1) a first synchronization pulse from a second node in the first node; obtaining (S2) first data related to the first synchronization pulse in the first node; timestamping (S3) the received first synchronization pulse in the first node with a timestamp t1, which is related to the time when the first synchronization pulse is received in the first node relative to the local clock; storing (S4) the timestamped first synchronization pulse and the obtained first data in a memory of the system; interrupting (S5) the service of the first node; restarting (S6) the service of the first node; and adjusting (S7A) the internal clock of the first node using the estimated time error to restore the time of the local clock.

[0070] In some embodiments, synchronization pulses are repeatedly transmitted / received at a certain pulse interval, and the method includes: repeatedly receiving (S1) first synchronization pulses from a second node in a first node; repeatedly obtaining (S2) first data related to the first synchronization pulses in the first node; in the first node, timestamping (S3) each received first synchronization pulse with a timestamp t1, which is related to the time when the corresponding first synchronization pulse is received in the first node relative to the local clock; and storing (S4) each timestamped first synchronization pulse and the obtained first data in a memory of the system.

[0071] Figure 11A method for restarting (S6) the service of the first node in the above method is illustrated, wherein the restart includes: retrieving (S61) information from a memory in the first node, the information indicating a first synchronization pulse and its timestamp t1 and the obtained first data; receiving (S62) a second synchronization pulse from the second node in the first node; obtaining (S63) second data related to the second synchronization pulse in the first node, wherein the first data and the second data enable the first node to estimate the time that has passed between the second synchronization pulse and the first synchronization pulse; in the first node, timestamping (S64) the received second synchronization pulse with a timestamp t2, which timestamp t2 is related to the time when the synchronization pulse is received in the first node relative to the local clock; optionally, in the first node, evaluating (S65) whether it is possible to adjust the time of the local clock of the first node based on the second synchronization pulse and the second data; and under the condition that it is not possible to adjust the time of the local clock based on the information related to the second synchronization pulse; adjusting (S7B) the internal clock of the first node using a conventional time transfer or synchronization process. In some embodiments, the evaluation can be performed using tokens, wherein the first data and the second data include a first random token and a second random token, the random tokens being reselected each time the second node restarts, and wherein evaluating (S65) whether it is possible to adjust the synchronization of the local clock of the first node based on the second synchronization pulse and the second data comprises: comparing (S651) the first random token with the second random token; and, if the first random token and the second random token are identical, determining (S652A) that it is possible to adjust the local clock of the first node based on the second synchronization pulse and the second data; or, if the first random token and the second random token are different, determining (S652B) that it is not possible to adjust the local clock of the first node based on the second synchronization pulse and the second data. The presence of the new token indicates that the second node has also restarted and therefore the time given by its synchronization pulse cannot be trusted. If adjustment of the time of the local clock based on the information related to the second synchronization pulse is possible or not evaluated, the method further includes: in the first node, estimating (S66A) the time error E of the local clock of the first node based on the retrieved information, the timestamp t2 of the second synchronization pulse and the second data; and using the estimated time error to adjust (S7A) the internal clock of the first node to recover the time of the local clock.

[0072] In some embodiments, obtaining (S2) first data associated with the first synchronization pulse includes obtaining (S2A) first data including first metadata d1 for the first synchronization pulse from the second node, and obtaining a pulse interval p associated with a time interval between two consecutive synchronization pulses. ivwherein the pulse interval can be obtained from the second node or from a memory, and wherein obtaining (S63) second data related to the second synchronization pulse comprises: obtaining (S63A) second data comprising second metadata d2 for the second synchronization pulse from the second node, wherein the first metadata and the second metadata comprise information of a synchronization pulse count for each respective synchronization pulse. In this embodiment, estimating (S66A) a time error E of the local clock of the first node comprises: estimating (S66A) the time error E as e2-e1, wherein e1 is an apparent elapsed time in the first node determined based on the timestamps as e1=t2-t1, and e2 is determined based on the metadata and the pulse interval as e2=(d2-d1)*p iv an apparent elapsed time in the second node of the first node, where t1 is a timestamp of a first synchronization pulse received before the service interruption of the first node and d1 is metadata of the first synchronization pulse received before the service interruption of the first node, and t2 is a timestamp of a second synchronization pulse received after the service restart of the first node and d2 is metadata of the second synchronization pulse received after the service restart of the first node.

[0073] In another embodiment, obtaining (S2) first data related to the first synchronization pulse comprises obtaining (S2B) first data comprising an approximate absolute time a1 related to an approximate absolute time when the first synchronization pulse is received in the first node, and optionally a pulse interval p related to a time interval between two consecutive synchronization pulses. iv ; and; wherein obtaining (S63) second data associated with the first synchronization pulse comprises: obtaining (S63B) second data comprising an approximate absolute time a2 associated with the approximate absolute time when the second synchronization pulse is received in the first node. In this embodiment, estimating (S66A) a time error E of the local clock of the first node comprises: estimating (S66B) the time error E as e2-e1, wherein e1 is an apparent elapsed time in the first node determined based on the timestamps as e1=t2-t1, and e2 is an approximate absolute time determined using p iv The apparent elapsed time in the second node rounded to e2 = a2 - a1, where t1 is the timestamp of the first synchronization pulse received before the service interruption of the first node, and a1 is the approximate absolute time of the first synchronization pulse received before the service interruption of the first node, and t2 is the timestamp of the second synchronization pulse received after the service of the first node is restarted, and a2 is the approximate absolute time of the second synchronization pulse received after the service of the first node is restarted, and where e2 is rounded to or the pulse interval p ivThe approximate absolute time can be obtained from any available source, such as a battery-powered real-time clock (RTC) or a Network Time Protocol (NTP) server. Calling the server using, for example, the http protocol will give a response including a rough timestamp. Any source that can give a time indication with a reasonable accuracy depending on the application can be used.

[0074] In the above embodiments, obtaining (S2, S63) the first data or the second data includes receiving a separate transmission including the first data or the second data, or receiving the first data or the second data within each synchronization pulse transmission from the second node, for example by encoding a pulse count into the synchronization pulse as a pulse train.

[0075] The service interruption may be caused by a reset, restart, or reboot of the first node, which may be planned (e.g., for a system upgrade) or unplanned (e.g., due to a power outage, etc.). In some embodiments, the first node is a field programmable gate array (FPGA). The second node may also be a field programmable gate array (FPGA), wherein the first node is a primary FPGA and the second node is a secondary FPGA.

[0076] Thus, the present disclosure enables enhanced restarting of the first node after a service interruption when the first node is part of a system that includes a secondary node that does not restart and thus can preserve the time of the first node during the outage.

[0077] In the drawings and description, exemplary aspects of the present disclosure have been disclosed. However, many variations and modifications may be made to these aspects without departing substantially from the principles of the present disclosure. Therefore, the present disclosure should be considered illustrative rather than restrictive, and is not limited to the specific aspects discussed above. Therefore, although specific terms are employed, these terms are used in a generic and descriptive sense only and not for purposes of limitation.

[0078] The description of the example embodiments provided herein has been presented for illustrative purposes. This description is not intended to be exhaustive or to limit the example embodiments to the precise form disclosed, and modifications and variations are possible in light of the above teachings or may be obtained from practicing various alternatives to the provided embodiments. The examples discussed herein are selected and described to explain the principles and properties of the various example embodiments and their practical applications so that those skilled in the art can utilize the example embodiments in various ways and with various modifications suitable for the intended specific use. The features of the embodiments described herein may be combined in all possible combinations of methods, products, and systems. It should be understood that the example embodiments presented herein may be practiced in any combination with each other.

[0079] It should be noted that the word "comprising" does not necessarily exclude the presence of other elements or steps than those listed, and the word "a" or "an" preceding an element does not exclude the presence of a plurality of such elements. It should also be noted that any reference signs do not limit the scope of the claims, and example embodiments can be implemented in the broadest sense of the claims.

Claims

1. A method for restoring time of a local clock of a first node in a system after a service interruption of the first node, the system comprising a memory, a second node, and one or more frequency oscillators, each oscillator being connected to one or both of the first node and the second node, the method comprising: receiving, in the first node, a first synchronization pulse (S1) from the second node; Obtaining first data related to the first synchronization pulse in the first node (S2); In the first node, time stamping the received first synchronization pulse with a time stamp t1, the time stamp t1 being related to a time when the first synchronization pulse was received in the first node relative to the local clock (S3); storing the time-stamped first synchronization pulse and the obtained first data in a memory of the system (S4); interrupting the service of the first node (S5); Restarting the service of the first node (S6), the restarting comprising: Retrieving information from the memory in the first node, the information indicating the first synchronization pulse and its time stamp t1 and the obtained first data (S61); receiving, in the first node, a second synchronization pulse from the second node (S62); obtaining, in the first node, second data associated with the second synchronization pulse, wherein the first data and the second data enable the first node to estimate a time that has elapsed between the second synchronization pulse and the first synchronization pulse (S63); In the first node, time stamping the received second synchronization pulse with a time stamp t2, the time stamp t2 being related to a time when the synchronization pulse was received in the first node relative to the local clock (S64); In the first node, the time error E of the local clock of the first node is estimated based on the retrieved information, the timestamp t2 of the second synchronization pulse and the second data (S66A); and the internal clock of the first node is adjusted using the estimated time error to recover the time of the local clock (S7A).

2. The method of claim 1, further comprising: An oscillator signal (S0) is continuously received in the first node and the second node from one of the one or more oscillators, wherein the oscillator signal is used to maintain a local clock in the first node and the second node.

3. The method according to claim 1, wherein: Obtaining first data associated with the first synchronization pulse (S2) includes: Obtaining first data including first metadata d1 for the first synchronization pulse from the second node and a pulse interval p related to a time interval between two consecutive synchronization pulses iv (S2A), and; Wherein, obtaining second data related to the second synchronization pulse (S63) includes: obtaining second data including second metadata d2 for the second synchronization pulse from the second node (S63A), The first metadata and the second metadata include information on a synchronization pulse count of each corresponding synchronization pulse.

4. The method according to claim 3, wherein: Estimating the time error E of the local clock of the first node (S66A) includes: The time error E is estimated as e2-e1 (S66A), where e1 is the apparent elapsed time in the first node determined based on the timestamp as e1=t2-t1, and e2 is determined based on the metadata and the pulse interval as e2=(d2-d1)*p iv The apparent elapsed time in the second node is t1, where t1 is the timestamp of the first synchronization pulse received before the service interruption of the first node and d1 is the metadata of the first synchronization pulse received before the service interruption of the first node.

5. The method according to claim 1 to 2, wherein: Obtaining first data associated with the first synchronization pulse (S2) includes: Obtaining first data comprising an approximate absolute time a1 associated with an approximate absolute time when the first synchronization pulse is received in the first node, and a pulse interval p associated with a time interval between two consecutive synchronization pulses iv (S2B); and; Wherein, obtaining second data related to the first synchronization pulse (S63) includes: Second data including an approximate absolute time a2 associated with the approximate absolute time when the second synchronization pulse is received in the first node is obtained (S63B).

6. The method according to claim 5, wherein: Estimating the time error E of the local clock of the first node (S66A) includes: The time error E is estimated as e2-e1 (S66B), where e1 is the apparent elapsed time in the first node determined based on the timestamp as e1=t2-t1, and e2 is determined based on the approximate absolute time (a2-a1) and rounded to the pulse interval p iv The apparent elapsed time in the second node is the closest multiple of iv ), where t1 is the timestamp of the first synchronization pulse received before the service interruption of the first node, and a1 is the approximate absolute time of the first synchronization pulse received before the service interruption of the first node.

7. The method according to claims 5 to 6, wherein: The approximate absolute time is obtained from a battery-powered real-time clock (RTC) or a Network Time Protocol (NTP) server.

8. The method according to claims 1 to 7, wherein The obtaining of the first data or the second data (S2, S63) includes receiving a separate transmission including the first data or the second data, or receiving the first data or the second data within each synchronization pulse transmission from the second node.

9. The method according to claims 1 to 8, further comprising: In the first node, evaluating based on the retrieved information and the second data whether it is possible to adjust the time of the local clock of the first node based on the second synchronization pulse and the second data (S65); as well as Under the condition that it is not possible to adjust the time of the local clock based on the information associated with the second synchronization pulse; The internal clock of the first node is adjusted using conventional time transfer or synchronization procedures (S7B).

10. The method of claim 9, wherein: The first data and the second data include a first random token and a second random token, the random tokens being reselected each time the second node is restarted, and wherein evaluating whether it is possible to adjust the local clock of the first node based on the second synchronization pulse and the second data (S65) includes: comparing the first random token with the second random token (S651); and Under the condition that the first random token and the second random token are the same, determining that it is possible to adjust the local clock of the first node based on the second synchronization pulse and the second data (S652A); or Under the condition that the first random token and the second random token are different, it is determined that it is impossible to adjust the local clock of the first node based on the second synchronization pulse and the second data (S652B).

11. The method according to claims 2 to 10, wherein: The oscillator signals received in the first node and the second node respectively are from the same frequency oscillator or from different frequency oscillators.

12. A system (100) for enabling time recovery of a local clock (15) in a first node (10) after a service interruption in the first node, the system comprising: A first node (10) comprising a local clock (15), a communication interface (11), and a processing circuit (12); a second node (20) comprising a local clock (25), a communication interface (21), and a processing circuit (22); one or more frequency oscillators (115), each of the one or more oscillators (115) being connected to one or both of the first node (10) and the second node (20), and Memory (35); The system is configured to perform the method according to any one of claims 1 to 11.

13. The method of claims 1 to 121 or the system of claim 12, wherein: The service interruption is caused by a reset, restart, or reboot of the first node.

14. The method of claims 1 to 11 or the system of claim 11, wherein: The first node includes a field programmable gate array (FPGA).

15. The method or system of claim 14, wherein: The first node includes a primary FPGA, and the second node includes a secondary FPGA.

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