Interposer for thermal engineering electro-optical multi-chip module

Abstract

The invention relates to an interposer for thermal engineering electro-optical multi-chip modules. A multi-chip module includes, from its bottom to top, a substrate and an interposer disposed on the substrate. The interposer is non-conductive and has klt; and a thermal conductivity (k) of 20 W / (mK). An integrated circuit component or chip set is disposed on the interposer. Each of a first subset of the component or chip set includes a passive heat spreader disposed on the chip. At least one chip of a second subset of the components or chips includes an active heat spreader disposed on the chip. The first and second sets of the components or chips are free of common components or chips. A common thermal interface is disposed on each passive heat sink and each active heat sink.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to U.S. Provisional Patent Application No. 63 / 556,589, filed on February 22, 2024, the disclosure of which is hereby incorporated by reference in its entirety. Technical Field

[0003] The present disclosure relates to multi-chip modules (MCMs), and more particularly, to thermal management of integrated circuit (IC) chips and / or components of such MCMs. Background Art

[0004] Next-generation optical interfaces for coherent optical signal transmission require denser packaging than before. A new generation of MCMs may include, among other things, one or more IC chips and one or more electro-optical (EO) components and / or chips on a common substrate. This is driven in part by the need for short, high-speed / high-frequency electrical connections between the IC chips and the EO components and / or chips.

[0005] In new generation MCMs, connections from the IC chip and EO components and / or chips to one or more peripheral devices are routed through the substrate to its bottom side, which provides a suitable electrical interface to a main printed circuit board (PCB), which can support or provide connections to one or more peripheral input / output (I / O) devices.

[0006] A unique requirement of some EO components and / or chips is that they require a specific operating temperature. This unique requirement does not exist in IC chips.

[0007] To efficiently achieve a specific operating temperature, the EO components and / or chips need to be thermally isolated from the (typically high-power-dissipating) IC chip. Because heat flows upward through the IC chip and EO components and / or chips within the MCM, a common heat sink can be placed on the top side of the IC chip and EO components and / or chips, with a substrate positioned beneath the electronics and EO chips. However, this substrate can cause undesirable thermal crosstalk. Summary of the Invention

[0008] Disclosed herein is the use of a non-conductive interposer with low thermal conductivity, disposed between a chip on the interposer and a substrate. The interposer will also include electrical conductors for carrying signals (e.g., high-speed signals) between the chips. The interposer can be made of any suitable and / or desired low thermal conductivity material (e.g., but not limited to, glass or fused silica), thereby combining low thermal conductivity with good RF properties. Herein, the good RF properties of the interposer can include the interposer being formed of a material that allows for the formation of RF waveguides / lines with a bandwidth of ≥70 GHz on or in the interposer.

[0009] Also disclosed herein is a multi-chip module comprising, from bottom to top, a substrate; an interposer disposed on the substrate, wherein the interposer is non-conductive and has a thermal conductivity (k) of k<20 W / (mK), wherein W=watt, m=meter, and K=Kelvin; a collection of integrated circuit components or chips disposed on the interposer, wherein each of a first subset of the collection of components or chips includes a passive heat sink disposed on the chip, and at least one chip in a second subset of the collection of components or chips includes an active heat sink disposed on the chip, wherein the first and second collections of components or chips have no common components or chips; and a common thermal interface disposed on each passive heat sink and each active heat sink. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 is a side schematic diagram of a multi-chip module according to the principles of the present disclosure;

[0011] Figure 2 It is along Figure 1 The line II-II in the Figure 1 a schematic cross-section of a multi-chip module; and

[0012] Figure 3 is a side schematic diagram of another multi-chip module according to the principles of the present disclosure. DETAILED DESCRIPTION

[0013] Various non-limiting embodiments will now be described with reference to the drawings, wherein like reference numerals correspond to similar or functionally equivalent elements or features.

[0014] As used herein, spatial or directional terms such as "left," "right," "inside," "outside," "above," "below," "top side," "bottom side," etc., refer to the disclosure as shown in the accompanying drawings. However, it is to be understood that the disclosure can take various alternative orientations and, therefore, such terms are not to be considered limiting. Furthermore, as used herein, all numbers expressing dimensions, physical properties, processing parameters, amounts of ingredients, reaction conditions, etc. used in the specification and claims are to be understood as being modified in all instances by the term "substantially" or "about." Therefore, unless indicated to the contrary, the numerical values ​​set forth in the following specification and claims may vary depending on the desired properties sought to be obtained by the present disclosure.

[0015] At least, it is not an attempt to limit the application of the doctrine of equivalents to the scope of the claims, and each numerical value should at least be interpreted in light of the number of reported significant figures and by applying conventional rounding techniques. In addition, all ranges disclosed herein are to be understood to encompass starting range values ​​and ending range values ​​and any and all subranges contained therein. For example, a stated range of "1 to 10" should be considered to include any and all subranges (and including the end values) between a minimum of 1 and a maximum of 10; that is, all subranges starting from a minimum of 1 or greater and ending at a maximum of 10 or less, for example, 1 to 3.3, 4.7 to 7.5, 5.5 to 10, etc. "One" or "an" refers to one or more.

[0016] As used herein, "coupled," "coupled," "disposed," "mounted," and similar terms refer to two or more elements that are joined, linked, fastened, connected, communicated, or otherwise associated (e.g., mechanically, electromagnetically, fluidically, optically) with one another. In various examples, these elements can be associated directly or indirectly. For example, element A can be directly associated with element B. As another example, element A can be indirectly associated with element B, for example, via another element C. It should be understood that not all associations between the various elements disclosed are necessarily present. Therefore, couplings other than those depicted in the figures may also exist.

[0017] As used herein, the phrase "at least one of" when used with a list of items means that various combinations of one or more of the listed items may be used, and only one of each item in the list may be required. For example, "at least one of item A, item B, and item C" may include, without limitation, item A or item A and item B. This example may also include item A, item B, and item C, or item B and item C. In other examples, "at least one of" may include, for example, without limitation, two items A, one item B, and ten items C; four items B and seven items C; and other suitable combinations.

[0018] refer to Figure 1 , an example multi-chip module according to the principles of the present disclosure can include, from bottom to top, a substrate 4 mounted on a main printed circuit board (PCB) 2. An interposer 6 can be disposed on substrate 4. In an example, interposer 6 can be non-conductive and can have a thermal conductivity (k) of k<20 W / (mK), where: W=watt, m=meter, and K=Kelvin. However, other values ​​of k are contemplated. In an example, an interposer 6 having a resistance of ≥1E10 ohms can be considered non-conductive.

[0019] An integrated circuit (IC) component or chip set may be disposed on interposer 6. In an example, the IC component or chip set may include chips 1 to 3. In a non-limiting example, chip 1 8-1 may be a digital signal processor (DSP) chip, chip 2 8-2 may be a driver chip, and chip 3 8-3 may be a modulator component or chip. However, this is not to be construed in a limiting sense, as it is contemplated that each chip 1 to 3 may be any suitable and / or desired chip for a particular application. Herein, when referring to chip 3, the terms "chip" and "component" may be used interchangeably.

[0020] In an example, chip 1 8-1 and chip 2 8-2 may include integrated circuit chips, such as CMOS chips, GaAs chips, SiGe chips, InP chips, or some combination thereof. In an example, chip 2 8-2 may be an analog mixed signal chip, such as an RF chip. In an example, chip 3 8-3 may include an EO component or chip, including, for example, without limitation, one or more of the following: a laser, a waveguide, a modulator, an optical amplifier, and / or one or more photodiodes, which may require a specific operating temperature or maximum operating temperature not present in electronic chips.

[0021] refer to Figure 2 And continue to refer to Figure 1 In an example, Chip 1 and Chip 2 can be spaced apart from each other by spacers 16-1 on interposer 6, which can include conductive traces 18-1 on or adjacent its top surface configured to communicatively connect Chip 1 and Chip 2 in a manner known in the art. In an example, Chip 2 and Chip 3 can be spaced apart from each other by spacers 16-2 on interposer 6, which can include conductive traces 18-2 on or adjacent its top surface configured to communicatively connect Chip 2 and Chip 3 in a manner known in the art. In an example, conductive traces 18-1 and 18-2 can be disposed on the top surface of interposer 6 and / or in one or more so-called redistribution layers disposed below the top surface of interposer 6.

[0022] The interposer 6 can be made of any suitable and / or desired low thermal conductivity material (for example, but not limited to, glass or fused silica), thereby combining low thermal conductivity with good RF properties. Herein, the good RF properties of the interposer 6 can include the interposer 6 being formed of a material that allows one or more of the conductive traces 18-1 and / or 18-2 to be formed, wherein the conductive traces 18-1 and / or 18-2 have properties of an RF waveguide / line with a bandwidth ≥ 70 GHz on or in the interposer 6.

[0023] Interposer 6 and substrate 4 may include, for example, vertical conductive vias and (optionally) horizontal conductive traces (in addition to conductive traces 18-1 and 18-2) on a top surface of PCB 2 and / or in one or more redistribution layers of PCB 2 below the top surface of PCB 2, the vertical conductive vias and horizontal conductive traces configured to electrically connect conductors including conductive traces 18-1 and 18-2 of interposer 6 to conductors including conductive traces of PCB 2. In an example, the vertical conductive vias and (optionally) horizontal conductive traces may be configured to communicatively connect at least chip 18-1, for example, to external components and / or chips (not shown) via PCB 2. In an example, the conductive vias and optional conductive traces of interposer 6 and substrate 4 may be used for bidirectional communication between external components and / or chips and at least chip 18-1.

[0024] In an example, the conductive vias and optional conductive traces of the interposer 6 and substrate 4 may provide low-speed communication connections (via Figure 1 1 and 8-2, and between chip 2 8-2 and chip 3 8-3. Figure 1 ), for example >10 Gbps and preferably >100 Gbps. However, this is not to be construed in a limiting sense.

[0025] In an example, the conductive vias and (optionally) conductive traces of interposer 6 and substrate 4 may also provide electrical paths for providing electrical bias from one or more external power supplies (not shown) to chips 1 to 3 and thermal management portion 12 (discussed in more detail below) via PCB 2.

[0026] In an example, chip 1 8-1 to chip 3 8-3 can be mechanically and electrically coupled to an interposer 6, which in turn can be mechanically and electrically coupled to a substrate 4, which in turn can be mechanically and electrically coupled to a PCB 2 using any suitable and / or desired surface mounting technology known in the art (e.g., ball grid array technology).

[0027] In an example, at least one of chip 1 8-1 and / or chip 2 8-2 (preferably both) may include a heat sink 10-1 and / or 10-2 disposed thereon. In an example, each heat sink 10 may be a passive heat sink, such as one or more of: a metal (e.g., copper or aluminum) plate; a ceramic plate; a compound semiconductor (e.g., SiC) layer; a diamond layer; a thermal interface tape or paste; a vapor chamber; a graphite or graphene sheet; and / or a heat pipe. In an example, chip 3 8-3 may include a thermal management portion 12 disposed thereon. In an example, thermal management portion 12 may include an active component (such as a heater or a thermo-electric cooler) that is operable and / or configured to maintain chip 3 8-3 at or below a desired operating temperature during use.

[0028] Finally, the multi-chip module may include a common thermal interface 14 disposed on top of the heat spreaders 10-1 and 10-2, the thermal management portion 12, and over the spaces 16-1 and 16-2 therebetween. Figure 1 , the top of the thermal-management portion 12 will be the so-called "hot side" that will contact the portion of the bottom of the common thermal interface 14 that is aligned with the thermal-management portion 12. In examples, the common thermal interface can be a passive heat sink, such as one or more of: a metal (e.g., copper or aluminum) plate; a ceramic plate; a compound semiconductor (e.g., SiC) layer; a diamond layer; a thermal interface tape or paste; a vapor chamber; a graphite or graphene sheet; and / or a heat pipe.

[0029] Continue to refer Figure 2 In an example, the interposer 6 may include one or more cavities 20 to reduce the thermal conductivity between the chip 3 and the chips 1 and / or 2. In an example, the one or more cavities 20 may include cavities disposed between the conductor 18-2 and the bottom and top edges of the interposer 6 (at Figure 2 In the orientation shown in FIG) between the cavities 20-1 and 20-2. Figure 2 In the example shown in FIG, the cavity 20-1 may not extend to the bottom edge of the interposer 6 (in Figure 2 ) (spaced from the bottom edge), while cavity 20-2 may extend to the top edge of interposer 6 (at Figure 2 ). However, this is not to be construed in a limiting sense, as it is contemplated that each cavity 20 may be spaced from or extend to a corresponding edge of the interposer 6, as may be deemed appropriate and / or desired for a particular application. Furthermore, each cavity 20 may extend partially or completely through the thickness of the interposer 6, as may be deemed appropriate and / or desired for a particular application.

[0030] Continue to refer Figure 1In the example, it is envisaged that the functionality of chip 1 8-1 and chip 2 8-2 may be combined into, for example, a single chip 8, whereby Figure 1 In the embodiment, the chips and their heat sinks 10 combined into a single chip 8 may be omitted; the common thermal interface 14 may be sized to contact the remaining heat sink 10 and the top of the thermal management portion 12 (perhaps with some extension of the common thermal interface 14 beyond the remaining heat sink 10 and / or the top of the thermal management portion 12); and, if desired, a low-speed communication connection (by Figure 1 ) can be repositioned to extend between the single chip 28 and the PCB 2.

[0031] refer to Figure 3 Another example of a multi-chip module according to the principles of the present disclosure may be similar to Figure 1 The example multi-chip module shown in FIG. 1 has at least the following differences: chip 1 8-1 can be mounted directly on substrate 4; chip 2 8-2 and chip 3 8-3 can be mounted on interposer 6, with heat sink 10-2 and thermal management portion 12 provided between chip 2 8-2 and chip 3 8-3 and common thermal interface 14; low-speed communication connection (by Figure 3 A high-speed communication connection or conductive trace (shown by arrow A in FIG) may extend through the substrate 4 between the chip 18-1 and the PCB 2; Figure 3 8-2), may extend laterally between the bottom of the interposer 6 below the chip 1 8-1 and the chip 2 8-2, vertically through the interposer 6 between the substrate 4 and the chip 2 8-2, and laterally between the chip 2 8-2 and the chip 3 8-3.

[0032] In an example, the heat spreader 10-1 (shown in phantom) may or may not be disposed on top of the chip 18-1. In the event that the heat spreader 10-1 (shown in phantom) is not disposed on top of the chip 18-1, the common thermal interface 14 may be sized so that it contacts the top of the heat spreader 10-2 and the thermal-management portion 12 (perhaps with some portion of the common thermal interface 14 extending beyond the top of the heat spreader 10-2 and / or the thermal-management portion 12).

[0033] In the case where the heat sink 10-1 (shown in dotted lines) is indeed disposed on top of the chip 18-1, in one example, the height of the heat sink 10-1 can be selected so that the tops of the heat sinks 10-1 and 10-2 and the top of the thermal management portion 12 can all be located at or near the same plane P, and the common thermal interface 14 can include an additional section 14 (shown in dotted lines) that contacts the top of the heat sink 10-1 (in addition to the tops of the heat sink 10-2 and the thermal management portion 12 that contact the common thermal interface 14).

[0034] The heat sink 10-1 (shown in dotted lines) is placed on top of the chip 18-1, and the top of the heat sink 10-1 (shown in dotted lines) Figure 3 In the case where the heat sink 10-2 and the top of the thermal management portion 12 are arranged below the level of the top of the heat sink 10-2 and the top of the thermal management portion 12 (i.e., the top of the heat sink 10-1 is arranged below the level of the plane P), the additional section of the common thermal interface 14 (shown in dotted lines) can be omitted, whereby only the top of the heat sink 1-2 and the thermal management portion 12 are in contact with the common thermal interface 14.

[0035] Other non-limiting examples or aspects of the present disclosure are set forth in the following illustrative and exemplary numbered clauses.

[0036] Item 1: A multi-chip module comprising, from bottom to top: a substrate; an interposer disposed on the substrate, wherein the interposer is non-conductive and has a thermal conductivity (k) of k<20 W(mK), where W=watts, m=meters, and K=kelvin; a collection of integrated circuit components or chips disposed on the interposer, wherein each of a first subset of the collection of components or chips includes a passive heat sink disposed on the chip; and each of a second subset of the components or chips includes an active heat sink disposed on the chip, wherein the first and second collections of components or chips have no components or chips in common; and a common thermal interface disposed on each passive heat sink and each active heat sink.

[0037] Clause 2: The multi-integrated circuit chip module of Clause 1 may further include a set of conductors electrically connecting the chip sets.

[0038] Clause 3: The multi-integrated circuit chip module of clause 1 or 2, wherein the conductor assembly is disposed on an interposer between the interposer and the chip assembly.

[0039] Clause 4: The multi-integrated circuit chip module of any of clauses 1 to 3, wherein the interposer comprises glass.

[0040] Clause 5: The multi-integrated circuit chip module of any of clauses 1 to 4, wherein the interposer comprises fused silica.

[0041] Clause 6: The multi-integrated circuit chip module of any of clauses 1 to 5, wherein the interposer may include one or more cavities configured to reduce thermal conductivity of the interposer between at least two chips in the chipset.

[0042] Clause 7: The multi-integrated circuit chip module of any one of clauses 1 to 6, further comprising a set of conductors disposed through the interposer to electrically connect the substrate to at least one chip in the chipset.

[0043] Clause 8: The multi-integrated circuit chip module of any of clauses 1 to 7, further comprising a set of conductors disposed through the substrate and electrically connected to the set of conductors disposed through the interposer.

[0044] Item 9: A multi-integrated circuit chip module according to any one of items 1 to 8, wherein the conductor set can be configured to pass through the substrate, and the conductor set configured to pass through the interposer can be configured to route one or more electrical signals conducted from an external source into or out of the substrate into or out of at least one chip in the chip set.

[0045] Clause 10: The multi-integrated circuit chip module of any one of clauses 1 to 9, wherein the active heat sink may comprise a heater or a thermo-electric cooler.

[0046] Clause 11: A multi-integrated circuit chip module according to any one of clauses 1 to 10, wherein the common thermal interface may include at least one of the following: a metal plate; a ceramic plate; a germanium plate, a compound semiconductor layer; a diamond layer; a thermal interface tape or paste; a vapor chamber; a graphite or graphene sheet; and / or a heat pipe.

[0047] Clause 12: A multi-integrated circuit chip module according to any one of clauses 1 to 11, wherein each passive heat sink may include at least one of the following: a metal plate; a ceramic plate; a germanium plate, a compound semiconductor layer; a diamond layer; a thermal interface tape or paste; a vapor chamber; a graphite or graphene sheet; and / or a heat pipe.

[0048] Clause 13: The multi-integrated circuit chip module of any of clauses 1 to 12, wherein the first subset of the set of components or chips can include a single component or chip.

[0049] Clause 14: The multi-integrated circuit chip module of any of clauses 1 to 13, wherein the second subset of the set of components or chips can include a single component or chip.

[0050] Clause 15: The multi-integrated circuit chip module according to any one of clauses 1 to 14, further comprising a component or chip disposed on a substrate.

[0051] Clause 16: The multi-integrated circuit chip module of any one of clauses 1 to 15, further comprising a passive heat sink coupled to the component or chip disposed on the substrate.

[0052] Clause 17: The multi-integrated circuit chip module of any one of clauses 1 to 16, wherein a passive heat sink coupled to a component or chip disposed on the substrate can be spaced apart from the common thermal interface.

[0053] Clause 18: The multi-integrated circuit chip module of any one of clauses 1 to 17, wherein a passive heat sink coupled to the components or chips disposed on the substrate may also be coupled to the common thermal interface.

[0054] Although the present disclosure has been described in detail for purposes of illustration based on what are presently considered to be the most practical and preferred embodiments, it is to be understood that such description is for that purpose only and that the present disclosure is not limited to the disclosed embodiments, but, on the contrary, is intended to cover modifications and equivalent arrangements within the spirit and scope of the appended claims. For example, it is to be understood that the present disclosure contemplates that, to the extent possible, one or more features of any embodiment or example can be combined with one or more features of any other embodiment or example.

Claims

1. A multi-chip module comprising, from bottom to top: substrate; an interposer disposed on the substrate, wherein the interposer is non-conductive and has a thermal conductivity k of k<20 W / (mK), where W=watt, m=meter, and K=Kelvin; An integrated circuit component or chip set is disposed on the interposer, wherein: Each of the first subset of components or chips comprises a passive heat sink disposed on the chip; and each of the second subset of components or chips includes an active heat sink disposed on the chip, wherein the first set and the second set of components or chips have no components or chips in common; and A common thermal interface is provided on each passive heat sink and each active heat sink.

2. The multi-IC chip module of claim 1, further comprising a conductor set electrically connecting the chip sets.

3. The multi-integrated circuit chip module according to claim 2, wherein: The conductor set is disposed on the interposer and is located between the interposer and the chip set.

4. The multi-integrated circuit chip module according to claim 1, wherein: The interposer includes glass.

5. The multi-integrated circuit chip module according to claim 1, wherein: The intervening layer includes fused silica.

6. The multi-integrated circuit chip module according to claim 1, wherein: The interposer includes one or more cavities configured to reduce thermal conductivity of the interposer between at least two chips in the chip set.

7. The multi-integrated circuit chip module of claim 1, further comprising a set of conductors disposed through the interposer to electrically connect the substrate to at least one chip in the chip set.

8. The multi-integrated circuit chip module of claim 7, further comprising a set of conductors disposed through the substrate and electrically connected to the set of conductors disposed through the interposer.

9. The multi-integrated circuit chip module according to claim 8, wherein: The set of conductors disposed through the substrate and the set of conductors disposed through the interposer are configured to route one or more electrical signals conducted into or out of the substrate from an external source into or out of at least one chip in the chip set.

10. The multi-integrated circuit chip module according to claim 1, wherein: The active heat sink includes a heater or a thermo-electric cooler.

11. The multi-integrated circuit chip module according to claim 1, wherein: The common thermal interface comprises at least one of: a metal plate; a ceramic plate; a germanium plate, a compound semiconductor layer; a diamond layer; a thermal interface tape or paste; a vapor chamber; a graphite or graphene sheet; and / or a heat pipe.

12. The multi-integrated circuit chip module according to claim 1, wherein: Each passive heat sink includes at least one of: a metal plate; a ceramic plate; a germanium plate, a compound semiconductor layer; a diamond layer; a thermal interface tape or paste; a vapor chamber; a graphite or graphene sheet; and / or a heat pipe.

13. The multi-integrated circuit chip module according to claim 1, wherein: The first subset of the set of components or chips includes a single component or chip.

14. The multi-integrated circuit chip module according to claim 1, wherein: The second subset of the set of components or chips includes a single component or chip.

15. The multi-integrated circuit chip module of claim 1, further comprising components or chips disposed on the substrate. 16 . The multi-integrated circuit chip module of claim 15 , further comprising a passive heat sink coupled to the components or chips disposed on the substrate.

17. The multi-integrated circuit chip module according to claim 16, wherein: The passive heat sink coupled to the component or chip disposed on the substrate is spaced apart from the common thermal interface.

18. The multi-integrated circuit chip module according to claim 16, wherein: The passive heat sink coupled to the component or chip disposed on the substrate is also coupled to the common thermal interface.

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