Pulse generation method for pulse ablation

Abstract

The invention discloses a pulse generation method for pulse ablation, which relates to the technical field of medical equipment, and comprises the following steps: when a unipolar pulse is generated, closing MOS (Metal Oxide Semiconductor) tubes Q1, Q3 and Q4, conducting an MOS tube Q2, and pre-charging a bootstrap capacitor C1 through a driving chip P1; after pre-charging is completed, triggering signals are input to corresponding pins of the driving chips P1 and P2, and unipolar pulses are generated at the two ends of the load RL; when a bipolar pulse is generated, the MOS tubes Q1 and Q3 are closed, the MOS tubes Q2 and Q4 are conducted, and the bootstrap capacitors C1 and C2 are pre-charged through the driving chips P1 and P2 respectively; after pre-charging is completed, trigger signals are input to corresponding pins of the driving chips P1 and P2, and positive polarity pulses are generated at the two ends of the load RL. According to the invention, a bootstrap gate drive circuit and a pre-charging management strategy are combined, and miniaturized, low-power-consumption and high-precision unipolar / bipolar pulse output is realized.

Description

Technical Field

[0001] The present invention relates to the technical field of medical equipment, and in particular to a pulse generating method for pulse ablation. Background Art

[0002] Pulsed field ablation (PFA) refers to the application of intermittent high-intensity pulsed electric fields for a very short period of time, causing irreversible injury (IRE) by electroporation of the cell membrane. Tumor pulse ablation technology is widely used in the treatment of various cancers due to its minimally invasive, non-thermal and selective advantages. Existing clinical studies have achieved precise interventional treatment of digestive tract tumors such as esophageal cancer and gastric cancer by integrating IRE technology with endoscopic catheters. However, traditional pulse ablation devices need to apply pulse voltages of up to several thousand volts to induce tetanic muscle contraction, resulting in the treatment process relying on general anesthesia and electrocardiogram synchronization, which is expensive. At the same time, the "missed ablation" phenomenon caused by uneven electric field distribution often requires 3-5 repeated treatments, and each treatment requires repeated endoscopic intervention and anesthesia operations, which increases the physical and mental burden on patients. Therefore, it is necessary to implant the pulse ablation device into the body.

[0003] Existing pulse sources specifically used for pulse ablation are all high-voltage pulse sources of several thousand volts. They are bulky and consume a lot of power, making them completely unsuitable for implantation. Therefore, there is an urgent need for an implantable pulse source that meets the following five conditions:

[0004] (1) Miniaturization: The maximum outer diameter of the device is ≤11 mm (the lower limit of the working channel diameter of the gastroscope) to adapt to the endoscopic delivery path.

[0005] (2) Basic requirements for voltage amplitude: The field strength can be increased by reducing the electrode spacing, thereby reducing the voltage required for ablation. However, for contact electrodes, the smaller the electrode spacing, the shallower the ablation depth, and a trade-off between voltage level and ablation effect is necessary. Existing literature has achieved good ablation effects at a voltage of 100V, so the pulse source needs to meet the basic requirements for voltage amplitude (greater than 100V).

[0006] (3) Single and bipolar: Bipolar pulses can cause the action potential to rise after one pulse, but this rise is reduced by the subsequent negative pulse, resulting in a slow rise in the action potential. Therefore, high-frequency bipolar microsecond pulses effectively alleviate the muscle contraction problem in traditional IRE treatment, but their ablation effect is not as good as that of unipolar pulses. Therefore, the pulse generator needs to integrate a unipolar / bipolar switchable output function and dynamically adjust the output mode according to the lesion location and patient tolerance.

[0007] (4) Low power consumption: Due to limited energy supply, implantable devices need to adopt low power consumption design to extend continuous working time.

[0008] (5) Wide-range adjustability: Individual differences require flexible adaptation of pulse parameters.

[0009] At present, the most suitable technical solution for implantable application scenarios is mainly H-bridge + bootstrap boost circuit, such as Figure 1 As shown in Figure 1, this solution utilizes the simple structure and small size of the H-bridge circuit, combined with bootstrap boost technology to replace the traditional isolated power supply to drive the high-end switch tubes (Q1, Q3). The gate drive voltage is raised through the bootstrap capacitors (C1, C2), thus avoiding the use of a bulky isolation transformer. However, this solution is currently used in the scenario of driving a generator, and in unipolar pulse mode (such as triggering only Q1 / Q4 to turn on), the storage voltage of the bootstrap capacitor C1 can only maintain 3.3V, which is unable to drive Q1 to fully turn on. Figure 2 The measured voltage at the final load end is only 4V (far lower than the design value of 200V), which cannot form an effective ablation electric field. Before the bipolar pulse is output, the bootstrap capacitor must be pre-charged through the initial pulse, resulting in the first few trigger signals being unable to generate effective pulses. Figure 3 This pre-charging process causes the actual number of output pulses to deviate from the theoretical trigger number, which cannot meet the clinical treatment requirements for precise control of pulse dose.

[0010] In summary, the existing H-bridge + bootstrap boost circuit solution, when used as an implantable pulse source, cannot generate unipolar pulses that meet the design value, and the number of bipolar pulses cannot be controlled. Summary of the Invention

[0011] Based on the defects of the above-mentioned prior art, the present invention provides a pulse generation method for pulse ablation, which solves the problem that the existing H-bridge + bootstrap boost circuit solution cannot generate unipolar pulses that meet the design values ​​when used as an implantable pulse source, and the number of bipolar pulses cannot be controlled.

[0012] The present invention adopts the following technical solutions:

[0013] The present invention provides a pulse generation method for pulse ablation, wherein the composite pulse is generated by a pulse source composed of an H-bridge circuit and a bootstrap gate drive circuit, wherein the H-bridge circuit includes MOS tubes Q1, Q2, Q3 and Q4 and a load R L The bootstrap gate drive circuit includes drive chips P1 and P2, diodes D1 and D2, bootstrap capacitors C1 and C2, and drive resistors R1, R2, R3, and R4 symmetrically arranged on both sides of the H-bridge circuit; the pulse is generated by a pulse source composed of an H-bridge circuit and a bootstrap gate drive circuit, wherein the H-bridge circuit includes MOS tubes Q1, Q2, Q3, and Q4 and a load R LThe bootstrap gate drive circuit includes driver chips P1 and P2, diodes D1 and D2, bootstrap capacitors C1 and C2, and drive resistors R1, R2, R3, and R4 symmetrically arranged on both sides of the H-bridge circuit; characterized in that it includes the following steps:

[0014] When a unipolar pulse is generated, MOS tubes Q1, Q3 and Q4 are turned off, MOS tube Q2 is turned on, and the bootstrap capacitor C1 is pre-charged through the driver chip P1;

[0015] After the pre-charging is completed, the MOS tubes Q1 and Q4 are turned on, the MOS tubes Q2 and Q3 are turned off, and the trigger signal is input to the corresponding pins of the driver chips P1 and P2. L Unipolar pulses are generated at both ends;

[0016] When a bipolar pulse is generated, MOS tubes Q1 and Q3 are turned off, and MOS tubes Q2 and Q4 are turned on, and the bootstrap capacitors C1 and C2 are pre-charged respectively through the driver chips P1 and P2;

[0017] After the pre-charging is completed, the MOS tubes Q1 and Q4 are turned on, the MOS tubes Q2 and Q3 are turned off, and the trigger signal is input to the corresponding pins of the driver chips P1 and P2. L Positive polarity pulses are generated at both ends;

[0018] Set the dead time to turn off MOS tubes Q1 and Q4 during the dead time;

[0019] After the dead time ends, MOS tubes Q2 and Q3 are turned on, and trigger signals are input to the corresponding pins of driver chips P1 and P2, generating negative polarity pulses at both ends of the load.

[0020] Preferably, the drains of the MOS transistors Q1 and Q3 are connected to a DC power supply, the gates are connected to one end of the driving resistors R1 and R3 respectively, and the sources are connected to the drains of the MOS transistors Q2 and Q4; the sources of the MOS transistors Q2 and Q4 are grounded; the load R L The two ends are respectively connected to the drains of the MOS tubes Q2 and Q4 and the sources of the MOS tubes Q1 and Q3.

[0021] Preferably, the driver chips P1 and P2 have the same structure and both include a first pin, a second pin, a third pin, a fourth pin, a fifth pin, a sixth pin, a seventh pin and an eighth pin, wherein the first pin is a high-side drive input interface, the second pin is a low-side drive input interface, the third pin is a low-side drive output interface, the fourth pin is a bootstrapped high-end VB power supply, the fifth pin is a high-side drive output interface, the sixth pin is a high-end floating ground terminal, the seventh pin is a chip power supply, and the eighth pin is grounded.

[0022] Preferably, the third pin of the driver chip P1 is connected to one end of the driving resistor R2, the fourth pin is connected to the cathode of the diode D1 and one end of the bootstrap capacitor C1, the fifth pin is connected to one end of the driving resistor R1, and the sixth pin is connected to the other end of the bootstrap capacitor C1 and the load R L The other end of the driving resistor R1 is connected to the gate of the MOS tube Q1, and the other end of the driving resistor R2 is connected to the gate of the MOS tube Q2.

[0023] Preferably, the pre-charging of the bootstrap capacitor C1 by the driver chip P1 includes the following steps:

[0024] Input a trigger signal to the second pin of the driver chip P1;

[0025] The bootstrap capacitor C1 is precharged by the chip power supply.

[0026] Preferably, during the generation of the unipolar pulse, a trigger signal is input to corresponding pins of the driver chips P1 and P2, wherein the corresponding pins include a first pin of the driver chip P1 and a second pin of P2.

[0027] Preferably, the pre-charging of the bootstrap capacitors C1 and C2 by the driving chips P1 and P2 respectively includes the following steps:

[0028] Input trigger signals to the second pins of the driver chips P1 and P2;

[0029] The bootstrap capacitor C1 is precharged by two chip power supplies.

[0030] Preferably, during the generation of the positive polarity pulse, a trigger signal is input to the corresponding pins of the driver chips P1 and P2, wherein the corresponding pins include the first pin of the driver chip P1 and the second pin of P2; during the generation of the negative polarity pulse, a trigger signal is input to the corresponding pins of the driver chips P1 and P2, wherein the corresponding pins include the second pin of the driver chip P1 and the first pin of P2.

[0031] Compared with the prior art, the at least one technical solution adopted by the present invention can achieve the following beneficial effects:

[0032] This invention adds a precharge strategy to the H-bridge + bootstrap boost circuit. This adds corresponding precharge steps to the generation of unipolar and bipolar pulses, ensuring that the unipolar pulses generated after precharge meet the design value while also controlling the number of bipolar pulses after precharge. This invention utilizes four power MOSFETs to construct a full-bridge topology, combining a bootstrap gate drive circuit with a precharge management strategy to achieve miniaturized, low-power, and high-precision unipolar and bipolar pulse output. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0034] Figure 1 It is the topological structure diagram of H bridge circuit;

[0035] Figure 2 Schematic diagram of unipolar pulse generated by existing H-bridge + bootstrap boost circuit;

[0036] Figure 3 Schematic diagram of bipolar pulses generated by the existing H-bridge + bootstrap boost circuit;

[0037] Figure 4 Schematic diagram of the principle of generating unipolar pulses in an H-bridge + bootstrap boost circuit using the method of the present invention;

[0038] in, Figure 4 (a): Schematic diagram of the pre-charging process of the bootstrap capacitor C1, Figure 4 (b): Schematic diagram of the unipolar pulse generation process;

[0039] Figure 5 Schematic diagram of the generation principle of bipolar pulses in an H-bridge + bootstrap boost circuit using the method of the present invention;

[0040] in, Figure 5 (a): Schematic diagram of the pre-charging process of bootstrap capacitors C1 and C2, Figure 5 (b): Schematic diagram of the positive polarity pulse generation process; Figure 5 (c): Schematic diagram of the negative polarity pulse generation process;

[0041] Figure 6 Schematic diagram of a unipolar pulse waveform of the present invention;

[0042] in, Figure 6 (a): Schematic diagram of pulse waveforms with different amplitudes, Figure 6 (b): Schematic diagram of 500ns pulse waveform, Figure 6 (c): 1000ns pulse waveform diagram, Figure 6 (d): Schematic diagram of 100kHz pulse waveform;

[0043] Figure 7 Schematic diagram of a bipolar pulse waveform of the present invention;

[0044] in, Figure 7 (a): Bipolar string 1Hz waveform diagram, Figure 7 (b): Schematic diagram of the waveform within the bipolar string. DETAILED DESCRIPTION

[0045] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of the present invention.

[0046] Reference Figure 1 The pulse forming module uses four groups of power MOSFETs to build a full-bridge topology, combined with a bootstrap gate drive circuit and a pre-charge management strategy to achieve miniaturization, low power consumption, and high-precision single / bipolar pulse output.

[0047] The composite pulse is generated by a pulse source composed of an H-bridge circuit and a bootstrap gate drive circuit. The H-bridge circuit includes MOS tubes Q1, Q2, Q3 and Q4 and a load R L The bootstrap gate drive circuit includes drive chips P1 and P2, diodes D1 and D2, bootstrap capacitors C1 and C2, and drive resistors R1, R2, R3, and R4, which are symmetrically arranged on both sides of the H-bridge circuit.

[0048] The drains of MOS tubes Q1 and Q3 are connected to the DC power supply, the gates are connected to one end of the driving resistors R1 and R3 respectively, and the sources are connected to the drains of MOS tubes Q2 and Q4; the sources of MOS tubes Q2 and Q4 are grounded; the load R L The two ends are respectively connected to the drains of the MOS tubes Q2 and Q4 and the sources of the MOS tubes Q1 and Q3.

[0049] The driver chips P1 and P2 have the same structure and both include a first pin, a second pin, a third pin, a fourth pin, a fifth pin, a sixth pin, a seventh pin and an eighth pin. Among them, the first pin is the high-side drive input interface, the second pin is the low-side drive input interface, the third pin is the low-side drive output interface, the fourth pin is the bootstrapped high-end VB power supply, the fifth pin is the high-side drive output interface, the sixth pin is the high-end floating ground terminal, the seventh pin is the chip power supply, and the eighth pin is grounded.

[0050] The third pin of the driver chip P1 is connected to one end of the driving resistor R2, the fourth pin is connected to the cathode of the diode D1 and one end of the bootstrap capacitor C1, the fifth pin is connected to one end of the driving resistor R1, and the sixth pin is connected to the other end of the bootstrap capacitor C1 and the load R LThe other end of the driving resistor R1 is connected to the gate of the MOS tube Q1, and the other end of the driving resistor R2 is connected to the gate of the MOS tube Q2.

[0051] Reference Figure 4 , unipolar pulse generation mechanism:

[0052] 1) Pre-charge stage: Figure 4 As shown in (a), the lower bridge arm MOSFET Q2 is turned on and the chip power supply voltage V cc The freewheeling diode (D1) accumulates the charge on the bootstrap capacitor (C1), so that the voltage across C1 reaches (V cc -V f )(V f is the diode forward voltage drop);

[0053] 2) Positive pulse output stage: Figure 4 As shown in (b), the upper-arm MOSFET (Q1) and the lower-arm MOSFET (Q4) are triggered synchronously to form V dc →Q1→load→Q4→GND, generating a current path with an amplitude of +V at both ends of the load. dc At this time, the bootstrap capacitor C1 provides a driving potential higher than Vdc for the gate of Q1 to ensure that the power tube is fully turned on.

[0054] High-frequency bipolar microsecond pulse generation mechanism ( Figure 5 ):

[0055] 1) Pre-charge stage: Figure 5 As shown in (a), the lower bridge arm MOSFETs Q2 and Q4 are turned on, and V cc The bootstrap capacitors C1 and C2 are charged in parallel through D1 and D2 respectively.

[0056] 2) Positive polarity pulse stage: Figure 4 As shown in (b), the upper-arm MOSFET (Q1) and the lower-arm MOSFET (Q4) are triggered synchronously to form V dc →Q1→load→Q4→GND, generating a current path with an amplitude of +V at both ends of the load. dc At this time, the bootstrap capacitor C1 provides a driving potential higher than Vdc for the gate of Q1 to ensure that the power tube is fully turned on.

[0057] 3) Polarity switching transition period: All MOSFETs are turned off (dead time).

[0058] 4) Negative polarity pulse stage: Figure 5As shown in (c), the upper bridge arm MOSFET (Q3) and the lower bridge arm MOSFET (Q2) are triggered synchronously, forming a current path of Vdc→Q3→load→Q2→GND, generating a current with an amplitude of -V at both ends of the load. dc At this time, the bootstrap capacitor C2 provides a driving potential higher than Vdc for the gate of Q3 to ensure that the power tube is fully turned on.

[0059] Example

[0060] The key components are selected as follows: Power MOSFETQ1, Q2, Q3 and Q4 use DMN24H3D5L type N-channel enhancement MOSFET (VDSS = 250V, RDS(on) = 1.3Ω, tr = 4ns), which is a small SOT-23 package (size 1.6mm×2.9mm×1.3mm). The freewheeling diodes D1D2 use Schottky diodes, which have low forward voltage drop and very fast switching action. The bootstrap boost capacitor uses a 22μF multilayer ceramic capacitor to ensure the stability of the high-side drive voltage. The gate drive uses a high-speed dual-channel driver packaged as DFN10 (4mm×4mm×0.8mm). The overall size of the pulse source is compressed to 10mm×20mm×1.5mm (volume 0.3cm 3 ).

[0061] The unipolar pulses generated are as follows Figure 6 As shown, refer to Figure 6 (a), the amplitude is adjustable from 10V to 200V, refer to Figure 6 (b) and (c), the pulse width is adjustable from 500ns to 1000ns, refer to Figure 6 (d), the frequency can reach 100kHz.

[0062] The high-frequency bipolar microsecond pulses generated are as follows: Figure 7 As shown, the pulse amplitude is ±200V, the repetition frequency outside the pulse train is 1Hz, the dead time inside the train is 2us, the pulse width is 10us, and the number of pulses is 10.

[0063] Although the preferred embodiments of the present invention have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the present invention.

[0064] Obviously, those skilled in the art may make various modifications and variations to the present invention without departing from the spirit and scope of the present invention. Thus, if such modifications and variations fall within the scope of the claims and their equivalents, the present invention is intended to include such modifications and variations.

Claims

1. A pulse generation method for pulse ablation, wherein the pulse is generated by a pulse source composed of an H-bridge circuit and a bootstrap gate drive circuit, wherein: The H-bridge circuit includes MOS tubes Q1, Q2, Q3 and Q4 and a load R L The bootstrap gate drive circuit includes driver chips P1 and P2, diodes D1 and D2, bootstrap capacitors C1 and C2, and drive resistors R1, R2, R3, and R4 symmetrically arranged on both sides of the H-bridge circuit; characterized in that it includes the following steps: When a unipolar pulse is generated, MOS tubes Q1, Q3 and Q4 are turned off, MOS tube Q2 is turned on, and the bootstrap capacitor C1 is pre-charged through the driver chip P1; After the pre-charging is completed, the MOS tubes Q1 and Q4 are turned on, the MOS tubes Q2 and Q3 are turned off, and the trigger signal is input to the corresponding pins of the driver chips P1 and P2. L Unipolar pulses are generated at both ends; When a bipolar pulse is generated, MOS tubes Q1 and Q3 are turned off, and MOS tubes Q2 and Q4 are turned on, and the bootstrap capacitors C1 and C2 are pre-charged respectively through the driver chips P1 and P2; After the pre-charging is completed, the MOS tubes Q1 and Q4 are turned on, the MOS tubes Q2 and Q3 are turned off, and the trigger signal is input to the corresponding pins of the driver chips P1 and P2. L Positive polarity pulses are generated at both ends; Set the dead time to turn off MOS tubes Q1 and Q4 during the dead time; After the dead time ends, MOS tubes Q2 and Q3 are turned on, and trigger signals are input to the corresponding pins of driver chips P1 and P2, generating negative polarity pulses at both ends of the load.

2. A pulse generation method for pulse ablation according to claim 1, characterized in that: The drains of the MOS transistors Q1 and Q3 are connected to a DC power supply, the gates are connected to one end of the driving resistors R1 and R3 respectively, and the sources are connected to the drains of the MOS transistors Q2 and Q4; the sources of the MOS transistors Q2 and Q4 are grounded; the load R L The two ends are respectively connected to the drains of the MOS tubes Q2 and Q4 and the sources of the MOS tubes Q1 and Q3.

3. The pulse generating method for pulse ablation according to claim 2, wherein: The driver chips P1 and P2 have the same structure and both include a first pin, a second pin, a third pin, a fourth pin, a fifth pin, a sixth pin, a seventh pin and an eighth pin, wherein the first pin is a high-side drive input interface, the second pin is a low-side drive input interface, the third pin is a low-side drive output interface, the fourth pin is a bootstrapped high-end VB power supply, the fifth pin is a high-side drive output interface, the sixth pin is a high-end floating ground terminal, the seventh pin is a chip power supply, and the eighth pin is grounded.

4. A pulse generation method for pulse ablation according to claim 3, characterized in that: The third pin of the driver chip P1 is connected to one end of the driving resistor R2, the fourth pin is connected to the cathode of the diode D1 and one end of the bootstrap capacitor C1, the fifth pin is connected to one end of the driving resistor R1, and the sixth pin is connected to the other end of the bootstrap capacitor C1 and the load R L The other end of the driving resistor R1 is connected to the gate of the MOS tube Q1, and the other end of the driving resistor R2 is connected to the gate of the MOS tube Q2.

5. The pulse generating method for pulse ablation according to claim 4, characterized in that: The pre-charging of the bootstrap capacitor C1 by the driver chip P1 includes the following steps: Input a trigger signal to the second pin of the driver chip P1; The bootstrap capacitor C1 is precharged by the chip power supply.

6. The pulse generating method for pulse ablation according to claim 4, characterized in that: During the generation of the unipolar pulse, a trigger signal is input to corresponding pins of the driver chips P1 and P2 , wherein the corresponding pins include a first pin of the driver chip P1 and a second pin of P2 .

7. The pulse generating method for pulse ablation according to claim 4, characterized in that: The pre-charging of the bootstrap capacitors C1 and C2 by the driver chips P1 and P2 respectively includes the following steps: Input trigger signals to the second pins of the driver chips P1 and P2; The bootstrap capacitor C1 is precharged by two chip power supplies.

8. The pulse generating method for pulse ablation according to claim 4, characterized in that: During the generation of the positive polarity pulse, a trigger signal is input to the corresponding pins of the driver chips P1 and P2, wherein the corresponding pins include the first pin of the driver chip P1 and the second pin of P2; during the generation of the negative polarity pulse, a trigger signal is input to the corresponding pins of the driver chips P1 and P2, wherein the corresponding pins include the second pin of the driver chip P1 and the first pin of P2.

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