Chip screening method, device, equipment and medium

Abstract

The embodiment of the invention provides a chip screening method and device, equipment and a medium, and relates to the technical field of chip detection, and the method comprises the steps: introducing a test model message from a drainage port of an Ethernet switch chip, and taking each port of the Ethernet switch chip as a target port. And controlling each target port to perform a self-loop test based on the test model message, and closing the function of re-editing the frame verification sequence field of the Ethernet switch chip in the self-loop test process. And whether the Ethernet switch chip is the target chip is determined based on whether each target port has the frame verification sequence field error count for the test model message, so that the screening reliability of the Ethernet switch chip is improved.

Description

Technical Field

[0001] The present invention relates to the field of chip detection technology, and in particular to a chip screening method, device, equipment and medium. Background Art

[0002] Ethernet switch chips are key components in network equipment, enabling data exchange and routing between local area networks (LANs) and data center networks, as well as integrating various network security features. Therefore, reliability screening of Ethernet switch chips during production is crucial, directly impacting their yield rate when delivered to end users. Summary of the Invention

[0003] One of the purposes of the present invention includes, for example, providing a chip screening method, apparatus, device and medium to at least partially improve the reliability of Ethernet switch chip screening during the production process.

[0004] The embodiments of the present invention can be implemented as follows:

[0005] In a first aspect, an embodiment of the present invention provides a chip screening method, comprising:

[0006] Introducing test model messages from the drainage port of the Ethernet switch chip;

[0007] Using each port of the Ethernet switch chip as a target port, controlling each target port to perform a self-loop test based on the test model message, and disabling a function of the Ethernet switch chip to re-edit a frame check sequence field during the self-loop test;

[0008] Whether the Ethernet switching chip is a target chip is determined based on whether a frame check sequence field error count exists for the test model message at each target port.

[0009] In an optional embodiment, the bit transition probability of the test model message is greater than a preset threshold, and inside the Ethernet switch chip, the test model message can cause data bits on the storage unit and the bus to transition rapidly;

[0010] The bit width of the test model message is the same as the bit width of the internal data bus of the Ethernet switching chip.

[0011] In an optional implementation manner, controlling each of the target ports to perform a self-loop test based on the test model message includes:

[0012] Controlling each of the target ports to perform self-loop tests based on the test model message through an external PCB loopback of the Ethernet switch chip; or,

[0013] Control each of the target ports to perform self-loop tests based on the test model message through the SerDes loopback on the Ethernet switch chip.

[0014] In an optional implementation manner, controlling each of the target ports to perform a self-loop test based on the test model message includes:

[0015] Each of the target ports is controlled to switch to various port rates supported by the Ethernet switching chip, and self-loop tests are performed based on the test model message under different port rate conditions.

[0016] In an optional embodiment, disabling the function of the Ethernet switch chip re-editing the frame check sequence field during the self-loop test includes:

[0017] During the self-loop test, the test model message is controlled to be forwarded through the second layer of the Open Systems Interconnection Reference Model to disable the function of the Ethernet switch chip to re-edit the frame check sequence field.

[0018] In an optional implementation manner, controlling each of the target ports to perform a self-loop test based on the test model message includes:

[0019] After the Ethernet switching chip is subjected to a finished product test, a system-level test is added. During the system-level test, each of the target ports is controlled to perform a self-loop test based on the test model message.

[0020] In an optional embodiment, determining whether the Ethernet switching chip is a target chip based on whether a frame check sequence field error count exists for the test model message on each of the target ports includes:

[0021] Checking whether there is a frame check sequence field error count in the statistical information of the test model message in the receiving direction of each of the target ports;

[0022] If so, it indicates that some bits of the received test model message have changed, and it is determined that the Ethernet switch chip is a target chip with an internal fault;

[0023] If not, it means that the bits of the received test model message have not changed, and it is determined that the Ethernet switching chip is not the target chip with an internal fault.

[0024] In a second aspect, an embodiment of the present invention provides a chip screening device, comprising:

[0025] An information acquisition module is used to import test model messages from the drainage port of the Ethernet switch chip;

[0026] An information processing module is used to use each port of the Ethernet switching chip as a target port, control each of the target ports to perform a self-loop test based on the test model message, and disable the function of the Ethernet switching chip to re-edit the frame check sequence field during the self-loop test; and determine whether the Ethernet switching chip is a target chip based on whether a frame check sequence field error count exists for each of the target ports for the test model message.

[0027] In a third aspect, an embodiment of the present invention provides an electronic device comprising: a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein when the processor executes the program, the chip screening method described in any one of the aforementioned embodiments is implemented.

[0028] In a fourth aspect, an embodiment of the present invention provides a computer-readable storage medium, wherein the computer-readable storage medium includes a computer program, and when the computer program is executed, the electronic device where the computer-readable storage medium is located is controlled to execute the chip screening method described in any one of the aforementioned embodiments.

[0029] The beneficial effects of the embodiments of the present invention include, for example: by introducing a test model message to perform a self-loop test on each target port of the Ethernet switching chip, during the test process, the function of the Ethernet switching chip to re-edit the frame check sequence field is turned off, so that the error count of the frame check sequence field of the opposite end can be used to determine whether there are certain faults inside the Ethernet switching chip that cause the test model message to be rewritten, thereby conveniently improving the reliability of chip screening and improving the yield of the Ethernet switching chip to the user. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following briefly introduces the drawings required for use in the embodiments. It should be understood that the following drawings only illustrate certain embodiments of the present invention and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other relevant drawings can be obtained based on these drawings without paying any creative work.

[0031] Figure 1 A schematic diagram showing the composition of an Ethernet message provided by an embodiment of the present invention is shown.

[0032] Figure 2 A schematic diagram of data forwarding inside an Ethernet switch chip provided by an embodiment of the present invention is shown.

[0033] Figure 3 A schematic diagram of an application scenario provided by an embodiment of the present invention is shown.

[0034] Figure 4A schematic flow chart of a chip screening method provided by an embodiment of the present invention is shown.

[0035] Figure 5 A schematic diagram of data of an 8-bit buffer at various time points provided by an embodiment of the present invention is shown.

[0036] Figure 6 FIG. 4 shows a change of a buffer bit according to an embodiment of the present invention with time as the horizontal axis.

[0037] Figure 7 A schematic diagram of bit hopping provided by an embodiment of the present invention is shown.

[0038] Figure 8 A schematic diagram showing ports of an Ethernet switch chip provided by an embodiment of the present invention is shown.

[0039] Figure 9 An exemplary structural block diagram of a chip screening device provided by an embodiment of the present invention is shown.

[0040] Icons: 100 - electronic device; 110 - memory; 120 - processor; 130 - communication module; 140 - chip screening device; 141 - information acquisition module; 142 - information processing module. DETAILED DESCRIPTION

[0041] As a key component of network equipment, Ethernet switch chips require significant reliability screening during the production process. For example, during production testing, screening out relatively weak Ethernet switch chips is crucial for improving the quality of finished Ethernet switch chips and directly impacts the yield rate of Ethernet switch chips delivered to users.

[0042] Research has found that the reliability of Ethernet switch chip screening during production testing still needs to be improved. The analysis is as follows:

[0043] like Figure 1 As shown in FIG, the main components of an Ethernet message include: destination MAC address (MACDA), source MAC address (MACSA), payload (PAYLOAD), frame check sequence (FCS), etc.

[0044] Among them, FCS is a mechanism for detecting data transmission errors. In Ethernet, FCS usually uses a cyclic redundancy check (CRC) algorithm to calculate a 32-bit check value.

[0045] After receiving the complete frame, the receiving end will calculate the CRC-32 value of the received data (including the original data and FCS) again. If the calculated CRC value is 0, it means that no error occurred during the data transmission process. Otherwise, it means that the data may have an error during the transmission process.

[0046] Therefore, the error checking of Ethernet packets during transmission is usually detected by the FCS field.

[0047] In Ethernet switching chips, similar redundant check bits are usually included in register entries to ensure that the stored data is correct. Figure 2 As shown, on the bus / buffer, due to the large chip size and low error probability, redundancy protection is usually not performed, resulting in the inability to detect and filter out data transmission errors.

[0048] In order to improve the reliability of Ethernet switch chip screening, a final test (FT) can be performed on the Ethernet switch chip. The final test is usually divided into an AC scan test and a DC scan test. The final test can screen out some Ethernet switch chips that do not meet the requirements, but the coverage of the chips usually cannot reach 100%, and there is a possibility of missing the chips.

[0049] Based on the above research, an embodiment of the present invention provides a chip screening solution. After the finished product test, a system-level test (SLT) is added. By simulating the actual usage scenarios of end customers, as many Ethernet switching chips with weak buses / buffers as possible, such as those that produce values ​​inconsistent with expectations on the bus / buffer, are screened out. This improves the chip screening reliability, increases the yield of chips to customers, and enhances the customer's usage experience.

[0050] The defects in the above solutions are the results obtained by the inventors after practice and careful research. Therefore, the discovery process of the above problems and the solutions proposed in the embodiments of the present invention below should be the contributions made by the inventors in the invention process.

[0051] To make the objectives, technical solutions, and advantages of the embodiments of the present invention more clear, the technical solutions of the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Generally, the components of the embodiments of the present invention described and shown in the drawings herein can be arranged and designed in various different configurations.

[0052] Therefore, the following detailed description of the embodiments of the present invention provided in the accompanying drawings is not intended to limit the scope of the invention as claimed, but rather merely represents selected embodiments of the present invention. All other embodiments derived by persons of ordinary skill in the art based on the embodiments of the present invention without creative effort shall fall within the scope of protection of the present invention.

[0053] It should be noted that the terms "comprises," "includes," or any other variations thereof are intended to encompass non-exclusive inclusion, such that a process, method, article, or apparatus that includes a series of elements includes not only those elements but also other elements not explicitly listed, or elements inherent to such process, method, article, or apparatus. In the absence of further limitations, an element defined by the phrase "comprises a ..." does not preclude the presence of other identical elements in the process, method, article, or apparatus that includes the element.

[0054] It should be noted that similar reference numerals and letters denote similar items in the following drawings, and therefore, once an item is defined in one drawing, it does not need to be further defined or explained in subsequent drawings.

[0055] It should be noted that, in the absence of conflict, the features in the embodiments of the present invention may be combined with each other.

[0056] Please refer to Figure 3 , is a block diagram of an electronic device 100 provided in this embodiment. The electronic device 100 in this embodiment may be a server, processing device, or processing platform capable of data interaction and processing. For example, the electronic device 100 may be a network device for communication, etc.

[0057] The electronic device 100 includes a memory 110, a processor 120, and a communication module 130. The memory 110, processor 120, and communication module 130 are electrically connected to each other directly or indirectly to enable data transmission or exchange. For example, these components can be electrically connected to each other via one or more communication buses or signal lines.

[0058] The memory 110 is used to store programs or data. The memory 110 may be, but is not limited to, a random access memory (RAM), a read-only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), etc.

[0059] The processor 120 is used to read / write data or programs stored in the memory 110 and execute corresponding functions.

[0060] The communication module 130 is used to establish a communication connection between the electronic device 100 and other communication terminals through the network, and to send and receive data through the network.

[0061] It should be understood that Figure 3 The structure shown is only a schematic diagram of the structure of the electronic device 100. The electronic device 100 may also include Figure 3 More or fewer components than shown, or with Figure 3 Different configurations shown. Figure 3 Each component shown in the figure can be implemented by hardware, software or a combination thereof.

[0062] Please refer to Figure 4 , which is a flow chart of a chip screening method provided by an embodiment of the present invention, can be obtained by Figure 3 The electronic device 100 executes, for example, the processor 120 in the electronic device 100. The chip screening method includes S110, S120 and S130.

[0063] S110: Import a test model message from the drainage port of the Ethernet switch chip.

[0064] S120, taking each port of the Ethernet switch chip as a target port, controlling each target port to perform a self-loop test based on the test model message, and disabling the function of the Ethernet switch chip to re-edit the frame check sequence field during the self-loop test.

[0065] S130: Determine whether the Ethernet switching chip is a target chip based on whether a frame check sequence field error count exists for the test model message at each target port.

[0066] Through the above solution, target chips can be screened more comprehensively during the chip production and testing phase, thereby improving the reliability of finished chips and the yield rate at the end customer end, improving the quality of Ethernet switching chips, and making up for the shortcomings of finished product testing and screening.

[0067] In S110, a port may be randomly selected from the ports of the Ethernet switch chip as a drainage port to introduce the test model message.

[0068] Test model messages can be flexibly selected. For example, to comprehensively test the performance of an Ethernet switch chip, a test model message with rapid bit transitions, such as one with a bit transition probability greater than a preset threshold, can be selected. This allows the test model message to rapidly transition data bits in the storage unit and on the bus within the Ethernet switch chip.

[0069] For example, Figure 5 As shown in the figure, a buffer data with a length of 8 bits is given as an example. Figure 5 The first line is the data of the buffer at time point 0 under normal circumstances. Figure 5 The second line is the data of the buffer at time point 0+tick under normal circumstances. Figure 5 The third line shows that when the buffer is at 0+tick, there may be abnormal data.

[0070] Please refer to Figure 6 , showing the change of a buffer bit with time as the horizontal axis. (a) is a diagram of a normal 0 / 1 transition. (b) is a diagram of an abnormal 0 / 1 transition when the Ethernet switch chip has poor performance and a bit remains in one state for a long time and has no time to flip within a short period of time.

[0071] Taking the test model message of fast bit jump as an example, 0xAA and 0x55 are selected, which are converted into binary as 0b10101010 and 0b01010101. Based on this test model message, the data bits in a buffer / storage unit inside the Ethernet switch chip can jump rapidly, challenging the performance of the Ethernet switch chip's buffer / storage unit.

[0072] For another example, in order to optimize performance and improve efficiency, a test model message having the same bit width as the internal data bus bit width of the Ethernet switch chip may be selected.

[0073] For example, please refer to Figure 7When the test model message is selected to be the same as the bit width of the internal data bus of the Ethernet switching chip, such as the internal bus width of the Ethernet switching chip is 32 bits, then when there are two test model messages, the two test model messages can be 0xffffffff and 0x00000000 respectively. In this way, the two test model messages are output to the same bus, which can make the content on the same bus jump quickly.

[0074] After the test model message is introduced through the diversion port in S110, in S120, each target port is controlled to perform a self-loop test based on the test model message, which can be flexibly implemented.

[0075] For example, to ensure screening reliability, a system-level test may be added after the Ethernet switch chip is subjected to product testing. During the system-level test, each target port is controlled to perform a self-loop test based on the test model message.

[0076] For another example, each of the target ports may be controlled to perform a self-loop test based on the test model message through an external printed circuit board (PCB) of the Ethernet switch chip.

[0077] For another example, each of the target ports may be controlled to perform a self-loop test based on the test model message through a SerDes loopback on the Ethernet switch chip.

[0078] SerDes (Serializers) are primarily used for serialization and deserialization, receiving and transmitting high-speed serial data over serial channels. By designing each target port on the Ethernet switch chip to send and receive loopbacks from the SerDes, all hardware resources on each target port are covered by the test model messages, thereby ensuring comprehensive testing of the Ethernet switch chip. Loopbacks can be implemented using external optical modules, copper cables, and other devices.

[0079] Please refer to Figure 8 , provides a schematic diagram of each target port (including the drainage port and the remaining ports) when an application-specific integrated circuit (ASIC) switching chip is selected as the Ethernet switching chip.

[0080] In related technologies, Ethernet switching chips typically have extensive non-Layer 2 functionality and can perform numerous editing operations on messages. For example, Ethernet switching chips recalculate and edit the Frame Check Sequence (FCS) field of Ethernet messages. However, to ensure convenient and reliable testing of Ethernet switching chips based on test model messages and detect unexpected changes caused by the Ethernet switching chip's internal circuitry, Ethernet switching chips must be designed to disable the Frame Check Sequence (FCS) field re-editing function during loopback testing. By not editing test model messages, the automatic Frame Check Sequence (FCS) editing function of the Ethernet switching chip can be prevented from affecting screening.

[0081] For example, during the self-loop test, the test model message can be controlled to be forwarded through the second layer of the Open System Interconnect (OSI) reference model to disable the function of the Ethernet switching chip to re-edit the frame check sequence field, ensuring that the test model message is not changed.

[0082] After controlling each target port to perform self-loop tests based on the test model message in S120, in S130, determining whether the Ethernet switching chip is a target chip based on whether there is a frame check sequence field error count for the test model message at each target port can be flexibly implemented.

[0083] For example, the receiving direction of each target port can be checked to see whether there is a frame check sequence field error count in the statistical information of the test model message. If so, it indicates that certain bits of the received test model message have changed, and the Ethernet switch chip is determined to be a target chip with an internal fault. If not, it indicates that the bits of the received test model message have not changed, and the Ethernet switch chip is determined not to be a target chip with an internal fault.

[0084] By sending the expected test model message to each target port and disabling the function of re-editing the frame check sequence field, it is possible to check whether the statistical information of the receiving direction on each target port contains FCS error counts to determine whether the Ethernet switch chip is the target chip.

[0085] If there is an FCS error, it means that some bits of the current message are not the same as the bits of the original test model message, indicating that there is a fault inside the Ethernet switch chip and it is a target chip that needs to be screened out. Otherwise, it means that there is no fault inside the Ethernet switch chip and it is not a target chip that needs to be screened out.

[0086] The above describes the overall principle of chip screening. By introducing the expected test model message into the Ethernet switch chip, the internal bitstream of the message changes rapidly and sufficiently, forcing the Ethernet switch chip to not edit the message. For example, compared to related art, assuming the original message content is X and the FCS field is Y, then Y = f(X), where f(x) is the algorithm for generating the FCS field. This embodiment forces messages entering the Ethernet switch chip to remain unchanged after being forwarded by the Ethernet switch chip. This allows the FCS detection function of the peer end to quickly determine whether the message has been rewritten due to internal defects in the Ethernet switch chip, achieving convenient and reliable detection of the target chip.

[0087] Taking into account that various Ethernet switching chips may support different port rates, in order to further improve the reliability of screening, each target port can be controlled to switch to various port rates supported by the Ethernet switching chip, and self-loop tests can be performed based on the test model message under different port rate conditions.

[0088] By switching the target port to different port rates supported by various Ethernet switching chips, self-loop tests are performed for each port rate based on the test model message. Through multiple repeated tests, all port rates supported by the Ethernet switching chip are covered, thereby maximizing the reliability of chip screening.

[0089] In order to execute the corresponding steps in the above embodiments and various possible methods, a method for implementing a chip screening device is given below. Figure 9 , Figure 9 This is a functional module diagram of a chip screening device 140 provided in an embodiment of the present invention. The chip screening device 140 can be applied to Figure 3 The electronic device 100 is shown. It should be noted that the basic principles and technical effects of the chip screening device 140 provided in this embodiment are the same as those of the above-mentioned embodiments. For the sake of brevity, any details not mentioned in this embodiment can be referred to the corresponding contents of the above-mentioned embodiments. The chip screening device 140 includes an information acquisition module 141 and an information processing module 142.

[0090] The information acquisition module 141 is used to import the test model message from the drainage port of the Ethernet switch chip.

[0091] The information processing module 142 is used to take each port of the Ethernet switching chip as a target port, control each of the target ports to perform a self-loop test based on the test model message, and turn off the function of the Ethernet switching chip to re-edit the frame check sequence field during the self-loop test; and determine whether the Ethernet switching chip is a target chip based on whether there is a frame check sequence field error count for the test model message on each of the target ports.

[0092] Based on the above, an embodiment of the present invention further provides a computer-readable storage medium, which includes a computer program. When the computer program is running, it controls the electronic device where the computer-readable storage medium is located to execute the above chip screening method.

[0093] By adopting the above-mentioned scheme in the embodiment of the present invention, the production screening of Ethernet switching chips is carried out through Ethernet Layer 2 switching forwarding without changing the message content and FCS characteristics. The logical screening topology can cover all logical functions of the Ethernet switching chip and all port rates supported by the Ethernet switching chip, ensuring that the logical functions at each port rate are not missed, thereby ensuring the reliability of chip screening.

[0094] In the several embodiments provided by the present invention, it should be understood that the disclosed devices and methods can also be implemented in other ways. The device embodiments described above are merely illustrative. For example, the flowcharts and block diagrams in the accompanying drawings show the possible architectures, functions, and operations of the devices, methods, and computer program products according to multiple embodiments of the present invention. In this regard, each box in the flowchart or block diagram can represent a module, program segment, or part of the code, which contains one or more executable instructions for implementing the specified logical functions. It should also be noted that in some alternative implementations, the functions marked in the boxes can also occur in an order different from that marked in the accompanying drawings. For example, two consecutive boxes can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each box in the block diagram and / or flowchart, as well as the combination of boxes in the block diagram and / or flowchart, can be implemented using a dedicated hardware-based system that performs the specified functions or actions, or can be implemented using a combination of dedicated hardware and computer instructions.

[0095] In addition, the functional modules in the various embodiments of the present invention may be integrated together to form an independent part, or each module may exist independently, or two or more modules may be integrated to form an independent part.

[0096] If the functions are implemented in the form of software function modules and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, or the part that contributes to the prior art, or the part of the technical solution, can be embodied in the form of a software product. The computer software product is stored in a storage medium and includes several instructions for enabling a computer device (which can be a personal computer, server, or network device, etc.) to execute all or part of the steps of the method described in each embodiment of the present invention. The aforementioned storage medium includes various media that can store program codes, such as a USB flash drive, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk, or an optical disk.

[0097] The foregoing description is merely a preferred embodiment of the present invention and is not intended to limit the present invention. Those skilled in the art will readily appreciate that various modifications and variations of the present invention are possible. Any modifications, equivalent substitutions, or improvements made within the spirit and principles of the present invention are intended to be within the scope of protection of the present invention.

Claims

1. A chip screening method, characterized in that: include: Introducing test model messages from the drainage port of the Ethernet switch chip; Using each port of the Ethernet switch chip as a target port, controlling each target port to perform a self-loop test based on the test model message, and disabling a function of the Ethernet switch chip to re-edit a frame check sequence field during the self-loop test; Whether the Ethernet switching chip is a target chip is determined based on whether a frame check sequence field error count exists for the test model message at each target port.

2. The chip screening method according to claim 1, characterized in that The bit transition probability of the test model message is greater than a preset threshold value, and inside the Ethernet switch chip, the test model message can cause the data bits on the storage unit and the bus to transition rapidly; The bit width of the test model message is the same as the bit width of the internal data bus of the Ethernet switching chip.

3. The chip screening method according to claim 1, characterized in that The controlling each of the target ports to perform a self-loop test based on the test model message includes: Controlling each of the target ports to perform self-loop tests based on the test model message through an external PCB loopback of the Ethernet switch chip; or, Control each of the target ports to perform self-loop tests based on the test model message through the SerDes loopback on the Ethernet switch chip.

4. The chip screening method according to claim 1, characterized in that The controlling each of the target ports to perform a self-loop test based on the test model message includes: Each of the target ports is controlled to switch to various port rates supported by the Ethernet switching chip, and self-loop tests are performed based on the test model message under different port rate conditions.

5. The chip screening method according to claim 1, characterized in that The step of disabling the function of re-editing the frame check sequence field of the Ethernet switch chip during the self-loop test includes: During the self-loop test, the test model message is controlled to be forwarded through the second layer of the Open Systems Interconnection Reference Model to disable the function of the Ethernet switch chip to re-edit the frame check sequence field.

6. The chip screening method according to claim 1, characterized in that The controlling each of the target ports to perform a self-loop test based on the test model message includes: After the Ethernet switching chip is subjected to a finished product test, a system-level test is added. During the system-level test, each of the target ports is controlled to perform a self-loop test based on the test model message.

7. The chip screening method according to any one of claims 1 to 6, characterized in that: The determining whether the Ethernet switching chip is a target chip based on whether a frame check sequence field error count exists for the test model message at each target port includes: Checking whether there is a frame check sequence field error count in the statistical information of the test model message in the receiving direction of each of the target ports; If so, it indicates that some bits of the received test model message have changed, and it is determined that the Ethernet switch chip is a target chip with an internal fault; If not, it means that the bits of the received test model message have not changed, and it is determined that the Ethernet switching chip is not the target chip with an internal fault.

8. A chip screening device, characterized in that: include: An information acquisition module is used to import test model messages from the drainage port of the Ethernet switch chip; An information processing module is used to use each port of the Ethernet switching chip as a target port, control each of the target ports to perform a self-loop test based on the test model message, and disable the function of the Ethernet switching chip to re-edit the frame check sequence field during the self-loop test; and determine whether the Ethernet switching chip is a target chip based on whether a frame check sequence field error count exists for each of the target ports for the test model message.

9. An electronic device, characterized in that: include: A memory, a processor, and a computer program stored in the memory and executable on the processor, wherein when the processor executes the program, the chip screening method according to any one of claims 1 to 7 is implemented.

10. A computer-readable storage medium, characterized in that The computer-readable storage medium includes a computer program, and when the computer program is executed, the electronic device where the computer-readable storage medium is located is controlled to execute the chip screening method according to any one of claims 1 to 7.

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