Circuit board manufacturing method suitable for Msap process and circuit board

Abstract

The invention relates to the technical field of circuit board manufacturing, and discloses a circuit board manufacturing method suitable for an Msap process and a circuit board, and the method comprises the steps: S100, pasting a dry film at a position corresponding to an etching line on one side or two sides of a laminated board; s200, pattern electroplating is conducted on the laminated board till the difference value between the height of the laminated board and the height of the dry film is within a preset value range; s300, the surface, subjected to pattern electroplating, of the laminated board is leveled, and the horizontal plane of the leveled laminated board coincides with the end face of the leveled dry film; and S400, removing the dry film attached to the surface of the laminated board, and carrying out surface treatment to obtain a finished product carrier board. According to the method, the electroplated layer is removed through leveling with the dry film, so that the electroplated layer is overlapped with the end face of the dry film, the micro step difference between the electroplated layer and the dry film is eliminated, defects formed on the surface of the electroplated layer are removed, and secondary defects such as uneven solder infiltration and blind hole deviation can be fundamentally eliminated.

Description

Technical Field

[0001] The present invention relates to the field of circuit board manufacturing, and in particular to a circuit board manufacturing method and a circuit board suitable for the MSAP process. Background Art

[0002] The semi-additive process (Msap) is widely used in the field of IC substrates. MSap uses an electroplating process to produce graphics, which can achieve ultra-high-density wiring with line widths / spacing as low as 30μm or even 25μm, significantly meeting the stringent requirements for miniaturization and signal integrity in fields such as 5G communications and AI chip packaging. 14 This technology has gradually replaced traditional subtractive methods and become the mainstream solution for high-precision circuit board manufacturing due to its advantages in nearly rectangular line cross-sectional morphology and surface smoothness.

[0003] However, many technical difficulties remain in the field of MSAP processing. During the electroplating process, uneven current density distribution or turbulence in the plating solution flow field can easily form depressions or protrusions on the circuit surface, resulting in poor appearance. This not only causes excessive product scrapping, but also affects the soldering process due to uneven surface conditions, resulting in uneven solder infiltration, causing cold joints or component offset. Therefore, providing a circuit board manufacturing method and circuit board that can solve the problem of surface defects in the finished product after pattern electroplating has become an urgent problem to be solved. Summary of the Invention

[0004] The main purpose of the present invention is to provide a circuit board manufacturing method and a circuit board suitable for the MSAP process, aiming to solve the technical problem that depressions or protrusions are easily formed on the circuit surface after electroplating, causing surface quality defects of the circuit board.

[0005] To achieve the above-mentioned purpose, the present invention provides a circuit board manufacturing method suitable for the MSAP process, which is characterized in that it includes: step S100: laminating a dry film at the corresponding position of the etched circuit on one side or both sides of the laminate; step S200: performing graphic electroplating on the laminate until the difference between the height of the laminate and the height of the dry film is within a preset value range; step S300: leveling the surface of the laminate after graphic electroplating, wherein the horizontal surface of the laminate after leveling coincides with the end face of the dry film after leveling; step S400: removing the dry film adhered to the surface of the laminate and performing surface treatment to obtain a finished carrier board.

[0006] Optionally, step S010 is further included before step S100, in which photolithography and etching are performed in sequence on the surface of the incoming copper-clad laminate to form a first circuit layer, and at least one build-up board is pressed on one or both sides of the copper-clad laminate to form a laminate, wherein the build-up board includes a dielectric layer and a second circuit layer pressed on the surface of the first circuit layer, and the second circuit layer is arranged at an end of the dielectric layer facing away from the first circuit layer.

[0007] Optionally, the method further includes step S011 between step S010 and step S100, wherein a via hole is provided in the dielectric layer, and the aperture of the via hole changes from small to large from the surface of the first circuit layer to the second circuit layer.

[0008] Optionally, in step S100, a vacuum laminating machine is used to laminate the dry film to a preset position on the second circuit layer, and the laminating pressure range of the vacuum laminating machine is 0.4-0.6 MPa.

[0009] Optionally, in step S200, the via hole is first pulse plated until the via hole is filled, and then thickening plating is performed on the second circuit layer to obtain a plating leveling layer. The dry film bonding portion is plated to form an avoidance groove, and the thickening plating is stopped after the top wall of the avoidance groove protrudes 30±5μm from the top surface of the dry film.

[0010] Optionally, in step S300, the electroplated leveling layer is polished using a grinding plate, and the single grinding removal amount is controlled within 2 μm. After each grinding, the thickness of the electroplated leveling layer is measured using 3D visual inspection equipment, and the grinding plate preparation material includes alumina ceramics and silicon carbide.

[0011] Optionally, the grinding process is divided into a rough grinding stage and a fine grinding stage. In the rough grinding stage, the grinding plate uses an abrasive of at least 800 mesh to remove the electroplated leveling layer, and in the fine grinding stage, the grinding plate uses an abrasive of at least 2000 mesh to remove the electroplated leveling layer, and the abrasive is wrapped with synthetic resin in the rough grinding stage or the fine grinding stage.

[0012] Optionally, in step S400, a film stripping machine is used to strip the dry film in the electroplated leveling layer, and a film stripping liquid is sprayed on the surface of the laminate. After spraying, the laminate is baked and cleaned.

[0013] Optionally, the method further includes step S500 after step S400: differentially etching the electroplating leveling layer of the laminate, and controlling the distance between the bottom surface of the avoidance groove and the plane of the electroplating leveling layer after differential etching to be within 50 μm.

[0014] The present invention also provides a circuit board, comprising: a copper-clad board, a first circuit layer being provided on one or both sides; at least one build-up board being pressed onto one or both sides of the copper-clad layer, the build-up board comprising a dielectric layer, a second circuit layer, a via and an electroplating leveling layer, the dielectric layer being pressed onto the first circuit layer, the second circuit layer being arranged on a side of the dielectric layer facing away from the first circuit layer, the via being arranged in the dielectric layer, and the two ends of the via being connected to the first circuit layer and the second circuit layer respectively; the electroplating leveling layer being arranged on a side of the second circuit layer facing away from the dielectric layer, the electroplating leveling layer being provided with an avoidance groove for accommodating a protective layer; a protective layer being arranged on the electroplating leveling layer in the outermost build-up board, the protective layer filling the avoidance groove.

[0015] In the technical solution provided by the present invention, after the dry film is attached to the etched circuit, its height provides an accurate reference for subsequent electroplating. By controlling the preset value of the end face height difference between the electroplating layer and the dry film (generally ±1μm), the flow uniformity of the electroplating solution on the surface of the laminate can be ensured, and the local over-thickness or over-thinness caused by the difference in current density can be avoided. In addition, the photoresist film component of the dry film forms a rigid support structure during the leveling process to prevent the edge of the circuit from collapsing or deforming during mechanical leveling. In the leveling process, the electroplating layer is removed to make it coincide with the end face between the dry film, eliminating the small step difference between the two, and removing the defects formed on the surface of the electroplating layer, which can fundamentally eliminate secondary defects such as uneven solder wetting and blind hole offset. At this stage, the dry film acts as a sacrificial layer, bearing the cutting force of the leveling tool to protect the copper circuit below from damage. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] One or more embodiments are exemplarily illustrated by corresponding drawings, which do not constitute limitations on the embodiments. Elements with the same reference numerals in the drawings are represented as similar elements, and unless otherwise stated, the figures in the drawings do not constitute proportional limitations.

[0017] Figure 1 Schematic diagram of the process of manufacturing a circuit board using the MSAP process according to the present invention;

[0018] Figure 2 A schematic diagram of a processing route of an embodiment of a circuit board manufacturing method applicable to the MSAP process of the present invention;

[0019] Figure 3 This is a schematic diagram of the blanking structure in the process route of the circuit board manufacturing method applicable to the MSAP process of the present invention;

[0020] Figure 4 This is a schematic diagram of the structure of the first circuit layer in the process route of the circuit board manufacturing method applicable to the MSAP process of the present invention;

[0021] Figure 5 This is a processing structure diagram of the layer-building and lamination process in the process route of the circuit board manufacturing method applicable to the MSAP process of the present invention;

[0022] Figure 6 This is a processing structure diagram of the laser drilling process in the process route of the circuit board manufacturing method applicable to the MSAP process of the present invention;

[0023] Figure 7 This is a processing structure diagram of a pattern electroplating process in a process route of a circuit board manufacturing method applicable to the MSAP process of the present invention;

[0024] Figure 8 This is a processing structure diagram of the leveling process in the process route of the circuit board manufacturing method applicable to the MSAP process of the present invention;

[0025] Figure 9 This is a processing structure diagram of the film removal process in the process route of the circuit board manufacturing method applicable to the MSAP process of the present invention;

[0026] Figure 10 This is a structural diagram of a finished circuit board after the surface treatment process in the process route of the circuit board manufacturing method applicable to the MSAP process of the present invention;

[0027] Figure 11 This is a structural diagram of a finished circuit board produced using the circuit board manufacturing method and process route suitable for the MSAP process.

[0028] In the figure: 1, laminate; 11, copper clad board; 111, first circuit layer; 12, build-up board; 121, dielectric layer; 122, second circuit layer; 123, via; 1231, bump; 124, electroplating leveling layer; 1241, avoidance groove; 13, protective layer; 14, dry film. DETAILED DESCRIPTION

[0029] To facilitate understanding of the present invention, the present invention is described in more detail below with reference to the accompanying drawings and specific embodiments. It should be noted that when an element is described as being "fixed to" another element, it can be directly attached to the other element, or one or more elements can be interposed therebetween. When an element is described as being "connected to" another element, it can be directly connected to the other element, or one or more elements can be interposed therebetween. The terms "vertical," "horizontal," "left," "right," "inner," "outer," and similar expressions used in this specification are for illustrative purposes only. In the description of the present invention, the terms "first" and "second" are used for descriptive purposes only and are not to be construed as indicating relative importance or implicitly specifying the number of technical features indicated. Therefore, unless otherwise specified, features specified as "first" or "second" may explicitly or implicitly include one or more of such features; "plurality" means two or more. The term "comprising" and any variations thereof are intended to be non-exclusive, and one or more other features, integers, steps, operations, units, components, and / or combinations thereof may be present or added.

[0030] In addition, unless otherwise expressly specified and limited, the terms "installed", "connected" and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, an indirect connection through an intermediate medium, or internal communication between two components. All technical and scientific terms used in this specification have the same meaning as commonly understood by technicians in the technical field to which the present invention belongs. The terms used in the description of the present invention are only for the purpose of describing specific embodiments and are not intended to limit the present invention. The term "and / or" used in this specification includes any and all combinations of one or more related listed items.

[0031] In addition, the technical features involved in different embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other.

[0032] Please refer to Figures 1 to 11 The present invention provides a circuit board manufacturing method suitable for the MSAP process, which is characterized by comprising: step S100: laminating a dry film 14 at a corresponding position of the etched circuit on one side or both sides of a laminate 1; step S200: performing pattern electroplating on the laminate 1 until the height difference between the laminate 1 and the dry film 14 is within a preset value range; step S300: leveling the surface of the laminate 1 after pattern electroplating, wherein the horizontal surface of the laminate 1 after leveling coincides with the end surface of the dry film 14 after leveling; step S400: removing the dry film 14 laminating on the surface of the laminate 1 and performing surface treatment to obtain a finished carrier board.

[0033] In the technical solution provided by the present invention, after the dry film 14 is attached to the etched circuit, its height provides an accurate reference for subsequent electroplating. By controlling the preset value of the end face height difference between the electroplating layer and the dry film 14 (generally ±1μm), the flow uniformity of the electroplating solution on the surface of the laminate 1 can be ensured, and the local over-thickness or over-thinness caused by the difference in current density can be avoided. In addition, the photoresist film component of the dry film 14 forms a rigid support structure during the leveling process to prevent the edge of the circuit from collapsing or deforming during mechanical leveling. In the leveling process, the electroplating layer is removed to coincide with the end face between it and the dry film 14, eliminating the small step difference between the two, and removing the defects formed on the surface of the electroplating layer, which can fundamentally eliminate secondary defects such as uneven solder wetting and blind hole offset. At this stage, the dry film 14 acts as a sacrificial layer, bearing the cutting force of the leveling device and protecting the copper circuit below from damage.

[0034] Please refer to Figures 2 to 6 In this embodiment, step S010 is further included before step S100, in which a first circuit layer 111 is formed by sequentially performing photolithography and etching on the surface of the incoming copper-clad laminate 11, and at least one build-up board 12 is laminated on one or both surfaces of the copper-clad laminate 11 to form a laminate 1. The build-up board 12 includes a dielectric layer 121 and a second circuit layer 122 laminated on the surface of the first circuit layer 111. The second circuit layer 122 is disposed at an end of the dielectric layer 121 facing away from the first circuit layer 111. A via 123 is provided in the dielectric layer 121, and the aperture of the via 123 varies from small to large from the surface of the first circuit layer 111 to the second circuit layer 122. This laminate 1 is primarily suitable for the production of IC carriers. The copper layer on the surface of the copper-clad laminate 11 is formed through processes such as photolithography and etching to form a first circuit layer 111, providing an initial conductive path. Multiple build-up boards 12 can be installed on the upper and lower surfaces of the copper-clad laminate 11 through hot pressing as needed. The dielectric layer 121 in the build-up boards 12 is typically made of a low-dielectric material such as ABF (Ajinomoto Build-up Film). The primary function of the vias 123 is to conduct electricity between the first circuit layer 111 on the copper-clad laminate 11 and the second circuit layer 122 on the build-up boards 12. The aperture of the vias 123 gradually increases from the first circuit layer 111 to the second circuit layer 122. This gradual increase in opening size is intended to reduce gaps filled with electroplated metal during the subsequent electroplating of the vias 123, preventing the surface of the laminate 1 from being squeezed and collapsed by internal gaps during the subsequent leveling process, forming new pits.

[0035] Please refer to Figure 7In this embodiment, in step S100, a vacuum laminating machine is used to adhere the dry film 14 to a preset position on the second circuit layer 122, and the laminating pressure range of the vacuum laminating machine is 0.4-0.6 MPa. In the subsequent leveling process, a grinding plate is usually used to level the surface of the laminate 1, so it is necessary to apply the dry film 14 to the weak circuit position of the second circuit layer 122 to protect the circuit from being worn during the grinding process. In the initial lamination stage, a low pressure of 0.3-0.4 MPa can be used to allow the dry film 14 to initially cover the surface of the second circuit layer 122, reducing the deformation effect of mechanical stress on the thin substrate; in the high-pressure sealing stage, it can be increased to 0.6-0.7 MPa, focusing on the edge area of ​​the circuit to enhance the adhesion between the dry film 14 and the copper layer, and avoid edge peeling during grinding. Silica nanoparticles can also be added to the adhesive layer of the dry film 14 to improve wear resistance and scratch resistance, and to reduce the probability of the dry film 14 detaching during the grinding process.

[0036] Please refer to Figure 8 In this embodiment, in step S200, pulse plating is first performed on the via hole 123 until the via hole 123 is filled. Concentration polarization is eliminated by periodic reverse current, so that the via hole 123 is filled without voids, so that the position of the via hole 123 will not produce secondary surface defects in the subsequent leveling process; then thickening plating is performed on the second circuit layer 122 to obtain the electroplating leveling layer 124, and the avoidance groove 1241 is formed by electroplating at the contact part of the dry film 14 until the top wall of the avoidance groove 1241 protrudes from the top surface of the dry film 14 by 30±5μm. Then, the thickening plating is stopped. By controlling the thickness gradient of the thickening plating, zero accidental damage to the protection area of ​​the dry film 14 during subsequent grinding is ensured, and a clear physical stop is provided for the grinding plate.

[0037] Please refer to Figure 9 In this embodiment, in step S300, the electroplated leveling layer 124 is polished using a grinding plate, with the removal amount per grinding cycle controlled to within 2μm. After each grinding cycle, the thickness of the electroplated leveling layer 124 is measured using 3D visual inspection equipment. The grinding plate is made of alumina ceramic and silicon carbide. The alumina ceramic / silicon carbide grinding plate, combined with a single grinding removal amount of ≤2μm and real-time visual scanning feedback of the electroplated leveling layer 124 by a 3D line scan camera, ensures a surface roughness Ra of ≤0.05μm for the electroplated leveling layer 124. This meets the exposure requirements for fine lines less than 5μm while eliminating defects such as pits and bumps 1231.

[0038] In this embodiment, the grinding process is divided into a coarse grinding stage and a fine grinding stage. The coarse grinding stage uses an abrasive with a mesh size of at least 800 to remove the electroplated leveling layer 124. The fine grinding stage uses an abrasive with a mesh size of at least 2000 to remove the electroplated leveling layer 124. Synthetic resin-coated abrasives are used during either the coarse or fine grinding stages. This phased grinding process, combined with synthetic resin-coated abrasives, rapidly removes excess electroplating while achieving an ultra-high surface flatness of ≤0.03 μm. The resin's cushioning effect reduces the breakage rate of the dry film 14, extending the life of the abrasive plate and reducing coolant usage, achieving a balance of high efficiency, minimal damage, and environmental friendliness.

[0039] Please refer to Figure 10 In this embodiment, in step S400, a film stripper is used to strip the dry film 14 from the electroplated leveling layer 124, and a film stripping solution is sprayed on the surface of the laminate 1. After spraying, the laminate 1 is baked and cleaned. The main purpose of stripping the dry film 14 is to remove the protective layer on the surface of the electroplated leveling layer 124, exposing the copper surface area to be etched, thereby providing a foundation for precise patterning processing for subsequent differential etching. The dry film 14 acts as a photosensitive resist layer, forming a solidified area that protects the circuit after exposure and development. After stripping, the uncured area is removed, allowing the etching solution to selectively corrode the exposed copper surface, ultimately forming a circuit pattern. This process ensures etching accuracy and circuit integrity by controlling the adhesion and corrosion resistance of the dry film 14.

[0040] This embodiment further includes step S500, which follows step S400: differential etching of the electroplated leveling layer 124 of the laminate 1, controlling the distance between the bottom surface of the avoidance groove 1241 and the plane of the electroplated leveling layer 124 after differential etching to within 50 μm. Differential etching selectively removes material in stages, reducing uneven erosion of the electroplated leveling layer 124. This prevents copper thinning or increased hole wall roughness caused by excessive etching, maintaining the bonding strength between the plated layer and the substrate. Furthermore, by controlling the distance between the bottom surface of the avoidance groove 1241 and the plane of the plated layer, the internal stress distribution of the laminate 1 is balanced, reducing defects such as warping and delamination caused by stress concentration during subsequent processing or use.

[0041] Please refer to Figure 11The present invention also provides a circuit board, comprising: a copper clad plate 11, with a first circuit layer 111 provided on one or both sides; at least one build-up plate 12, pressed onto one or both sides of the copper clad layer, the build-up plate 12 comprising a dielectric layer 121, a second circuit layer 122, a via 123 and an electroplating leveling layer 124, the dielectric layer 121 being pressed onto the first circuit layer 111, the second circuit layer 122 being provided on a side of the dielectric layer 121 facing away from the first circuit layer 111, the via 123 being provided in the dielectric layer 121, and the two ends of the via 123 being respectively connected to the first circuit layer 111 and the second circuit layer 122 The electroplating leveling layer 124 is disposed on the side of the second circuit layer 122 facing away from the dielectric layer 121. The electroplating leveling layer 124 is provided with a relief groove 1241 for accommodating the protective layer. The protective layer 13 is disposed on the electroplating leveling layer 124 in the outermost build-up board 12. The protective layer 13 fills the relief groove 1241. Through solder resist and surface treatment, the protective layer 13 is formed on the outward-facing side of the electroplating leveling layer 124. The solder resist layer covers the surface of the electroplating leveling layer 124, selectively exposing the pad area, effectively isolating adjacent circuits from short circuit risks while preventing moisture and oxidizing media from corroding the copper layer. After the protective layer 13 fills the relief groove 1241, it forms a continuous protective interface, eliminating exposed copper points at the edge of the electroplating leveling layer 124.

[0042] The above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit them. Under the concept of the present invention, the technical features in the above embodiments or different embodiments can also be combined, the steps can be implemented in any order, and there are many other variations of the different aspects of the present invention as described above. For the sake of simplicity, they are not provided in detail. Although the present invention has been described in detail with reference to the above embodiments, ordinary technicians in this field should understand that it is still possible to modify the technical solutions described in the above embodiments, or to make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A method for manufacturing a circuit board suitable for the MSAP process, characterized in that: include: Step S100: Laminating a dry film (14) at positions corresponding to the etched circuits on one or both sides of the laminate (1); Step S200: performing pattern electroplating on the laminate (1) until the height difference between the laminate (1) and the dry film (14) is within a preset value range; Step S300: leveling the surface of the laminate (1) after pattern electroplating, wherein the horizontal surface of the leveled laminate (1) coincides with the end surface of the leveled dry film (14); Step S400: removing the dry film (14) adhered to the surface of the laminate (1) and performing surface treatment to obtain a finished carrier board.

2. The method for manufacturing a circuit board suitable for the MSAP process according to claim 1, characterized in that: The method further includes a step S010 before step S100, wherein photolithography and etching are sequentially performed on the surface of the incoming copper-clad plate (11) to form a first circuit layer (111), and at least one build-up plate (12) is pressed on one or both sides of the copper-clad plate (11) to form a laminate (1), wherein the build-up plate (12) includes a dielectric layer (121) pressed on the surface of the first circuit layer (111) and a second circuit layer (122), and the second circuit layer (122) is arranged at an end of the dielectric layer (121) facing away from the first circuit layer (111).

3. The method for manufacturing a circuit board suitable for the MSAP process according to claim 2, characterized in that: The method further includes step S011 between step S010 and step S100, wherein a via hole (123) is provided in the dielectric layer (121), and the aperture of the via hole (123) changes from small to large from the surface of the first circuit layer (111) to the second circuit layer (122).

4. The method for manufacturing a circuit board suitable for the MSAP process according to claim 3, characterized in that: In the step S100, a vacuum laminating machine is used to laminate the dry film (14) to a preset position on the second circuit layer (122), wherein the laminating pressure of the vacuum laminating machine is in the range of 0.4-0.6 MPa.

5. The method for manufacturing a circuit board suitable for the MSAP process according to claim 4, characterized in that: In step S200, the through hole (123) is first pulse-plated until the through hole (123) is filled, and then thickening plating is performed on the second circuit layer (122) to obtain a plating leveling layer (124). The dry film (14) is plated at the joint to form an avoidance groove (1241), and the thickening plating is stopped after the top wall of the avoidance groove (1241) protrudes 30±5μm from the top surface of the dry film (14).

6. The method for manufacturing a circuit board suitable for the MSAP process according to claim 5, characterized in that: In step S300, the electroplated leveling layer (124) is polished using a grinding plate, and the amount of removal in a single polishing is controlled to be within 2 μm. After each polishing, the thickness of the electroplated leveling layer (124) is measured using a 3D visual inspection device, and the grinding plate is made of materials including alumina ceramics and silicon carbide.

7. The method for manufacturing a circuit board suitable for the MSAP process according to claim 6, characterized in that: The grinding process is divided into a rough grinding stage and a fine grinding stage. In the rough grinding stage, the grinding plate uses an abrasive of at least 800 mesh to remove the electroplated leveling layer (124). In the fine grinding stage, the grinding plate uses an abrasive of at least 2000 mesh to remove the electroplated leveling layer (124). In the rough grinding stage or the fine grinding stage, the abrasive is wrapped with synthetic resin.

8. The method for manufacturing a circuit board suitable for the MSAP process according to any one of claims 1 to 7, characterized in that: In step S400, a film stripping machine is used to strip the dry film (14) in the electroplated leveling layer (124), and a film stripping liquid is sprayed on the surface of the laminate (1). After spraying, the laminate (1) is baked and cleaned.

9. The method for manufacturing a circuit board suitable for the MSAP process according to claim 8, characterized in that: The method further comprises step S500 located after step S400: differentially etching the electroplating leveling layer (124) of the laminate (1), and controlling the distance between the bottom surface of the avoidance groove (1241) and the plane of the electroplating leveling layer (124) after the differential etching to be within 50 μm.

10. A circuit board, characterized in that: include: A copper-clad plate (11) having a first circuit layer (111) on one or both sides; At least one build-up plate (12) is pressed onto one or both sides of the copper clad layer, the build-up plate (12) comprising a dielectric layer (121), a second circuit layer (122), a via (123) and an electroplating leveling layer (124), the dielectric layer (121) being pressed onto the first circuit layer (111), the second circuit layer (122) being arranged on a side of the dielectric layer (121) facing away from the first circuit layer (111), the via (123) being arranged in the dielectric layer (121), and two ends of the via (123) being connected to the first circuit layer (111) and the second circuit layer (122) respectively; the electroplating leveling layer (124) being arranged on a side of the second circuit layer (122) facing away from the dielectric layer (121), and the electroplating leveling layer (124) being provided with an avoidance groove (1241) for accommodating a protective layer; A protective layer (13) is provided on the electroplated leveling layer (124) in the outermost build-up plate (12), and the protective layer (13) fills the avoidance groove (1241).

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