Voltage stabilizer chip management system and method, electronic equipment and storage medium

Abstract

The invention discloses a voltage stabilizer chip management system and method, electronic equipment and a storage medium, and relates to the technical field of electric digital data processing, the monitoring of a voltage stabilizer chip can be realized through a management controller, the management controller can set two monitoring tasks, one monitoring task is used for obtaining an alarm signal and positioning an abnormal chip, and the other monitoring task is used for obtaining an alarm signal and positioning an abnormal chip. And the other one can call information according to abnormal chip positioning so as to manage the chip of the voltage stabilizer, and through more efficient alarm signal acquisition and hierarchical task design, the technical problems of rough abnormal chip positioning, delayed alarm signal acquisition, full data acquisition required during diagnosis, resource waste and the like in related technologies are solved, and the diagnosis efficiency is improved. The technical effects of efficiently and accurately positioning the abnormal chip and reasonably allocating resources to optimize the chip management of the voltage stabilizer are achieved.

Description

Technical Field

[0001] The present invention relates to the technical field of electronic digital data management, and in particular to a voltage stabilizer chip management system, method, electronic equipment and storage medium. Background Art

[0002] The reliable operation of the voltage stabilizer chip is crucial to the stability of the motherboard's timing. In related technologies, a management controller can interact with the motherboard's complex programmable logic device (CPLD / FPGA) to read preset registers to diagnose timing faults. However, this method has significant limitations: it only focuses on the timing status register and does not involve active monitoring and alarm response mechanisms for the voltage stabilizer chip. When the voltage stabilizer chip is abnormal, it is impossible to accurately locate the source of the fault, resulting in low diagnostic efficiency; the lack of a cross-process coordination mechanism makes it impossible to dynamically trigger targeted log collection, requiring the retrieval of massive amounts of raw register data; the alarm signal must be transferred through multiple layers, making it difficult to achieve sub-second fault capture and targeted response, increasing the risk of system downtime.

[0003] In summary, in the related technologies, abnormal chip positioning is rough, alarm signal acquisition is delayed, and full data collection is required for diagnosis, which easily leads to waste of resources and urgently needs to be improved. Summary of the Invention

[0004] The present invention provides a voltage stabilizer chip management system, method, electronic device and storage medium to at least solve technical problems in related technologies such as rough positioning of abnormal chips, delayed acquisition of alarm signals, and the need for full data collection during diagnosis, resulting in waste of resources.

[0005] The present invention provides a voltage stabilizer chip management system, which is applied to a server. The system includes: multiple voltage stabilizer chips; a management controller, which is used to create a first preset monitoring task and a second preset monitoring task, and upon receiving an information collection instruction, call the chip information of at least one target voltage stabilizer chip from the second preset monitoring task, and generate corresponding log information based on the chip information; a mainboard controller, which is used to respond to the first preset monitoring task and determine whether an alarm signal is generated from the multiple voltage stabilizer chips, so as to generate an information collection instruction based on the alarm signal when an alarm signal is generated, and control the server to execute a control action corresponding to the log information in response to the log information.

[0006] The present invention also provides a voltage stabilizer chip management method, comprising the following steps: generating a first preset monitoring task for monitoring the voltage stabilizer chip of the mainboard controller to detect whether multiple voltage stabilizer chips generate an alarm signal; if an alarm signal is generated, generating an information collection instruction based on the alarm signal; based on the information collection instruction, obtaining a response result of a second preset monitoring task for monitoring the voltage stabilizer chip, and obtaining log information of at least one target voltage stabilizer chip based on the response result, so as to control the server to execute a control action corresponding to the log information.

[0007] The present invention also provides an electronic device, comprising: a memory for storing a computer program; and a processor for implementing the steps of any of the above-mentioned voltage stabilizer chip management methods when executing the computer program.

[0008] The present invention also provides a computer-readable storage medium, in which a computer program is stored. When the computer program is executed by a processor, the steps of any of the above-mentioned voltage stabilizer chip management methods are implemented.

[0009] The present invention also provides a computer program product, comprising a computer program, which implements the steps of any of the above-mentioned voltage stabilizer chip management methods when executed by a processor.

[0010] Through the present invention, the voltage stabilizer chip can be monitored through the management controller. The management controller can set two monitoring tasks, one for obtaining alarm signals and locating abnormal chips, and the other for calling information based on the abnormal chip positioning to manage the voltage stabilizer chip. Through more efficient alarm signal acquisition and layered task design, the technical problems in related technologies such as rough abnormal chip positioning, delayed alarm signal acquisition, and the need for full data collection during diagnosis, resulting in waste of resources, are solved, and the technical effect of efficiently and accurately locating abnormal chips and reasonably allocating resources to optimize voltage stabilizer chip management is achieved. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] In order to more clearly illustrate the embodiments of the present invention, the following is a brief introduction to the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0012] Figure 1 A schematic diagram of the structure of a voltage stabilizer chip management system provided by an embodiment of the present invention; Figure 2 A schematic diagram showing the principle of a voltage stabilizer chip management system according to an embodiment of the present invention; Figure 3A diagram of a hardware design architecture provided according to an embodiment of the present invention; Figure 4 A hardware design architecture diagram provided according to another embodiment of the present invention; Figure 5 This is a flow chart of a voltage stabilizer chip management method provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0013] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of them. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making any creative efforts shall fall within the scope of protection of the present invention.

[0014] It should be noted that, in the description of the present invention, the terms "comprises," "includes," or any other variations thereof are intended to encompass non-exclusive inclusion, such that a process, method, article, or apparatus comprising a series of elements includes not only those elements but also other elements not explicitly listed, or elements inherent to such process, method, article, or apparatus. The terms "first," "second," etc., in the present invention are used to distinguish similar objects, and are not used to describe a particular order or precedence.

[0015] In order to enable those skilled in the art to better understand the solutions of the present invention, the present invention is further described in detail below with reference to the accompanying drawings and specific implementation methods.

[0016] As you can understand, a VR (voltage regulator) is an electronic device or circuit designed to maintain output voltage stability even when input voltage, load conditions, or ambient temperature fluctuate. Voltage regulators are widely used in various electronic devices, ensuring a stable operating voltage that is insensitive to power supply fluctuations and supplies electronic components. Many VR chips also monitor voltage, current, and power consumption. VR chips are typically used in the CPU (Central Processing Unit) and memory power supply modules on motherboards, as well as in power supply modules for boards like fan boards and hard drive backplanes. They provide stable power while also monitoring the voltage, current, and power consumption of the power supply modules. The Baseboard Management Controller (BMC) typically communicates with the VR chip via the Inter-Integrated Circuit (I2C) protocol. The BMC can read the VR chip's input and output voltages, current, and power consumption, as well as its operating status and fault codes from certain VR status registers, useful for troubleshooting power supply failures.

[0017] like Figure 1 As shown, a voltage stabilizer chip management system 10 is applied to a server, wherein the voltage stabilizer chip management system 10 includes: a plurality of voltage stabilizer chips 100 , a management controller 200 and a motherboard controller 300 .

[0018] Specifically, the management controller 200 is used to create a first preset monitoring task and a second preset monitoring task, and upon receiving an information collection instruction, call the chip information of at least one target voltage stabilizer chip 100 from the second preset monitoring task, and generate corresponding log information based on the chip information.

[0019] In practice, the BMC 200 in this embodiment of the present invention, an independent service processor based on the Intelligent Platform Management Interface specification, can create monitoring tasks. This device uses a built-in sensor network to monitor real-time hardware status data, including server power, CPU, memory, hard disk, and environmental parameters. It also supports out-of-band communication with the motherboard via the baseband management interface. It offers remote power on / off control, firmware updates, event logging, and fault diagnosis capabilities, making it widely applicable in scenarios such as data center server cluster monitoring and remote maintenance of distributed equipment.

[0020] During the actual execution process, the management controller 200 can create a motherboard controller monitoring process, that is, the first preset monitoring task of the motherboard controller to monitor the voltage stabilizer chip, so as to use the motherboard controller to monitor whether multiple voltage stabilizer chips generate alarm signals, that is, read the status data of at least one voltage stabilizer chip to determine whether the status data includes the first preset alarm signal.

[0021] The management controller 200 can determine whether it has received the information collection instruction sent by the mainboard controller 300. If it has received the information collection instruction from the first preset monitoring task, the embodiment of the present invention can read the corresponding chip information from the register of the corresponding VR chip based on the chip identifier in the information collection instruction, and then form log information based on the chip information, and return the log information to the first preset monitoring task to analyze the log information, confirm the cause of the abnormality, take corresponding control actions, curb the spread of the abnormality, facilitate timely correction of the fault, and reduce the impact of the fault on the actual process.

[0022] Optionally, in one embodiment of the present invention, the management controller 200 includes: a first connection module.

[0023] The first connection module is used to communicate with the mainboard controller 300 to read the alarm signal in the mainboard controller 300, wherein the first connection module is a preset serial bus.

[0024] The management controller 200 may communicate with the motherboard controller 300 via an I2C bus to read data of at least one voltage stabilizer chip 100 in the motherboard controller 300 .

[0025] Optionally, in one embodiment of the present invention, the management controller 200 includes: a first positioning module, a third determination module, a second positioning module and a generation module.

[0026] The first positioning module is configured to locate a chip identifier of at least one target voltage stabilizer chip 100 based on the information collection instruction.

[0027] The third determining module is configured to determine the chip model, chip label, chip parameters, bus type, bus serial number, device address, switch chip address, and switch chip channel of at least one target voltage stabilizer chip 100 based on the chip identification.

[0028] The second positioning module is used to locate at least one target voltage stabilizer chip 100 based on the chip model, chip label, chip parameters, bus type, bus serial number, device address, switch chip address and switch chip channel, so as to read corresponding chip information from the chip register of the at least one target voltage stabilizer chip 100.

[0029] A generating module is used to generate the log information based on the chip information.

[0030] Since the management controller 200 communicates with the voltage stabilizer chip 100 through the i2c bus, and there are multiple voltage stabilizer chips 100, the management controller 200 first needs to know the hardware topology of the target voltage stabilizer chip 100 before reading the register of the target voltage stabilizer chip 100 where the alarm occurs, such as the i2c bus serial number where it is located, the device address of the i2cSwitch chip, and the i2c The channel number of the switch chip and its own device address mainly include the device ID, the target voltage stabilizer chip 100 model, the label (this is the label of the target voltage stabilizer chip 100 in the circuit diagram and has no actual use in the management controller 200), parameters (including the Type / Label represented by the target voltage stabilizer chip 100 in the management controller 200, and the CPU serial number CPUIdx corresponding to the target voltage stabilizer chip 100), the bus type (the management controller 200 generally uses the I2C bus to communicate with the target voltage stabilizer chip 100), the bus serial number (the serial number of the I2C bus where the target voltage stabilizer chip 100 is located), the device address (the I2C device address of the target voltage stabilizer chip 100), the switch chip address (the address of the I2C switch chip where the target voltage stabilizer chip 100 is located), and the switch chip channel (the channel of the I2C switch chip where the voltage stabilizer chip 100 is located) to form a configuration file.

[0031] The motherboard manager 300 monitoring process, that is, the first preset monitoring task will send the device ID of the target voltage stabilizer chip 100 where the alarm occurs, and then the voltage stabilizer chip 100 monitoring process matches the target VR chip in the above file according to the device ID, and then reads the target voltage stabilizer chip 100 according to the i2c topology.

[0032] The management controller 200 mainly reads a series of status registers of the target voltage stabilizer chip 100. The register addresses range from 0x70 to 0x80. Some registers have a 1-byte reading value, and some register addresses have a 2-byte reading value. Therefore, the management controller 200 first reads the value of this register to determine whether it is 1 or 2 bytes, and then reads the register value to form a complete register log of the voltage stabilizer chip 100.

[0033] Optionally, in one embodiment of the present invention, the management controller 200 includes: a second connection module.

[0034] The second connection module is used to communicate with multiple voltage stabilizer chips 100 to detect alarm signals of the multiple voltage stabilizer chips 100 . The management controller 200 is connected to the pins of the multiple voltage stabilizer chips 100 to form the second connection module.

[0035] The management controller 200 may also directly connect the alarm pin of the voltage stabilizer chip 100 to a GPIO (General-purpose input / output) pin of the management controller 200 chip to directly read the alarm signal of the voltage stabilizer chip 100 .

[0036] Optionally, in one embodiment of the present invention, the management controller 200 includes: a setting module and an interrupt module.

[0037] The setting module is used to set the second connection module to an interruption mode.

[0038] The interruption module is used to interrupt the connection between the at least one voltage stabilizer chip 100 and the management controller 200 when the at least one voltage stabilizer chip 100 meets a preset abnormal condition, so as to determine the at least one target voltage stabilizer chip 100 and the alarm signal of the at least one target voltage stabilizer chip 100.

[0039] In other embodiments, the management controller 200 can also detect alarm conditions on the voltage stabilizer chip 100 through interrupt triggering. When the voltage stabilizer chip 100 generates an alarm, it pulls its alarm pin low, which in turn pulls the connected BMC GPIO pin low. The management controller 200 then sets the GPIO pin connected to the voltage stabilizer chip 100 alarm pin to interrupt mode, generating an interrupt immediately upon detecting the pin being pulled low. Optionally, in one embodiment of the present invention, the interruption module includes: an acquisition unit and a tracing unit.

[0040] The obtaining unit is used to obtain the identifier of the interrupt pin.

[0041] The tracing unit is configured to trace the corresponding at least one target voltage stabilizer chip 100 based on the identifier of the interrupt pin.

[0042] The management controller 200 of this embodiment of the present invention can determine which voltage stabilizer chip 100 has generated an alarm based on the correspondence between the GPIO serial number and the device ID of the voltage stabilizer chip 100. This approach eliminates the need to read the alarm status of the voltage stabilizer chip 100 from the motherboard controller 300. Furthermore, because interrupt response is relatively fast, alarms can be detected more quickly, reducing system complexity.

[0043] The mainboard controller 300 is used to respond to the first preset monitoring task and determine whether an alarm signal is generated from the multiple voltage stabilizer chips 100, so as to generate an information collection instruction based on the alarm signal when an alarm signal is generated, and to control the server to execute a control action corresponding to the log information in response to the log information.

[0044] The mainboard controller 300 may be a MB (Main Board) CPLD (Complex Programmable Logic Device). CPLD is a high-density programmable logic device with an integration density greater than 1000 gates and more input / output signals, product terms, and macro units.

[0045] Because the motherboard controller 300 only records which voltage stabilizer chip 100 (VR0-X) has triggered an alarm and cannot communicate the topology of the voltage stabilizer chip 100 to the management controller 200, the management controller 200 only receives the VR chip serial number VRX (X: 0, 1, 2, ...), which cannot be directly matched with the topology of the target voltage stabilizer chip 100 in the configuration file. Therefore, the management controller 200 needs to assign a device ID (chip identifier) ​​to each voltage stabilizer chip 100 and bind this device ID to the serial number VRX of the voltage stabilizer chip 100 recorded in the motherboard controller 300. In this embodiment of the present invention, the management controller 200 can also create a voltage stabilizer chip 100 monitoring process, namely, a second preset monitoring task for monitoring the voltage stabilizer chip. This voltage stabilizer chip 100 monitoring process can determine whether it has received an information collection instruction from the first preset monitoring task.

[0046] Optionally, in one embodiment of the present invention, the mainboard controller 300 includes: a third connection module.

[0047] The third connection module is used to communicate with multiple voltage stabilizer chips 100 to detect alarm signals of the multiple voltage stabilizer chips 100. The mainboard controller 300 is connected to the pins of the multiple voltage stabilizer chips 100 to form the third connection module.

[0048] The mainboard controller 300 and the voltage stabilizer chip 100 can be pin-connected to more quickly obtain the status or alarm information of the voltage stabilizer chip 100. The status or alarm information of the voltage stabilizer chip 100 can also be confirmed by obtaining error codes and error code mapping relationships. Through dual-mode monitoring such as time-sharing polling (presetting the power-on timing table of the voltage stabilizer chip 100 (including error code mapping), the mainboard controller 300 sequentially sends power-down instructions to the EN pin of the target voltage stabilizer chip 100) and event triggering (the mainboard controller 300 has a built-in multi-channel signal comparator that monitors the PG signals of all voltage stabilizer chips 100 in real time. Any PG jump triggers an immediate interrupt, and the location of the faulty voltage stabilizer chip 100 is locked in combination with the polling timing), embodiments of the present invention can confirm whether the voltage stabilizer chip 100 has generated an alarm based on any one result, or two or more results that are mutually verified.

[0049] Optionally, in one embodiment of the present invention, the mainboard controller 300 includes: a reading module and a first judgment module.

[0050] The reading module is configured to read the status values ​​of the abnormality registers of the plurality of voltage stabilizer chips 100 based on the third connection module.

[0051] The first judgment module is used to judge whether there is at least one byte with a value of 0 in the status value, obtain a judgment result, and determine whether to generate an alarm signal based on the judgment result.

[0052] In some embodiments, taking the pin connection between the motherboard controller 300 and the voltage stabilizer chip 100 as an example, the motherboard controller 300 can set an abnormal register of the voltage stabilizer chip to determine whether an alarm signal exists by directly reading the status value of the abnormal register.

[0053] For example, for a normal voltage stabilizer chip 100, the read value of the abnormal register is 1 byte, the total number of bytes represents the total number of voltage stabilizer chips 100, and each bit represents the status of a voltage stabilizer chip 100. If 0 appears, it means that there is a voltage stabilizer chip 100 in an abnormal state, that is, the voltage stabilizer chip 100 has an alarm or error.

[0054] In this embodiment of the present invention, the motherboard controller only needs to read the value of the exception register (one or more bytes) once and then check whether any byte is equal to 0, thereby improving detection efficiency and eliminating the complex parsing process of checking bit by bit to see whether the specific alarm type represented by each bit is set. This extremely simple judgment method can quickly confirm whether a voltage stabilizer chip 100 is in an abnormal state, which is crucial for power failure scenarios that require a quick response.

[0055] By locating the voltage stabilizer chip corresponding to the character with a value of 0 through the status value, the embodiment of the present invention can obtain the chip serial number of the target voltage stabilizer chip where the alarm occurs, and convert the chip serial number into the device ID of the chip, that is, the chip identifier, and then generate a corresponding information collection instruction through the chip identifier to perform corresponding chip information collection based on the information collection instruction.

[0056] Optionally, in one embodiment of the present invention, the mainboard controller 300 further includes: a conversion module.

[0057] The conversion module is used to convert the state value into binary to obtain a new state value, so as to determine whether there is at least one byte with a value of 0 in the new state value.

[0058] For example, if the VR_STATUS1 reading is 0xFE in hexadecimal, which is converted to binary as 1111 1110, then it means that the VR0 chip, that is, the voltage stabilizer chip 100 No. 0, has reported an error. If the VR_STATUS2 reading is 0xFE in hexadecimal, which is converted to binary as 1111 1110, then it means that the VR8 chip, that is, the voltage stabilizer chip 100 No. 8, has reported an error.

[0059] Optionally, in one embodiment of the present invention, the mainboard controller 300 includes: an acquisition module and a first determination module.

[0060] The acquisition module is used to obtain the position of the byte in the status value.

[0061] The first determining module is configured to determine at least one target voltage stabilizer chip 100 based on the position, and obtain a chip identification of the at least one target voltage stabilizer chip, so as to generate an information collection instruction based on the chip identification.

[0062] When locking the chip location, the embodiment of the present invention can confirm it through the position of the 0 character in the abnormal register.

[0063] For example, in this embodiment of the present invention, the read value of a VR fault register (exception register) on a motherboard controller 300 is 1 byte (8 bits), with each bit representing the status of a voltage stabilizer chip 100. A value of 0 indicates that the voltage stabilizer chip 100 has an alarm or error. If a machine has 12 voltage stabilizer chips 100, the motherboard controller 300 needs to use two registers as VR status registers: VR_STATUS1 register represents VR0-7, and VR_STATUS2 register represents VR8-15.

[0064] According to the positioning of the chip, the embodiment of the present application can obtain the corresponding identification of the target voltage stabilizer chip 100, such as the serial number, ID, etc., so as to write the chip identification into the information collection instruction, so that the management controller 200 can perform corresponding information call according to the chip identification.

[0065] Optionally, in one embodiment of the present invention, the mainboard controller 300 includes: a detection module, a second judgment module and a second determination module.

[0066] The detection module is used to detect the connection status of the pins in the third connection module.

[0067] The second judgment module is configured to judge whether a pin corresponding to at least one voltage stabilizer chip 100 satisfies a preset level change condition according to the pin connection status.

[0068] The second determining module is configured to determine that at least one target voltage stabilizer chip 100 issues an alarm when a preset level change condition is met.

[0069] Furthermore, in an embodiment of the present invention, the fault / alt alarm information pin of the voltage stabilizer chip 100 can be connected to a pin of the motherboard controller 300. Once an alarm or an abnormality occurs inside the voltage stabilizer chip 100, it will change the level of this pin. When the motherboard controller 300 detects that the level of the pin connected to the voltage stabilizer chip 100 has changed (for example, the default level is generally high, if the level is pulled down, it means that the voltage stabilizer chip 100 has generated an alarm signal), it means that the voltage stabilizer chip 100 has generated an alarm, and the motherboard controller 300 will then store this alarm status in the status register of its voltage stabilizer chip 100, that is, the abnormality register.

[0070] On this basis, the embodiment of the present invention can determine whether there is an alarm signal according to the status value in the abnormal register.

[0071] Optionally, in one embodiment of the present invention, the mainboard controller 300 includes: an analysis module and a control module.

[0072] The analysis module is used to analyze the log information to obtain the alarm cause of at least one target voltage stabilizer chip 100 .

[0073] The control module is configured to match a control action based on an alarm cause and cut off power supply to at least one target voltage stabilizer chip 100 .

[0074] Furthermore, the first preset monitoring task, namely the motherboard controller 300 monitoring process, can call the VR.MonitorDbus method to obtain the voltage stabilizer chip 100 register reading information str_vr_reg, which is the response result of the second preset monitoring task. It then adds a timestamp string to this string to form a voltage stabilizer chip 100 register reading log, which is stored in the vr.log file. At the same time, a sel log and diagnostic log with the same timestamp are generated. After the user knows that the sel log contains a VR alarm log, they can check the vr.log log to obtain the VR chip register information to further analyze and diagnose the cause of the alarm and match the corresponding control action based on the alarm cause.

[0075] Optionally, in one embodiment of the present invention, the voltage stabilizer chip management system 10 further includes: an actuator and a recovery controller.

[0076] The executor is configured to execute a first preset monitoring task to determine whether at least one target voltage stabilizer chip 100 generates a new alarm signal.

[0077] The recovery controller is used to restore power supply when no new alarm signal is generated.

[0078] The management controller 200 can intelligently diagnose the cause of the alarm based on the register information of the voltage stabilizer chip 100 and provide a solution, which is stored in the diagnostic log. The management controller 200 can also selectively cut off the power supply to protect the circuit based on the cause of the problem (current or power overload, etc.), and then restore power after the device is repaired and no more abnormalities such as current overload are detected.

[0079] Combine Figures 2 to 4 As shown, the working principle of the voltage stabilizer chip management method according to an embodiment of the present invention is described in detail using an embodiment.

[0080] like Figure 2 As shown, taking the BMC as the management controller 200, the MB CPLD as the motherboard controller 300, and the VR chip as the voltage stabilizer chip 100 as an example, the embodiment of the present invention may include two monitoring tasks, that is, two monitoring processes, the MB CPLD monitoring process and the VR monitoring process. Specifically, the embodiment of the present invention may include the following steps: Step S201: Create an MB CPLD monitoring process.

[0081] Step S202: Read the abnormal register. The embodiment of the present invention can communicate with the MB CPLD via the i2c bus to read the value of the abnormal register in the MB CPLD.

[0082] Step S203: Determine whether there is a VR chip alarm. The VR chip alarm pin is connected to a pin of the MB CPLD. Once an alarm or anomaly occurs within the VR chip, it changes the level of this pin. When the MB CPLD detects a level change on the VR pin (for example, the default level is usually high; if the level is pulled down, it indicates that the VR has generated an alarm signal), it indicates that the VR has generated an alarm. The MB CPLD then stores the alarm status in its VR status register.

[0083] The hardware design architecture diagram of the embodiment of the present invention can be as follows: Figure 3 shown.

[0084] Typically, an MB CPLD uses a binary bit to represent the alarm status of a VR chip. 1 represents normal operation, and 0 represents an alarm. Each MB CPLD register is 1 byte, equivalent to 8 bits. This means that one MB CPLD status register can store the status of eight VR chips. If there are more than eight VR chips, multiple VR status registers can be used. The BMC communicates with the MB CPLD over the I2C bus, polling the MB CPLD's VR fault register.

[0085] The read value of an MB CPLD's exception register is 1 byte (8 bits), with each bit representing the status of a VR. A value of 0 indicates an alarm or error for that VR. If a machine has 12 VR chips, the MB CPLD needs to use two registers as VR status registers: VR_STATUS1 for VRs 0-7 and VR_STATUS2 for VRs 8-15.

[0086] If the VR_STATUS1 reading is hexadecimal 0xFE, which is converted to binary as 1111 1110, then it means that the VR0 chip has reported an error. If the VR_STATUS2 reading is hexadecimal 0xFE, which is converted to binary as 1111 1110, then it means that the VR8 chip has reported an error.

[0087] In addition, the BMC can also connect the VR chip alarm pin directly to the GPIO pin of the BMC chip and capture the VR chip alarm status through interrupt triggering. Figure 4 As shown in the figure, when the VR chip generates an alarm, its alarm pin will be pulled low, and the GPIO pin of the BMC connected to it will of course be pulled low. The BMC sets the GPIO pin connected to the VR chip alarm pin to interrupt mode. Once it detects that it is pulled low, an interrupt will be generated immediately. Then, the BMC knows which VR chip has generated the alarm based on the correspondence between the GPIO serial number and the VR chip device ID.

[0088] Step S204: Obtain the chip ID of the target VP chip. Because the MB CPLD only records which VR chip (VR0-X) triggered the alarm and cannot communicate the VR chip topology to the BMC, the BMC only receives the VR chip serial number VRX (X: 0, 1, 2, ...), which cannot be directly matched with the VR chip topology in the YAML file. Therefore, the BMC needs to assign a device ID to each VR chip and bind this device ID to the VR chip serial number VRX recorded in the MB CPLD.

[0089] For example, the device ID COMMER_COMP_DEVID_VR_CPU0VR0 is bound to VR0, COMMER_COMP_DEVID_VR_CPU0VR1 is bound to VR1, ..., COMMER_COMP_DEVID_VR_CPU0VRx is bound to VRx.

[0090] In this way, the MB CPLD monitoring process in the BMC can read which VR has an alarm or error from the VR fault register of the MB CPLD, convert the target VR chip serial number into a device ID, and then pass the device ID as a parameter to the DBUS method.

[0091] Step S205: Generate an information acquisition instruction. Based on which VR alarm or error has occurred, the MB CPLD monitoring process in the BMC reads the VRfault register of the MB CPLD and calls the VR.Monitor Dbus service method created in the VR monitoring process in step 1. This method reads a series of VR chip status registers based on the device ID of the target VR chip passed by the MB CPLD (the device ID in the YAML file).

[0092] Step S206: Create a VR monitoring process. The BMC creates a VR chip monitoring process, which is used by the BMC to obtain VR chip information and respond to external VR chip information acquisition or VR chip control commands.

[0093] Step S207: Create a VR.Monitor DBUS service. The VR chip monitoring process creates a VR.MonitorDbus, with service = xyz.openbmc_project.VR.Monitor, path = / xyz / openbmc_project / collection, interface= xyz.openbmc_project.Collection, method=RegCollect, Its method is a function used to process and read VR register information and then pass the information out.

[0094] Step S207: Determine whether an information acquisition instruction is received.

[0095] Step S208: Read the VR chip register based on the chip ID. Since the BMC communicates with the VR chip via the I2C bus and there are multiple VR chips, the BMC must first know the hardware topology of the target VR chip before reading the register of the target VR chip where the alarm occurred, such as the I2C bus serial number of the target VR chip, the device address of the I2C switch chip, the channel number of the target VR chip, and its own device address.

[0096] For example, this information is configured in a .yaml configuration file, mainly including device ID, target VR chip model, label (this is the label of the target VR chip in the circuit diagram, which has no practical use in the BMC), parameters (including the Type / Label represented by the target VR chip in the BMC, and the CPU serial number CPUIdx corresponding to the target VR chip), bus type (BMC generally uses the i2c bus to communicate with the target VR chip), bus serial number (the serial number of the i2c bus where the target VR chip is located), device address (the i2c device address of the target VR chip), switch chip address (the address of the i2c switch chip where the target VR chip is located), and switch chip channel (the channel of the i2c switch chip where the VR chip is located).

[0097] The MB CPLD monitoring process sends the device ID of the VR chip that generates the alarm. The VR monitoring process then matches the VR chip in the YAML file based on the device ID and reads the VR chip based on the I2C topology.

[0098] Step S209: Return log information. The BMC mainly reads a series of status registers of the VR chip. The register addresses are from 0x70 to 0x80. Some registers have a 1-byte value, while others have a 2-byte value. Therefore, the BMC first reads the register value to determine whether it is 1 or 2 bytes, and then reads the register value.

[0099] For example, the 0x80 register is 2 bytes, so the BMC needs to read 2 bytes from the 0x80 register as the read value. The first byte is the lower 8 bits: 0xff, and the second byte is the upper 8 bits: 0xee, which are combined into a hexadecimal value 0xeeff, which is combined with the register address to become 0x80-0xeeff.

[0100] For example, register 0x7f is a 1-byte register with a read value of 0xdd, which is combined with the register address to form 0x7f-0xdd. Ultimately, the combined register read values ​​(str_vr_reg) are as follows: 0x70-0x00, 0x71-0x01, ..., 0x7f-0xdd, 0x80-0xeeff. The timestamp, time zone, and VR chip name in the BMC are then added to form a complete VR register log: [2025-03-17T18:12:39+08:00]PVCCIN_CPU0[0x70-0x00, 0x71-0x01, ..., 0x7f-0xdd, 0x80-0xeeff].

[0101] Step S210: Receive log information. The MB CPLD monitoring process calls the VR.Monitor Dbus method to obtain the VR register reading value information str_vr_reg, then adds a timestamp string to the front of this string to form a VR register reading value log and stores it in the vr.log file. At the same time, a sel log and a diagnostic log with the same timestamp are generated.

[0102] Step S211: Analyze log information and match control actions. After the user learns that there is a VR alarm log in the sel log, he can check the vr.log log to obtain the register information of the VR chip to further analyze and diagnose the cause of the alarm.

[0103] Furthermore, the BMC can intelligently diagnose the cause of the alarm based on VR chip register information and provide resolution suggestions, which are stored in the diagnostic log. The BMC can also selectively cut off power supply based on the cause of the problem (current or power overload, etc.) to protect the circuit. Power can then be restored once the device is repaired and no more abnormalities such as overload are detected.

[0104] In summary, the embodiments of the present invention connect the VR chip's alarm status pin to the MB CPLD. The BMC can read the MB CPLD's VR status register from the MB CPLD monitoring process to identify the VR chip that has triggered an alarm. By converting the VR chip serial number to the device ID, the BMC then obtains the VR chip's hardware topology from the VR chip hardware topology YAML file. Furthermore, a set of Dbus services is designed to implement inter-process calls, enabling the MB CPLD monitoring process (log collection process) to call the VR chip monitoring process's VR chip register collection method to obtain VR chip register logs. Furthermore, when a VR chip generates an alarm, the BMC promptly captures the alarm and triggers a Dbus method to collect the relevant VR chip register readings and generate a log. The BMC can further analyze the register readings to provide diagnostics, repair recommendations, and even cut off or reroute the power supply to prevent circuit damage.

[0105] Through the description of the above implementation methods, those skilled in the art can clearly understand that the method according to the above embodiment can be implemented by means of software plus the necessary general hardware platform, and of course it can also be implemented by hardware, but in many cases the former is a better implementation method.

[0106] like Figure 5 As shown, an embodiment of the present invention further provides a voltage stabilizer chip management method, comprising the following steps: In step S501 , a first preset monitoring task for monitoring a voltage stabilizer chip is generated for a mainboard controller to detect whether a plurality of voltage stabilizer chips generate an alarm signal.

[0107] Step S502: If an alarm signal is generated, an information collection instruction is generated based on the alarm signal.

[0108] Step S503 : Based on the information collection instruction, a response result of a second preset monitoring task for monitoring the voltage stabilizer chip is obtained, and log information of at least one target voltage stabilizer chip is obtained according to the response result, so as to control the server to execute a control action corresponding to the log information.

[0109] For descriptions of features in the embodiment corresponding to the voltage stabilizer chip management method, reference may be made to the relevant descriptions of the embodiment corresponding to the voltage stabilizer chip management system, which will not be described in detail here.

[0110] An embodiment of the present invention further provides an electronic device, including a memory and a processor, wherein the memory stores a computer program, and the processor is configured to run the computer program to perform the steps in any of the above-mentioned voltage stabilizer chip management method embodiments.

[0111] An embodiment of the present invention further provides a computer-readable storage medium storing a computer program, wherein the computer program is configured to execute the steps of any of the above-mentioned voltage stabilizer chip management method embodiments when running.

[0112] In an exemplary embodiment, the computer-readable storage medium may include, but is not limited to, various media that can store computer programs, such as a USB flash drive, a read-only memory (ROM), a random access memory (RAM), a mobile hard disk, a magnetic disk, or an optical disk.

[0113] An embodiment of the present invention further provides a computer program product, which includes a computer program. When the computer program is executed by a processor, the steps of any of the above-mentioned voltage stabilizer chip management method embodiments are implemented.

[0114] An embodiment of the present invention further provides another computer program product, including a non-volatile computer-readable storage medium, wherein the non-volatile computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the steps of any of the above-mentioned voltage stabilizer chip management method embodiments are implemented.

[0115] Professionals may further appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of the two. In order to clearly illustrate the interchangeability of hardware and software, the above description has generally described the components and steps of each example according to their functions. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professionals and technicians may use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of the present invention.

[0116] The above describes in detail the voltage stabilizer chip management system, method, electronic device, and storage medium provided by the present invention. This document uses specific examples to illustrate the principles and implementation methods of the present invention. The above examples are intended only to facilitate understanding of the method and core concepts of the present invention. It should be noted that those skilled in the art may make various improvements and modifications to the present invention without departing from the principles of the present invention, and such improvements and modifications fall within the scope of protection of the claims.

Claims

1. A voltage stabilizer chip management system, characterized in that: Applicable to servers, including: Multiple voltage stabilizer chips; a management controller, configured to create a first preset monitoring task and a second preset monitoring task, and upon receiving an information collection instruction, retrieve chip information of at least one target voltage stabilizer chip from the second preset monitoring task, and generate corresponding log information based on the chip information; A mainboard controller is configured to respond to the first preset monitoring task and determine whether an alarm signal is generated from the plurality of voltage stabilizer chips, so as to generate the information collection instruction based on the alarm signal when the alarm signal is generated, and control the server to execute a control action corresponding to the log information in response to the log information.

2. The voltage stabilizer chip management system according to claim 1, characterized in that: The management controller includes: The first connection module is used to communicate with the mainboard controller to read the alarm signal in the mainboard controller.

3. The voltage stabilizer chip management system according to claim 2, characterized in that: The first connection module is a preset serial bus.

4. The voltage stabilizer chip management system according to claim 1, characterized in that: The management controller includes: The second connection module is configured to communicate with the plurality of voltage stabilizer chips to detect alarm signals of the plurality of voltage stabilizer chips.

5. The voltage stabilizer chip management system according to claim 4, characterized in that: The management controller is connected to the plurality of voltage stabilizer chip pins to form the second connection module.

6. The voltage stabilizer chip management system according to claim 5, characterized in that: The management controller includes: A setting module, configured to set the second connection module to an interrupt mode; An interruption module is used to interrupt the connection between at least one of the voltage stabilizer chips and the management controller when at least one of the voltage stabilizer chips meets a preset abnormal condition, so as to determine at least one of the target voltage stabilizer chips and an alarm signal of at least one of the target voltage stabilizer chips.

7. The voltage stabilizer chip management system according to claim 6, characterized in that: The interrupt module includes: An acquisition unit, used to obtain the identifier of the interrupt pin; The tracing unit is configured to trace the corresponding at least one target voltage stabilizer chip based on the identifier of the interrupt pin.

8. The voltage stabilizer chip management system according to claim 1, characterized in that: The mainboard controller includes: The third connection module is configured to communicate with the plurality of voltage stabilizer chips to detect alarm signals of the plurality of voltage stabilizer chips.

9. The voltage stabilizer chip management system according to claim 8, characterized in that: The mainboard controller is connected to the plurality of voltage stabilizer chip pins to form the third connection module.

10. The voltage stabilizer chip management system according to claim 9, characterized in that: The mainboard controller includes: a reading module, configured to read, based on the third connection module, status values ​​of abnormal registers of the plurality of voltage stabilizer chips; The first judgment module is used to judge whether there is at least one byte with a value of 0 in the status value, obtain a judgment result, and determine whether to generate the alarm signal based on the judgment result.

11. The voltage stabilizer chip management system according to claim 10, characterized in that: The mainboard controller further includes: The conversion module is used to convert the state value into binary to obtain a new state value, so as to determine whether there is at least one byte with a value of 0 in the new state value.

12. The voltage stabilizer chip management system according to claim 10, characterized in that: The mainboard controller includes: An acquisition module, configured to acquire a position of the byte in the status value; The first determining module is configured to determine the at least one target voltage stabilizer chip based on the position, and obtain a chip identifier of the at least one target voltage stabilizer chip, so as to generate the information collection instruction based on the chip identifier.

13. The voltage stabilizer chip management system according to claim 9, characterized in that: The mainboard controller includes: A detection module, configured to detect a connection status of pins in the third connection module; a second judging module, configured to judge, based on the pin connection status, whether a pin corresponding to at least one of the voltage stabilizer chips satisfies a preset level change condition; The second determining module is configured to determine that at least one target voltage stabilizer chip issues an alarm when the preset level change condition is met.

14. The voltage stabilizer chip management system according to claim 1, characterized in that: The mainboard controller includes: an analysis module, configured to analyze the log information to obtain an alarm cause of at least one target voltage stabilizer chip; A control module is configured to match the control action based on the alarm cause and cut off power supply to at least one target voltage stabilizer chip.

15. The voltage stabilizer chip management system according to claim 14, characterized in that: Also includes: an executor, configured to execute the first preset monitoring task to determine whether at least one of the target voltage stabilizer chips generates a new alarm signal; The recovery controller is used to restore the power supply when the new alarm signal is not generated.

16. The voltage stabilizer chip management system according to claim 1, characterized in that: The management controller includes: a first positioning module, configured to locate a chip identifier of at least one target voltage stabilizer chip based on the information collection instruction; a third determining module, configured to determine a chip model, a chip label, chip parameters, a bus type, a bus serial number, a device address, a switch chip address, and a switch chip channel of at least one of the target voltage stabilizer chips based on the chip identifier; a second positioning module, configured to locate at least one of the target voltage stabilizer chips based on the chip model, chip label, chip parameters, bus type, bus serial number, device address, switch chip address, and switch chip channel, and read corresponding chip information from a chip register of the at least one target voltage stabilizer chip; A generating module is used to generate the log information based on the chip information.

17. A voltage stabilizer chip management method, characterized in that: The voltage stabilizer chip management system according to any one of claims 1 to 16 is used, wherein the method comprises the following steps: generating a first preset monitoring task for monitoring a voltage stabilizer chip of a mainboard controller to detect whether a plurality of voltage stabilizer chips generate an alarm signal; If the alarm signal is generated, generating an information collection instruction based on the alarm signal; Based on the information collection instruction, a response result of a second preset monitoring task of monitoring the voltage stabilizer chip is obtained, and log information of at least one target voltage stabilizer chip is obtained according to the response result to control the server to perform a control action corresponding to the log information.

18. An electronic device, characterized in that: include: Memory for storing computer programs; A processor is configured to implement the steps of the voltage stabilizer chip management method as claimed in claim 17 when executing the computer program.

19. A computer-readable storage medium, characterized in that The computer-readable storage medium stores a computer program, wherein when the computer program is executed by a processor, the steps of the voltage stabilizer chip management method according to claim 17 are implemented.

20. A computer program product comprising a computer program, characterized in that When the computer program is executed by a processor, the steps of the voltage stabilizer chip management method according to claim 17 are implemented.

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