Memory-based exclusive-or operation data processing method

Abstract

The application discloses a memory-based XNOR operation data processing method, and belongs to the technical field of computer data processing. The method comprises the following steps: obtaining two or more binary input data to be subjected to XNOR operation and preprocessing to obtain bit-level addressing data; configuring a mapping storage array pre-storing XNOR operation results according to the bit-level addressing data; generating parallel addressing signals; triggering multiple storage units in the mapping storage array to simultaneously output parallel result data based on the parallel addressing signals; and receiving the parallel result data and aggregating to obtain a final XNOR operation result. The application adopts a multi-dimensional storage unit array integrated micro logic gate to realize local XNOR operation, combines an innovative address coding scheme to optimize addressing energy consumption and data reliability, and through an efficient parallel addressing signal generation and multi-level tree network aggregation mechanism, can embed XNOR operation logic into the storage, and significantly improve the parallelism, energy efficiency ratio and operation speed of data processing.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of computer data processing, and in particular to a memory-based XNOR operation data processing method. BACKGROUND

[0002] As a basic logic operation, XNOR operation plays an important role in data verification, encryption and decryption, pattern recognition, and various parallel computing algorithms. Traditional XNOR operation mainly relies on general-purpose processors through instruction set execution or through dedicated logic gate circuits.

[0003] However, the existing XNOR operation method generally has efficiency and energy consumption problems when processing large-scale data. When performing bit-level logic operations, general-purpose processors have a memory wall effect due to the Von Neumann architecture, and frequent data transmission between the processor and the memory will cause significant delay and power consumption. At the same time, the traditional logic gate circuit implementation method has difficulty in meeting the computing needs of ultra-high parallelism, and the simple lookup table scheme fails to fully utilize the physical characteristics of the memory itself for deeper computing optimization, resulting in the inability to effectively implement ultra-high density, low-energy bit-level parallel computing when processing complex XNOR operations. SUMMARY

[0004] To solve the above problems, the present application provides a memory-based XNOR operation data processing method, which embeds XNOR operation logic into the physical structure and addressing process of a multi-dimensional memory cell array, and combines innovative address encoding schemes and parallel addressing signal generation mechanisms. The present application can realize ultra-high density, low-energy bit-level parallel XNOR operation, significantly improving the parallelism, energy efficiency ratio and operation speed of data processing.

[0005] The above object can be achieved by the following scheme:

[0006] A memory-based XNOR operation data processing method includes obtaining two or more binary input data to be subjected to XNOR operation, and preprocessing the input data to obtain corresponding bit-level addressing data; configuring a mapping storage array pre-stored with XNOR operation results according to the bit-level addressing data; generating corresponding parallel addressing signals according to the bit-level addressing data; triggering the mapping storage array based on the parallel addressing signals to make multiple storage cells in the mapping storage array output parallel result data simultaneously; receiving the parallel result data and aggregating to obtain the final XNOR operation result of the binary input data.

[0007] Optionally, the preprocessing of the input data to obtain corresponding bit-level addressing data comprises: splitting the input data into a plurality of binary sub-bit strings according to a preset bit width; and converting the plurality of binary sub-bit strings into independently addressable bit-level addressing data through an address coding scheme.

[0008] Optionally, the configuration of the mapping type storage array pre-stored with XOR operation results comprises: designing and integrating a multi-dimensional memory cell array supporting parallel addressing according to logical characteristics of the XOR operation and mapping requirements of the bit-level addressing data; traversing all possible combinations of the bit-level addressing data and calculating XOR operation results of each combination; and writing each bit-level input data combination and the corresponding XOR operation result into a corresponding memory cell address of the multi-dimensional memory cell array according to a preset mapping rule to form the mapping type storage array pre-stored with XOR operation results.

[0009] Optionally, the address coding scheme comprises: determining a coding optimization target according to numerical characteristics of each binary sub-bit string and logical association thereof in the XOR operation; and generating a non-traditional binary coding mode according to the coding optimization target, wherein the coding mode is a Gray code, a minimum Hamming distance coding, or a self-defined XOR optimization coding.

[0010] Optionally, the parallel addressing signal comprises: generating a plurality of independent addressing control signals according to the bit-level addressing data; generating corresponding timing synchronization pulses based on the addressing control signals; and combining the addressing control signals and the timing synchronization pulses to form a parallel addressing signal with efficient synchronization triggering capability.

[0011] Optionally, the multi-dimensional memory cell array comprises: designing and integrating a stacked storage layer with vertical path addressing capability to form a multi-plane parallel addressing structure; and integrating a micro logic gate into each memory cell in the multi-plane parallel addressing structure, wherein the micro logic gate is capable of performing local XOR operation based on received addressing signals and storage contents; and obtaining a parallel computing memory cell array with super-high density and low energy consumption through the vertical path addressing capability and the micro logic gate.

[0012] Optionally, the coding optimization target comprises: analyzing an addressing power consumption model based on a physical structure and an addressing path of the mapping type storage array; optimizing an address coding scheme according to the addressing power consumption model to obtain a minimum addressing energy consumption coding; evaluating crosstalk characteristics of parallel data transmission to obtain a highest data integrity transmission target; and designing an adaptive error correction coding according to the highest data integrity transmission target to improve data transmission reliability.

[0013] Optionally, the step of causing the plurality of memory cells in the mapping type memory array to output parallel result data simultaneously comprises: based on the parallel addressing signal, activating a preset parallel readout channel in the mapping type memory array to obtain a transient parallel data stream; amplifying the transient parallel data stream in parallel through a readout amplifier array integrated in the mapping type memory array to obtain a stable parallel result signal; and using the stable parallel result signal to directly carry out the XNOR operation result of the plurality of memory cells.

[0014] Optionally, the step of aggregating the final XNOR operation result of the binary input data comprises: based on the parallel result data, designing and integrating a multi-level tree network; and calculating the final XNOR operation result of the binary input data through the multi-level tree network.

[0015] Based on the same inventive concept, the application further provides a memory-based XNOR operation computing data processing system, which comprises: a data acquisition module configured to acquire two or more binary input data to be subjected to XNOR operation and to pre-process the input data to obtain corresponding bit-level addressing data; an array configuration module configured to configure a mapping type memory array pre-stored with XNOR operation results according to the bit-level addressing data; an addressing signal generation module configured to generate corresponding parallel addressing signals according to the bit-level addressing data; a data triggering module configured to trigger the plurality of memory cells in the mapping type memory array to output parallel result data simultaneously based on the parallel addressing signals and the mapping type memory array; and a result aggregation module configured to receive the parallel result data and aggregate the final XNOR operation result of the binary input data.

[0016] Compared with the prior art, the application has the following advantages:

[0017] 1. The application realizes the integration of data storage and computation by innovatively embedding the logical function of XNOR operation into the physical structure and addressing process of a multi-dimensional memory cell array. By designing a micro logic gate memory cell with local XNOR operation capability, combining an optimized address coding scheme and an efficient parallel addressing signal generation mechanism, the application can directly perform bit-level XNOR operation in parallel in the memory or near the memory, greatly reducing data transfer, thereby effectively solving the memory wall problem under the traditional architecture, greatly reducing operation delay and system power consumption.

[0018] 2、The application adopts a three-dimensional stacked structure to construct a multi-dimensional memory cell array, realizes more compact integration, and improves the calculation density. The address coding scheme not only considers the minimization of addressing energy consumption, but also improves the data transmission reliability through adaptive error correction coding, and ensures the data integrity in the parallel operation process. In the result aggregation stage, a multi-level tree network is designed and integrated to further optimize the aggregation efficiency of parallel results. These synergistic innovations enable the method and system to provide unprecedented high performance, low power consumption and high reliability when processing large-scale parallel XNOR operations, providing an efficient and stable computing foundation for data verification, encryption and decryption, and complex parallel algorithms. BRIEF DESCRIPTION OF DRAWINGS

[0019] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings needed to be used in the embodiments or the prior art description. Obviously, the drawings in the following description are some embodiments of the present application, and those skilled in the art can obtain other drawings according to these drawings without creative labor.

[0020] Figure 1 is a flowchart of a memory-based XNOR operation computing data processing method according to an embodiment of the present application.

[0021] Figure 2 is an address coding addressing flip count comparison diagram according to an embodiment of the present application.

[0022] Figure 3 is a parallel result data aggregation delay heat map according to an embodiment of the present application.

[0023] Figure 4 is a structural diagram of a memory-based XNOR operation computing data processing system according to an embodiment of the present application. DETAILED DESCRIPTION

[0024] In order to make the purpose, technical scheme and advantages of the embodiments of the present application more clear, the technical scheme in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are some embodiments of the present application, not all embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor are within the scope of protection of the present application.

[0025] With reference to Figure 1 , one embodiment of the present application proposes a memory-based XNOR operation computing data processing method. The method adopts a parallel computing mechanism of embedding XNOR operation logic into the internal memory, which can realize ultra-high density parallel XNOR operation and significantly improve the energy efficiency ratio.

[0026] The method of the embodiment specifically comprises:

[0027] Obtaining two or more binary input data to be subjected to XOR operation, and preprocessing the input data to obtain corresponding bit-level addressing data;

[0028] Specifically, a plurality of binary input data streams to be subjected to XOR operation are obtained through a data receiving interface. The data streams can be output from a high-speed parallel data bus or be numerical data blocks integrated in a high-performance computing unit. To perform efficient preprocessing, each binary input data is subjected to equal-length or non-equal-length segmentation operation according to a preset bit width, thereby forming a plurality of binary sub-bit strings. A specific address coding scheme is used to convert the binary sub-bit strings into idle addressable bit-level addressing data. The address coding scheme aims to map the numerical characteristics of each binary sub-bit string into a unique physical address offset in a mapping type storage array, so as to facilitate subsequent accurate addressing operation. Through the preprocessing process, the original binary input data is converted into suitable memory parallel addressing bit-level addressing data.

[0029] According to the bit-level addressing data, a mapping type storage array pre-storing XOR operation results is configured;

[0030] Specifically, according to the logical characteristics of the XOR operation and the mapping requirements of the bit-level addressing data, a multi-dimensional memory cell array supporting parallel addressing is designed and integrated. The array has vertical path addressing capability and stacked storage layers, thereby forming a multi-plane parallel addressing structure. When constructing the array, all possible combinations of bit-level addressing data are traversed, and the same XOR operation results of each combination are calculated. According to a preset mapping rule, each combination of bit-level addressing data and the corresponding XOR operation result is accurately written into the corresponding storage cell address in the multi-dimensional memory cell array, thereby forming a mapping type storage array pre-storing XOR operation results. Each storage cell in the array is integrated with a micro logic gate, which can perform local XOR operation based on the received addressing signal and storage content, and is constructed with a non-volatile storage element, thereby having high density and low power consumption characteristics, so as to obtain a parallel computing and storage integrated array.

[0031] According to the bit-level addressing data, corresponding parallel addressing signals are generated;

[0032] Specifically, the addressing control signal accurately corresponds to each storage cell or logical region in the multi-dimensional memory cell array that needs to be accessed in parallel. Based on the addressing control signal, a corresponding timing synchronization pulse is generated. The synchronization pulse aims to ensure the accurate alignment of each addressing path in the time dimension, so as to optimize the synchronization efficiency of parallel operation. The addressing control signal and the timing synchronization pulse are precisely combined to form a composite parallel addressing signal with efficient synchronization triggering capability, so as to drive the mapping type storage array to perform synchronous addressing and data output.

[0033] triggering the mapping type memory array based on the parallel addressing signal to make multiple memory cells in the mapping type memory array output parallel result data simultaneously;

[0034] Specifically, the generated parallel addressing signal with efficient synchronous triggering capability is precisely applied to the addressing input end of the mapping type memory array. This operation activates the preset parallel readout channel in the mapping type memory array, thereby obtaining an instantaneous parallel data stream. At the same time, the readout amplifier array integrated in the mapping type memory array amplifies the instantaneous parallel data stream in parallel to obtain a stable parallel result signal. The stable parallel result signal directly carries the exclusive-OR operation results of multiple memory cells, realizing synchronous parallel output of data. This process fully utilizes the multi-dimensional structure of the mapping type memory array and the internal micro logic gate to ensure that multiple memory cells can respond and cooperatively output data to the outside in real time after receiving the parallel addressing signal, thereby realizing efficient and synchronous parallel result data stream.

[0035] receiving the parallel result data and aggregating to obtain the final exclusive-OR operation result of the binary input data.

[0036] Specifically, the received parallel result data carries intermediate results of local exclusive-OR operations of multiple memory cells. To efficiently aggregate the intermediate results, the embodiment designs and integrates a multi-stage tree aggregation network. The multi-stage tree aggregation network uses pipeline technology to perform logical merging operations in parallel at each stage, thereby optimizing the overall timing delay and data throughput of the aggregation process. Finally, the final exclusive-OR operation result of the binary input data is obtained through the multi-stage tree aggregation network calculation, completing the data processing flow.

[0037] Optionally, the pre-processing of the input data to obtain corresponding bit-level addressing data comprises:

[0038] splitting the input data according to a preset bit width to obtain a plurality of binary sub-bit strings;

[0039] Specifically, the splitting operation accurately splits each complete binary input data according to a preset bit width specification, or flexibly splits it in a non-equal length manner, thereby obtaining a series of smaller granularity binary sub-bit strings. For example, if an input data is 128 bits wide and the preset bit width is 8 bits, it is split into 16 binary sub-bit strings of 8 bits. This splitting process ensures that the data unit granularity for subsequent processing is moderate, facilitating parallel operation.

[0040] converting the plurality of binary sub-bit strings into independently addressable bit-level addressing data through an address encoding scheme.

[0041] Specifically, the conversion utilizes a specific address encoding scheme to convert each binary sub-bit string into independently addressable bit-level addressing data. The address encoding scheme is not merely a simple binary-to-address mapping, but rather its core lies in determining an encoding optimization goal based on the numerical characteristics of each binary sub-bit string and its logical association in the XOR operation. The optimization goal can include: minimizing the number of bit flips of adjacent addressing data on the physical addresses of the mapping-type storage array, in order to reduce the energy consumption in the addressing process; or evaluating the latency differences of parallel addressing paths, aiming to maximize the synchronization efficiency between addressing paths; or measuring the durability of storage units under frequent write operations, thereby obtaining the optimal write lifespan. According to the determined encoding optimization goal, this embodiment generates a non-traditional binary encoding method. This encoding method can use Gray Code, which has the characteristic that the interval between adjacent numerical values has only one bit changing, thereby reducing the transient current change on the addressing line; it can also use Minimum Hamming Distance Code, which aims to ensure the robustness of the encoded addressing data during transmission or storage; or it can use Custom XOR Optimization Code, which is designed based on the specific logical characteristics of the XOR operation, aiming to minimize the complexity of internal logic operations of the memory. Finally, according to the generated non-traditional binary encoding method, each binary sub-bit string is accurately converted into corresponding independently addressable bit-level addressing data, as shown in Figure 2 the trend of the number of address line flips with the change of address bit width when addressing consecutive addresses.

[0042] For example, assume that the two binary input data to be XORed are and , each with a width of 4 bits. This embodiment divides and into two 2-bit binary sub-bit strings respectively, obtaining , and , . Then, in order to minimize the addressing energy consumption, this embodiment uses Gray Code as the address encoding scheme. If the binary sub-bit string is , the corresponding Gray Code addressing data is . The conversion function from to is:

[0043]

[0044] where represents the i-th bit of the Gray Code addressing data, represents the i-th bit of the binary sub-bit string, represents the exclusive OR operation. By the above Gray code encoding, there is only one bit difference between the adjacent bit-level addressing data, thereby effectively reducing the flipping power consumption of the addressing line in continuous addressing. The resulting bit-level addressing data is then sent to the mapping storage array for subsequent operations.

[0045] Optionally, the configuration obtains a mapping storage array pre-storing the exclusive OR operation results, including:

[0046] According to the logical characteristics of the exclusive OR operation and the mapping requirements of the bit-level addressing data, a multi-dimensional memory cell array supporting parallel addressing is designed and integrated;

[0047] Specifically, the multi-dimensional memory cell array is designed and integrated as a stacked storage layer with vertical path addressing capability, thereby forming a multi-plane parallel addressing structure. In this multi-plane parallel addressing structure, each memory cell is integrated with a micro logic gate, wherein the micro logic gate can perform a local exclusive OR operation based on the received addressing signal and the storage content. Through the vertical path addressing capability and the integration of the micro logic gate, the embodiment obtains a super-high-density and low-energy-consumption parallel computing memory cell array.

[0048] All possible combinations of bit-level addressing data are traversed, and the exclusive OR operation results of each combination are calculated;

[0049] Specifically, for an input composed of bit-level addressing data, the embodiment exhaustively enumerates all possible input combinations (N is the total number of bits of all bit-level addressing data). For each specific bit-level addressing data combination, the embodiment performs an accurate exclusive OR operation to calculate the unique exclusive OR operation result corresponding to the combination. For example, if the bit-level addressing data combination is its exclusive OR operation result is:

[0050]

[0051] wherein, represents the i-th bit-level addressing data, represents the exclusive OR operation result, represents the exclusive OR operation.

[0052] According to the preset mapping rule, each bit-level addressing data combination and its corresponding exclusive OR operation result are written into the corresponding memory cell address of the multi-dimensional memory cell array, forming a mapping storage array pre-storing the exclusive OR operation results.

[0053] Specifically, the mapping rule ensures that each unique bit-level addressing data combination corresponds to a specific physical storage location in the multi-dimensional memory cell array. In a write operation, the XOR operation result is pre-stored in these specific memory cells, thereby forming a mapping-type storage array of pre-stored XOR operation results.

[0054] Optionally, the address encoding scheme includes:

[0055] According to the numerical characteristics of each binary sub-bit string and its logical association in the XOR operation, an encoding optimization target is determined.

[0056] Specifically, the optimization target can include a minimum addressing energy consumption target, which is obtained by analyzing the physical structure and addressing path of the mapping-type storage array to obtain an addressing power consumption model; based on the addressing power consumption model, the address encoding scheme is optimized in this embodiment to obtain a minimum addressing energy consumption encoding. In addition, the optimization target can also cover a highest data integrity transmission target, which is obtained by evaluating the crosstalk characteristics in parallel data transmission; according to this highest data integrity transmission target, an adaptive error correction coding is designed in this embodiment to improve the reliability of data transmission.

[0057] According to the encoding optimization target, a non-traditional binary encoding method is generated, wherein the encoding method includes Gray code, minimum Hamming distance encoding or custom XOR optimization encoding.

[0058] Specifically, the encoding method can use Gray code, which is characterized by having only one bit changed between adjacent values, which helps to reduce the transient current fluctuation on the addressing line, thereby achieving the purpose of reducing the addressing energy consumption. Another optional encoding method is the minimum Hamming distance encoding, which aims to maximize the number of different bits between encoding words to enhance the robustness of encoded data during transmission or storage, so as to maintain data integrity when there is noise or interference. In addition, this embodiment can also use custom XOR optimization code, which is designed according to the specific logical characteristics of the XOR operation, aiming to minimize the complexity of internal logic operations of the memory, thereby optimizing the parallel computing efficiency. Finally, according to the selected non-traditional binary encoding method, each binary sub-bit string is accurately converted into corresponding independent addressable bit-level addressing data.

[0059] Exemplarily, if the encoding optimization target is to minimize the addressing energy consumption, this embodiment selects Gray code as the non-traditional binary encoding method. For a binary sub-bit string its corresponding Gray code addressing data The conversion function is:

[0060]

[0061] wherein, represents the i-th bit of Gray code addressing data, represents the i-th bit of binary sub-bit string, represents the XOR operation. Through this encoding method, the number of flips on the address line during the addressing process can be effectively reduced, thereby reducing power consumption.

[0062] Optionally, the parallel addressing signal comprises:

[0063] According to the bit-level addressing data, a plurality of independent addressing control signals are generated;

[0064] Specifically, if the bit-level addressing data is , , , then we will generate independent addressing control signals , , Each addressing control signal accurately corresponds to a storage unit or a logical area that needs to be accessed simultaneously in the mapping type storage array. This generation process aims to ensure the logical independence between the signals to maximize the efficiency of subsequent parallel addressing.

[0065] Based on the addressing control signals, corresponding timing synchronization pulses are generated;

[0066] Specifically, for each addressing control signal , we generate a corresponding timing synchronization pulse This synchronization pulse aims to provide a unified time reference for all parallel addressing operations. It can be realized through a high-precision clock source and a digital delay line, ensuring that each addressing control signal can be activated at the same time or within a preset microsecond-level time window when it reaches the target storage unit.

[0067] The addressing control signals and the timing synchronization pulses are combined to form a parallel addressing signal with high-efficiency synchronous triggering capability.

[0068] Specifically, this combination can be realized through a logical AND gate, i.e., the final parallel addressing signal

[0069]

[0070] wherein, represents the final parallel addressing signal, Representing logical AND operation, this combination process can be realized by logic gate circuit, so that the addressing control signal is only activated when the target storage unit is synchronized with the pulse. Through this composite addressing signal, the embodiment ensures that multiple storage units in the mapping storage array can be highly synchronized to be accessed and operated, thereby maximizing the efficiency of parallel computing and effectively avoiding data read-write conflicts or errors caused by asynchronous operation.

[0071] Optionally, the multi-dimensional memory cell array comprises:

[0072] The stacked storage layers with vertical access capability are designed and integrated to form a multi-plane parallel access structure.

[0073] Specifically, by using advanced packaging technology, multiple independent two-dimensional memory arrays are vertically stacked, and vertical interconnection technology is used to establish cross-layer data and control paths, thereby forming a multi-plane parallel access structure. This design aims to maximize storage density and provides a physical basis for simultaneous access to storage cells at different levels.

[0074] In the multi-plane parallel access structure, each storage cell is integrated with a micro-logic gate, wherein the micro-logic gate is capable of performing local XOR operation based on the received addressing signal and the stored content.

[0075] Specifically, this micro-logic gate is specially designed and optimized to perform local XOR operation directly within the storage cell based on the received addressing signal and the current stored content, without the need to move data out of the storage cell for calculation.

[0076] Through the vertical access capability and the micro-logic gate, a super-high-density and low-energy-consumption parallel computing storage cell array is obtained.

[0077] Specifically, the vertical access capability provides extremely high parallelism, allowing a large number of storage cells to be activated at the same time, and the micro-logic gate gives each storage cell the ability to perform independent calculations, thereby realizing large-scale parallel computing at the storage cell level, such as Figure 3 The heat map simulates and displays the activity distribution of the multi-dimensional memory array in the embodiment when performing local XOR operation.

[0078] Exemplarily, in a multi-dimensional array with 8 layers stacked, each layer containing 4096 memory cells, by vertical access, theoretically, all 8 memory cells at the same address on each layer can be activated simultaneously. The XNOR operation in each memory cell is performed simultaneously by the micro-logic gate, so that 8 XNOR calculations can be completed in parallel by one addressing operation. Compared with the traditional architecture which needs multiple data reading and writing and central processor calculation, the overall system energy consumption is significantly reduced, and the parallel computing capacity is improved by orders of magnitude.

[0079] Optionally, the encoding optimization target comprises:

[0080] Based on the physical structure and addressing path of the mapping type memory array, an addressing power consumption model is analyzed;

[0081] Specifically, this model describes in detail the energy consumption required for data access under different addressing schemes. For example, it can consider factors such as the charging and discharging loss of memory cells, the power consumption of driving circuits, and the signal attenuation and thermal effects of long-distance interconnection lines. By establishing an accurate mathematical model, for example, the addressing power consumption can be represented by the following formula:

[0082]

[0083] wherein, represents the number of nodes on the addressing path, is the equivalent capacitance of each node, is the power supply voltage, is the switching frequency or activity factor, is the leakage power consumption of each node.

[0084] According to the addressing power consumption model, the address encoding scheme is optimized to obtain the minimum addressing energy consumption encoding;

[0085] Specifically, according to the addressing power consumption model, the address encoding scheme is optimized to obtain the minimum addressing energy consumption encoding. This usually involves selecting an encoding method that can minimize the number of address line flips.

[0086] Exemplarily, when switching from address 0101 to address 0110, two bits (2nd and 4th bits) will be flipped in binary encoding, while using Gray code, switching from 0111 to 0101 (corresponding to binary 0101 to 0110), usually only one bit changes, thereby significantly reducing the switching power consumption in the addressing process. Through simulation and experimental verification, the address encoding strategy with the lowest power consumption under a specific hardware architecture can be found.

[0087] Evaluate the crosstalk characteristics of parallel data transmission to obtain the highest data integrity transmission target;

[0088] Specifically, in a highly parallel memory array, electromagnetic coupling between adjacent data lines can cause signal distortion, i.e. crosstalk. We quantify the crosstalk voltage and noise margin under different data transmission modes through signal integrity simulation tools. For example, when the adjacent bits on a data line change from high to low at the same time, a short voltage spike can be induced on another adjacent data line at rest, which is crosstalk. Our goal is to minimize to ensure the reliability of data transmission, wherein may be expressed as:

[0089]

[0090] wherein, is the coupling coefficient, is the mutual capacitance, is the self-capacitance of the signal line, is the signal amplitude.

[0091] According to the highest data integrity transmission target, adaptive error correction coding is designed to improve the reliability of data transmission.

[0092] Specifically, considering that noise sources such as crosstalk can cause data bit errors, error correction coding techniques such as cyclic redundancy check (CRC), Hamming code, or more advanced low-density parity-check code (LDPC) are used.

[0093] For example, if the transmitted data is 1011, it becomes 1011010 after encoding. When the receiving end receives 1001010 (where the 3rd bit is wrong), the error correction code can detect the error and automatically correct it back to 1011010 according to the encoding rule, thereby recovering the original data 1011. These encoding schemes can dynamically adjust the error correction capability according to the error rate of the actual transmission environment, ensuring that even in the presence of certain noise, the transmitted data can be accurately recovered, thereby significantly improving the robustness of data transmission.

[0094] Optionally, the method for making a plurality of memory cells in a mapping type memory array output parallel result data simultaneously comprises:

[0095] Based on the parallel addressing signal, a preset parallel readout channel in the mapping type memory array is activated to obtain a transient parallel data stream;

[0096] Specifically, based on the parallel addressing signal generated in the previous step, the embodiment activates the preset parallel readout channel in the mapped memory array, thereby obtaining a transient parallel data stream. When the parallel addressing signal reaches the mapped memory array, it synchronously selects multiple memory cells, so that the internal XOR operation results of these memory cells can be simultaneously read out to the corresponding bit lines, forming a transient parallel data stream with a width matching the parallel degree. This process ensures that all addressed memory cells can synchronously output their internal XOR operation results.

[0097] For example, if the parallel addressing signal is designed to simultaneously activate all columns in the first row, the second row and the third row of the memory array, then the internal XOR operation results of all memory cells in these three rows will be read out to the corresponding bit lines almost at the same time, forming a transient parallel data stream with a width equal to the total number of columns in the three rows. For example, if the parallel addressing signal is designed to simultaneously activate all columns in the first row, the second row and the third row of the memory array, then the internal XOR operation results of all memory cells in these three rows will be read out to the corresponding bit lines almost at the same time, forming a transient parallel data stream with a width equal to the total number of columns in the three rows.

[0098] The readout amplifier array integrated inside the mapped memory array amplifies the transient parallel data stream in parallel, obtaining a stable parallel result signal;

[0099] Specifically, the embodiment amplifies the transient parallel data stream in parallel through the readout amplifier array integrated inside the mapped memory array, obtaining a stable parallel result signal. Since the current or voltage signal output by the memory cell is usually very weak and susceptible to noise interference, in order to ensure the reliability of the signal, each parallel readout channel is connected to a dedicated readout amplifier. This readout amplifier array is tightly integrated with the memory array, and each amplifier processes the signal of one data bit in parallel, thereby converting the weak transient parallel data stream into a clear and anti-interference stable parallel result signal.

[0100] For example, each bit line is connected to a sensitive differential readout amplifier that can quickly perceive the tiny voltage change on the bit line and amplify it to a standard digital logic level, thereby converting the weak transient parallel data stream into a clear and anti-interference stable parallel result signal.

[0101] The stable parallel result signal is used to carry the XOR operation results of the plurality of memory cells.

[0102] Specifically, the stable parallel result signal is used to directly carry the XOR operation results of the plurality of memory cells. This means that the stable parallel result signal after amplification and shaping no longer needs additional processing or conversion, and it directly represents the local XOR operation results performed inside the memory cells.

[0103] For example, if the final output stable parallel result signal is a 3-bit binary number, then the stable parallel result signal directly represents the local XOR operation results of the three memory cells in the first row, the second row and the third row of the memory array. ​​parallel data (e.g. 101101), then this string of binary data is directly the The final result obtained after each of the addressed memory cells performs the XOR operation, where each bit corresponds to the output of a memory cell, can be directly used for subsequent parallel data processing or output. This direct output method greatly simplifies the data path, reduces the delay, and improves the efficiency of the entire data processing method.

[0104] Optionally, the final XOR operation result of the aggregated binary input data includes:

[0105] Based on the parallel result data, a multi-level tree network is designed and integrated;

[0106] Specifically, this tree network is composed of a series of logically gathered logic gates, aiming to efficiently perform aggregation operations on parallel result data to gradually approach the final XOR operation result. The design of the network structure will consider the balance of fan-in and fan-out, as well as the delay of signal transmission.

[0107] Through the multi-level tree network, the final XOR operation result of the binary input data is calculated.

[0108] Specifically, each logic layer in the network performs local aggregation calculation and passes the intermediate result to the next level until all parallel result data is fully integrated. This hierarchical aggregation method can effectively manage large-scale parallel data processing and avoid single-point bottlenecks.

[0109] Based on the same inventive concept, as shown in Figure 4 The application also provides a memory-based XOR operation calculation data processing system, which includes:

[0110] A data acquisition module is used to obtain two or more binary input data to be subjected to XOR operation and to pre-process the input data to obtain corresponding bit-level addressing data;

[0111] An array configuration module is used to configure a mapping-type memory array pre-stored with XOR operation results according to the bit-level addressing data;

[0112] An addressing signal generation module is used to generate corresponding parallel addressing signals according to the bit-level addressing data;

[0113] A data triggering module is used to trigger multiple memory cells in the mapping-type memory array to output parallel result data simultaneously based on the parallel addressing signals and the mapping-type memory array;

[0114] A result aggregation module is used to receive the parallel result data and aggregate the final XOR operation result of the binary input data.

[0115] It should be noted that the electrical connections between the various units described above are not necessarily direct connections, and that indirect connections are also possible in the embodiments of the present application. The above-described embodiments are merely exemplary embodiments of the present application, and should not be used in a limiting sense.

[0116] That is, any equivalent variations and modifications of the present application that follow the spirit of the present application are still within the scope of the present application. Other embodiments of the present application will be readily apparent to those skilled in the art upon considering the disclosure and the appended claims. The application is intended to cover any variations, uses, or adaptations of the application following, in general, the principles of the application and including such further uses of the application as come within the scope of the present application.

Claims

1. A memory-based XOR calculation data processing method, characterized in that: The method comprises: Obtaining two or more binary input data to be subjected to an XOR operation, and preprocessing the input data to obtain corresponding bit-level addressing data; A mapping type storage array for pre-storing the results of an exclusive-OR operation is configured based on the bit-level addressing data. The method includes: designing and integrating a multi-dimensional memory cell array supporting parallel addressing based on the logical characteristics of the exclusive-OR operation and the mapping requirements of the bit-level addressing data; traversing all possible bit-level addressing data combinations and calculating the exclusive-OR operation results of each combination; writing each bit-level input data combination and its corresponding exclusive-OR operation result into a corresponding storage cell address in the multi-dimensional memory cell array according to a preset mapping rule to form a mapping type storage array for pre-storing the exclusive-OR operation results; and generating corresponding parallel addressing signals based on the bit-level addressing data. triggering the mapping type storage array based on the parallel addressing signal, so that multiple storage units in the mapping type storage array simultaneously output parallel result data; Receiving the parallel result data and aggregating them to obtain a final XOR operation result of the binary input data; Wherein, the multi-dimensional memory cell array comprises: A stacked storage layer with vertical path addressing capability is designed and integrated to form a multi-plane parallel addressing structure. In the multi-plane parallel addressing structure, each storage unit integrates a micro logic gate, wherein the micro logic gate is capable of performing local XOR operations based on the received addressing signal and the storage content. Through the vertical path addressing capability and the micro logic gates, an ultra-high-density and low-energy parallel computing storage unit array is obtained.

2. The memory-based XOR calculation data processing method according to claim 1, characterized in that: The preprocessing of the input data to obtain corresponding bit-level addressing data includes: Splitting the input data into equal or unequal lengths according to a preset bit width to obtain a plurality of binary sub-bit strings; The plurality of binary sub-bit strings are converted into independently addressable bit-level addressing data through an address encoding scheme.

3. The memory-based XOR calculation data processing method according to claim 2, characterized in that: The address encoding scheme includes: Determine the coding optimization goal based on the numerical characteristics of each binary sub-bit string and its logical association in the XOR operation; According to the coding optimization target, a non-traditional binary coding method is generated, wherein the coding method includes Gray code, minimum Hamming distance coding or custom XOR optimization coding.

4. The memory-based XOR calculation data processing method according to claim 1, characterized in that: The parallel addressing signal includes: generating multiple independent addressing control signals according to the bit-level addressing data; Based on the addressing control signal, generating a corresponding timing synchronization pulse; The addressing control signal is combined with a timing synchronization pulse to form a parallel addressing signal with high-efficiency synchronous triggering capability.

5. The memory-based XOR calculation data processing method according to claim 3, characterized in that: The coding optimization goals include: Based on the physical structure and addressing path of the mapped storage array, the addressing power consumption model is analyzed. According to the addressing power consumption model, the address coding scheme is optimized to obtain the minimum addressing energy consumption coding; Evaluate the crosstalk characteristics of parallel data transmission to achieve the highest data integrity transmission target; Based on the highest data integrity transmission goal, adaptive error correction coding is designed to improve data transmission reliability.

6. The memory-based XOR calculation data processing method according to claim 1, characterized in that: The method of causing the plurality of storage units in the mapping type storage array to simultaneously output parallel result data comprises: Based on the parallel addressing signal, activating a preset parallel read path in the mapping type storage array to obtain an instantaneous parallel data stream; Amplifying the instantaneous parallel data stream in parallel through a sense amplifier array integrated in the mapping type memory array to obtain a stable parallel result signal; The stable parallel result signal is used to carry the XOR operation results of the multiple storage units.

7. The memory-based XOR calculation data processing method according to claim 1, characterized in that: The final XOR operation result of the binary input data obtained by aggregation includes: Based on the parallel result data, designing and integrating a multi-level tree network; The final XENOR operation result of the binary input data is calculated through the multi-level tree network.

8. A memory-based XOR calculation data processing system, applied to a memory-based XOR calculation data processing method according to any one of claims 1 to 7, characterized in that: The system comprises: A data acquisition module is used to obtain two or more binary input data to be subjected to XOR operation, and pre-process the input data to obtain corresponding bit-level addressing data; An array configuration module, configured to configure a mapping type storage array for pre-storing XOR operation results according to the bit-level addressing data; an addressing signal generating module, configured to generate a corresponding parallel addressing signal according to the bit-level addressing data; a data trigger module, configured to trigger, based on the parallel addressing signal and the mapping type storage array, a plurality of storage units in the mapping type storage array to simultaneously output parallel result data; The result aggregation module is used to receive the parallel result data and aggregate them to obtain the final XOR operation result of the binary input data.

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