Package floorplan arrangement method and system based on LEF file generation

Abstract

The invention relates to a packaging floorplan arrangement method and system based on LEF file generation. The method comprises the steps that 1, it is ensured that parameter attributes of a selected IP are matched with detail layout requirements of subsequent packaging design through IP model selection; step 2, restraining floorplan design according to PCB productization layout requirements, and ensuring that the floorplan design is consistent with a final product application scene through systematized arrangement of product forms and layout requirements; 3, collecting related design information of the chip and a third-party IP, and establishing a preliminary physical model of chip design; the related design information comprises HARD MACRO IP LEF document information; step 4, automatically processing the LEF document of the HARD MACRO IP by utilizing a Python script, and converting the LEF document into a bump map document; step 5, carrying out scheme design in Cadence APD software on the basis of the generated bump map document; step 6, performing pre-wiring and fine tuning on the main module, and performing fine tuning on the floorplan according to a result; and the main module comprises an SERDES and a DDR (Double Data Rate). The design efficiency and the scheme reliability can be improved.

Description

Technical Field

[0001] The present invention belongs to the field of chip packaging technology, and in particular relates to a packaging floorplan arrangement method and system generated based on LEF files. Background Art

[0002] With the continuous advancement of semiconductor process technology, modern chip design has an increasing demand for high performance, high density, and rapid iteration. FCBGA (Flip Chip Ball Grid Array) packaging, with its excellent signal transmission performance and compact layout structure, has become the preferred packaging format for high-end processors, graphics processing units (GPUs), and communication chips. In the FCBGA package design process, floorplan layout is a key step in connecting the chip's internal functional modules to the external package pins. Its design quality directly affects signal integrity, power distribution efficiency, and the feasibility of subsequent wiring designs.

[0003] In the traditional FCBGA package design process, floorplanning is typically performed in the early stages of chip design (e.g., at 50% or earlier). This is primarily based on the chip architecture dataflow, back-end layout and routing, and PCB product layout. Specifically, the chip architecture dataflow provides the logical relationships and signal transmission requirements between functional modules, back-end layout and routing provides preliminary constraints for physical implementation, and PCB product layout defines the external interface requirements of the package pins. Based on this information, designers roughly determine the relative positions of internal chip modules and the signal routing directions. This approach can meet initial planning needs to a certain extent, but due to the lack of detailed signal connection data, its ability to assess detailed details is very limited. For example, critical factors such as trace length, number of vias, and interaction with power planes for key high-speed modules (such as PCIe, DDR, or SerDes) are difficult to accurately analyze at this stage. These detailed assessments typically require late-stage design, after the bump netlist is obtained.

[0004] The bump netlist, mapping the connections between internal chip signals and bump pins on the package layer, is an indispensable data foundation for subsequent routing design and optimization. However, due to the phased nature of the design process, the bump netlist is typically not fully generated until the chip architecture design reaches 85% or later. This results in a significant time gap between floorplan layout and detailed analysis in the traditional process: early rough layouts based on chip architecture data flow, back-end layout and routing, and PCB product layout often reveal defects during later verification due to problems such as high-speed routing congestion, signal crosstalk, or insufficient power distribution, forcing the design team to overturn their previous work and readjust the layout. This repeated iteration not only prolongs the design cycle but also increases development costs.

[0005] To alleviate this problem, some compromise strategies are often adopted in existing technologies. For example, designers may reserve a certain amount of routing margin based on experience, or make preliminary assumptions about high-speed signal paths based on historical data. However, the accuracy and reliability of these methods are difficult to meet the high standards required for modern chip design, especially as the operating frequency and signal rate increase, the sensitivity of high-speed modules to routing constraints is further exacerbated. In addition, although some automated tools (such as EDA software) can assist in floorplan design, their functions still rely on complete input data and are difficult to function when the early data is incomplete. Therefore, in FCBGA package design, how to make up for the gaps in detailed evaluation caused by the lack of bump netlist in the early design stage and quickly generate high-quality floorplan layout solutions has become a key bottleneck in the current technological development.

[0006] In summary, the existing technology has the following technical defects:

[0007] First, existing technologies are severely lacking in their ability to assess details during the floorplan layout phase. Traditional design processes rely on chip architecture data flow, back-end layout and routing, and PCB product layout for preliminary planning. While this data can provide logical relationships between modules, physical constraints, and external interface requirements, it lacks specific connection information between signals and bump pins due to the inability to obtain bump netlists in the early stages of design. For example, questions like whether the routing path lengths of key high-speed modules (such as PCIe, DDR, or SerDes) meet timing requirements, whether the number of inter-layer switching (vias) causes signal attenuation, and whether the power plane distribution is balanced cannot be accurately analyzed at this stage. This results in floorplan solutions remaining at the rough layout level, and defects are often exposed during subsequent verification.

[0008] Secondly, time gaps in the design process lead to frequent iterations. The bump netlist, critical data for signal allocation, is typically generated when the chip design reaches 70% or later, while floorplan layout must be completed at 50% or earlier. This time mismatch makes early plans lack sufficient basis, and problems are often discovered when the bump netlist is obtained later for routing analysis. For example, high-speed signal paths may be unable to be routed due to channel congestion, or excessive crosstalk may affect signal integrity, or even insufficient power distribution may cause local voltage drops. These problems force the design team to overturn the early floorplan and readjust module positions and pinouts, significantly extending the design cycle and increasing costs.

[0009] Third, existing technologies rely too much on experience and assumptions, and accuracy is difficult to guarantee. To fill the gaps left by the bump netlist, designers often predict routing requirements based on historical data or personal experience, such as reserving additional routing channels or assuming signal path lengths. However, as chip frequencies increase (e.g., DDR5 speeds reach several Gbps), the sensitivity of high-speed signals to routing length matching, inter-layer switching, and crosstalk suppression increases significantly, and traditional empirical methods can no longer meet the requirements. For example, an inappropriate assumption may cause routing length deviations to exceed the timing window, resulting in signal distortion. The unreliability of this method is particularly evident in complex chip designs, and the error rate of the solution increases accordingly.

[0010] The root of these issues lies in the lack of a systematic approach to quickly acquire signal allocation information and perform routing analysis in the early stages of design. While traditional manual estimation or empirical assumptions can fill in the information gaps to a certain extent, their accuracy and reliability fall short of the demands of modern high-performance chip design. Therefore, efficiently and accurately generating high-quality floorplan layouts when a bumpnetlist is unavailable has become a critical technical bottleneck in FCBGA package design that needs to be addressed. Summary of the Invention

[0011] The purpose of the present invention is to provide a package floorplan arrangement method and system based on LEF file generation. By introducing a systematic data processing and analysis process in the early stage of design, the problem of insufficient detailed evaluation of floorplan arrangement due to the inability to obtain a complete bump netlist in the early stage of chip design, which in turn affects the design quality and subsequent development process, is solved, so as to improve design efficiency and solution reliability.

[0012] The present invention provides a package floorplan layout method based on LEF file generation, comprising the following steps:

[0013] Step 1: Ensure that the parameter attributes of the selected IP match the detailed layout requirements of the subsequent package design through IP selection;

[0014] Step 2: Constrain the floorplan design based on the PCB product layout requirements. By systematically organizing the product form and layout requirements, ensure that the floorplan design is consistent with the final product application scenario.

[0015] Step 3: Collect relevant design information of the chip and third-party IP and build a preliminary physical model of the chip design; the relevant design information includes die size estimation information, hard macro IP LEF document information, and back-end requirements for IP placement;

[0016] Step 4: Use Python scripts to automatically process the LEF file of the HARD MACRO IP and convert it into a bumpmap file;

[0017] Step 5: Design the solution in Cadence APD software based on the generated bump map document;

[0018] Step 6: Pre-route and fine-tune the main modules, and fine-tune the floorplan based on the results; the main modules include SERDES and DDR.

[0019] Furthermore, the key parameters involved in IP selection in step 1 include IP size, orientation, signal bump depth, and the number and type of power supplies.

[0020] Furthermore, the step 2 includes:

[0021] 1) Clarify the product form:

[0022] Clarify the half-height, half-length graphics card form factor, or other specific dimensions, including full-height, full-length dimensions, to provide boundary conditions for the external interface layout of the chip package;

[0023] 2) Determine key layout requirements:

[0024] Directly map the physical location of external interfaces to the chip's bump allocation requirements; the external interfaces include optical modules, PCIe gold fingers, DRAM memory, key power supplies, and GPIO interfaces;

[0025] 3) Mapping to floorplan requirements:

[0026] According to the PCB layout, the physical location of the external interface is converted into the signal lead-out direction and power distribution requirements of the chip's internal modules.

[0027] Furthermore, the die size estimate information in step 3 is obtained by the backend based on the evaluation of each IP block size and MFU optimization; the hard macro IP LEF document information is obtained from the IP supplier's LEF file, including the IP's physical layout information; the backend's IP placement requirements include the constraints imposed by the backend design team on IP placement;

[0028] Furthermore, the step 4 includes:

[0029] 1) The script parses the LEF file and extracts the coordinate information of the AP layer signal pins and power pins;

[0030] 2) Generate a bump map format file based on the extracted data, recording the mapping relationship between the signal and power pin bump grid of each IP.

[0031] Furthermore, the step 5 includes:

[0032] The floor plan design is carried out according to the following parameters:

[0033] Die size constraint: Set the chip boundaries based on the die size estimated in step 3;

[0034] Adjust IP orientation: Place each IP module according to the EW or NS orientation determined in step 1;

[0035] PCB product layout mapping: Combine the layout requirements in step 2 and allocate the bump area.

[0036] Furthermore, the step 6 includes:

[0037] 1) Pre-routing analysis: Test routing of signal paths for high-speed modules including SERDES and DDR in APD to evaluate trace length, number of inter-layer switching times, and crosstalk impact;

[0038] 2) Location fine-tuning: If pre-wiring finds congestion or an excessively long path, the relevant IP location is adjusted;

[0039] 3) Verification and optimization: Analyze signal and power quality through SIPI and clarify design rules.

[0040] The present invention also provides an encapsulated floorplan arrangement system generated based on the LEF file, including an encapsulated floorplan arrangement module, which executes the encapsulated floorplan arrangement method generated based on the LEF file.

[0041] The present invention also provides a non-transitory computer-readable storage medium, which stores computer instructions. When the computer instructions are executed by a processor, the encapsulated floorplan arrangement method generated based on the LEF file is implemented.

[0042] The present invention also provides an electronic device, comprising:

[0043] A memory and a processor, wherein the memory and the processor are communicatively connected to each other, the memory stores computer instructions, and the processor executes the encapsulated floorplan arrangement method generated based on the LEF file by executing the computer instructions.

[0044] The above solution, through the package floorplan layout method and system generated based on LEF files, automatically obtains the bumpmap information of the IP LEF file through a script, and combines it with stitching technology to quickly analyze the trylay of the routing of key high-speed modules. This generates a high-quality floorplan layout solution before the early stage of chip architecture design (50% progress). This ensures that the risk of subsequent design being overturned due to routing evaluation is greatly reduced, thereby improving design efficiency and package reliability. The specific technical effects include the following:

[0045] (1) Enhanced detailed evaluation: By generating a bump map through Python scripts, the routing and power distribution can be accurately evaluated in the early stages to avoid overturning in the later stages.

[0046] (2) Fewer iterations: Systematized processes and pre-wiring verification reduce late-stage design modifications and save time and costs.

[0047] (3) Higher automation: Automatically generate bump maps and optimize designs to reduce human errors.

[0048] (4) Better high-speed optimization: Pre-routing fine-tuning (such as routing <500μm) improves the performance of modules such as SERDES and DDR.

[0049] The above description is only an overview of the technical solution of the present invention. In order to more clearly understand the technical means of the present invention and implement it according to the contents of the specification, the following is a detailed description of the preferred embodiments of the present invention with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0050] Figure 1 The present invention is based on the LEF file generated package floorplan layout method;

[0051] Figure 2 PCB product layout in one embodiment of the present invention;

[0052] Figure 3 A HARD MACRO IP LEF document in one embodiment of the present invention;

[0053] Figure 4 Converting LEF to BUMP MAP in one embodiment of the present invention;

[0054] Figure 5 This is a floorplan scheme in one embodiment of the present invention;

[0055] Figure 6 The figure is a schematic structural diagram of an electronic device of the present invention. DETAILED DESCRIPTION

[0056] The following embodiments of the present invention are described in further detail with reference to the accompanying drawings and examples. The following examples are used to illustrate the present invention but are not intended to limit the scope of the present invention.

[0057] Ginseng Figures 1 to 5 As shown, this embodiment provides a package floorplan arrangement method based on LEF file generation, including the following steps:

[0058] Step S1: Ensure that the parameter attributes of the selected IP match the detailed layout requirements of the subsequent package design through IP selection.

[0059] In the initial stage of floorplan layout, the first step is to select IP (intellectual property module) to ensure that the parameter attributes of the selected IP match the detailed layout requirements of the subsequent package design. The following key parameters should be paid attention to during the selection:

[0060] IP size: Includes the length and width of the IP (e.g., in microns), which is used to determine its occupied area on the chip die.

[0061] Orientation (EW or NS): This refers to the East-West or North-South placement of the IP, which affects the planning of signal extraction and routing paths.

[0062] Signal bump depth: refers to the number of layers or distance from the internal signal pin of the IP to the external bump connection (such as 2-layer or 3-layer bump allocation), which determines the complexity of signal transmission and the wiring layer requirements.

[0063] The number and type of power supplies: including the type of power supply voltage required by the IP (such as 0.8V, 0.9V, 1.2V) and the number of pins, which affect the distribution design of the power plane.

[0064] Strictly controlling these parameters during the selection phase provides a reliable foundation for subsequent package layout, avoiding late adjustments due to mismatches between IP attributes and floorplan requirements. For example, selecting a smaller IP can optimize die space utilization, while a proper orientation can reduce signal crosstalk. Furthermore, ensure that the power supply type (e.g., 0.8V for low-power modules and 1.2V for high-speed signal modules) matches the overall chip requirements.

[0065] Step S2: Constrain the floorplan design according to the PCB product layout requirements. By systematically organizing the product form and layout requirements, ensure that the floorplan design is consistent with the final product application scenario.

[0066] After determining the IP selection, the floorplan design needs to be further constrained based on the product layout requirements of the PCB (printed circuit board). The specific steps include:

[0067] Clarify the product form: such as a half-height, half-length graphics card form factor, or other specific dimensions (such as full-height, full-length), to provide boundary conditions for the external interface layout of the chip package.

[0068] Determine key layout requirements, including the specific locations of optical modules (such as QSFP interfaces), PCIe gold fingers, DRAM memory (such as DDR5 slots), key power supplies (such as VRM modules), and GPIO interfaces. The physical locations of these components directly map to the chip's bump allocation requirements.

[0069] Mapping to floorplan requirements: Based on the PCB layout, the external interface locations are converted into signal routing and power distribution requirements for the chip's internal modules. For example, when an optical module is located near the top of the chip, the relevant high-speed signals must be preferentially distributed to the bump area above the die.

[0070] This stage ensures that the floorplan design is consistent with the final product application scenario by systematically organizing the product form and layout requirements, laying the foundation for subsequent steps.

[0071] Step S3: Collect relevant design information of the chip and third-party IP and establish a preliminary physical model of the chip design; the relevant design information includes die size estimation information, hard macro IP leaf document information, and back-end IP placement requirements.

[0072] To generate an accurate floorplan, you need to collect relevant design information about the chip and third-party IP, including:

[0073] Die size estimation: This mainly comes from the backend evaluation based on each IP block size and MFU optimization.

[0074] HARD MACRO IP LEF file: Obtain the LEF (Library Exchange Format) file from the IP vendor. This file contains the physical layout information of the IP, such as pin locations and dimensions.

[0075] Back-end requirements for IP placement: This includes constraints imposed by the back-end design team on IP placement, such as considering the proximity requirements between different IPs based on power domains.

[0076] By integrating this information, a preliminary physical model of the chip design is established to provide data support for subsequent bump map generation and module arrangement.

[0077] Step S4: Use a Python script to automatically process the LEF file of the HARD MACRO IP and convert it into a bumpmap file.

[0078] After collecting the design information, use Python scripts to automatically process the LEF file of the HARD MACRO IP and convert it into a bump map file. The specific implementation steps are as follows:

[0079] Data extraction: The script parses the LEF file and extracts the coordinate information of the AP layer signal pins and power pins.

[0080] Format conversion: Generate a bump map format file based on the extracted data, recording the mapping relationship between each IP signal and the power pin bump grid (such as coordinate format: X1, Y1 corresponds to signal A).

[0081] Step S5: Perform solution design in Cadence APD software based on the generated bump map document.

[0082] Import the generated bump map file into Cadence APD (Advanced Package Designer) software and design the floorplan according to the following parameters:

[0083] Die size constraint: Set the chip boundary based on the die size estimated in step S3.

[0084] IP orientation adjustment: Place each IP module according to the EW or NS orientation determined in step S1.

[0085] PCB product layout mapping: Based on the layout requirements of step S2, allocate the bump area (for example, if the optical module is located on the left side of the PCB, prioritize placing the optical module SERDES IP on the left, upper left, and lower left sides of the bump).

[0086] Step S6, pre-routing and fine-tuning the main modules, and fine-tuning the floorplan according to the results; the main modules include SERDES and DDR.

[0087] Perform pre-routing analysis on major modules (such as SERDES, DDR, etc.) and fine-tune the floorplan based on the results. The specific steps include:

[0088] Pre-routing analysis: Test-route the signal paths of high-speed modules such as SERDES and DDR in the APD to evaluate the trace length (e.g., less than 500 μm to meet timing), the number of inter-layer switching times (e.g., controlled within 2 times), and the impact of crosstalk.

[0089] Position fine-tuning: If congestion or excessively long paths are detected during pre-routing, the relevant IP locations can be adjusted. For example, the distance between different DDR PHYs can be increased to avoid overlapping traces.

[0090] Verification and optimization: Analyze signal and power quality through SIPI and clarify design rules.

[0091] This step verifies the feasibility of key signals through pre-wiring, avoiding the risk of overturning the plan due to routing problems later.

[0092] This invention uses automated tools and a systematic process to output a reliable package floorplan solution before the chip design is 50% complete. This solves the problem of traditional design that the bump netlist cannot be obtained in the early stages, resulting in insufficient evaluation of floorplan layout details and frequent iterations. The specific effects are as follows:

[0093] Early data generation and analysis: Automatically generate bumpmaps from the LEF file of the HARD MACRO IP through Python scripts, filling the gaps in the bump netlist missing in the early design stage and enabling rapid mapping of signal and power distribution.

[0094] Systematic design process: From IP selection (focusing on size, orientation, signal bump depth, and power supply type 0.8V / 0.9V / 1.2V), PCB product layout requirements analysis, to die size estimation (back-end based on IP block size and MFU optimization) and pre-routing fine-tuning, a complete early floorplan optimization solution is formed.

[0095] High-speed module optimization: Pre-routing analysis and fine-tuning of SERDES, DDR, and other modules are performed in Cadence APD software to ensure routing feasibility and avoid later revisions and rework.

[0096] This embodiment also provides an encapsulated floorplan arrangement system generated based on the LEF file, including an encapsulated floorplan arrangement module, which executes the encapsulated floorplan arrangement method generated based on the LEF file.

[0097] This embodiment also provides a non-transitory computer-readable storage medium, which stores computer instructions. When the computer instructions are executed by a processor, they implement the encapsulation floorplan arrangement method generated based on the LEF file.

[0098] Ginseng Figure 6 As shown, this embodiment further provides an electronic device, including:

[0099] The memory 201 and the processor 202 are communicatively connected to each other, the memory 201 stores computer instructions, and the processor 202 executes the encapsulated floorplan arrangement method generated based on the LEF file by executing the computer instructions.

[0100] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the technical principles of the present invention. These improvements and modifications should also be regarded as the scope of protection of the present invention.

Claims

1. A package floorplan layout method based on LEF file generation, characterized in that: The steps include: Step 1: Ensure that the parameter attributes of the selected IP match the detailed layout requirements of the subsequent package design through IP selection; Step 2: Constrain the floorplan design based on the PCB product layout requirements. By systematically organizing the product form and layout requirements, ensure that the floorplan design is consistent with the final product application scenario. Step 3: Collect relevant design information of the chip and third-party IP and build a preliminary physical model of the chip design; the relevant design information includes die size estimation information, hard macro IP LEF document information, and back-end requirements for IP placement; Step 4: Use Python scripts to automatically process the LEF file of the HARD MACRO IP and convert it into a bump map file; Step 5: Design the solution in Cadence APD software based on the generated bump map document; Step 6: Pre-route and fine-tune the main modules, and fine-tune the floorplan based on the results; the main modules include SERDES and DDR.

2. The package floorplan arrangement method based on LEF file generation according to claim 1, characterized in that: The key parameters involved in IP selection in step 1 include IP size, orientation, signal bump depth, and the number and type of power supplies.

3. The package floorplan arrangement method based on LEF file generation according to claim 2, characterized in that: The step 2 includes: 1) Clarify the product form: Clarify the half-height, half-length graphics card form factor, or other specific dimensions, including full-height, full-length dimensions, to provide boundary conditions for the external interface layout of the chip package; 2) Determine key layout requirements: Directly map the physical location of external interfaces to the chip's bump allocation requirements; the external interfaces include optical modules, PCIe gold fingers, DRAM memory, key power supplies, and GPIO interfaces; 3) Mapping to floorplan requirements: According to the PCB layout, the physical location of the external interface is converted into the signal lead-out direction and power distribution requirements of the chip's internal modules.

4. The package floorplan arrangement method based on LEF file generation according to claim 3 is characterized in that: The die size estimate information in step 3 comes from the backend's evaluation based on each IP block size and MFU optimization. The hard macro IP LEF document information is obtained from the IP supplier's LEF file, including the IP's physical layout information. The backend's IP placement requirements include the constraints imposed by the backend design team on IP placement.

5. The package floorplan layout method based on LEF file generation according to claim 4 is characterized in that: The step 4 comprises: 1) The script parses the LEF file and extracts the coordinate information of the AP layer signal pins and power pins; 2) Generate a bump map format file based on the extracted data, recording the mapping relationship between the signal and power pin bump grid of each IP.

6. The package floorplan layout method based on LEF file generation according to claim 5, characterized in that: The step 5 comprises: The floor plan design is carried out according to the following parameters: Die size constraint: Set the chip boundaries based on the die size estimated in step 3; Adjust IP orientation: Place each IP module according to the EW or NS orientation determined in step 1; PCB product layout mapping: Combine the layout requirements in step 2 and allocate the bump area.

7. The package floorplan layout method based on LEF file generation according to claim 6, characterized in that: The step 6 comprises: 1) Pre-routing analysis: Test routing of signal paths for high-speed modules including SERDES and DDR in APD to evaluate trace length, number of inter-layer switching times, and crosstalk impact; 2) Location fine-tuning: If pre-wiring finds congestion or an excessively long path, the relevant IP location is adjusted; 3) Verification and optimization: Analyze signal and power quality through SIPI and clarify design rules.

8. A packaged floorplan layout system generated based on LEF files, characterized in that: It includes an encapsulated floorplan arrangement module, which executes the encapsulated floorplan arrangement method generated based on the LEF file as described in any one of claims 1-7.

9. A non-transitory computer-readable storage medium, characterized in that The non-transitory computer-readable storage medium stores computer instructions, which, when executed by a processor, implement the package floorplan arrangement method generated based on the LEF file as described in any one of claims 1 to 7.

10. An electronic device, characterized in that: include: A memory and a processor, wherein the memory and the processor are communicatively connected to each other, the memory stores computer instructions, and the processor executes the encapsulated floorplan arrangement method generated based on the LEF file as described in any one of claims 1 to 7 by executing the computer instructions.

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