An on-chip integrated charge pump circuit and a boost chip suitable for automotive electronics

Abstract

The application provides an on-chip integrated charge pump circuit and a boost chip suitable for automobile electronics, wherein the charge pump circuit comprises a floating ground potential generation module, a level conversion module and a two-stage charge pump module; the floating ground potential generation module is used for sampling a voltage difference between an input voltage and an output voltage fed back by the two-stage charge pump module, comparing the voltage difference with a preset reference value, and adjusting an output floating ground potential so that the voltage difference between the output voltage and the input voltage reaches the preset reference value; the level conversion module is used for converting a clock input signal in a low voltage domain to a dynamic high voltage domain suitable for the two-stage charge pump module and outputting the clock input signal to the two-stage charge pump module; and the two-stage charge pump module charges and discharges a floating ground capacitor in the two-stage charge pump module according to the input voltage, the floating ground potential and an output signal of the level conversion module, so that the output voltage of the two-stage charge pump module is greater than the sum of the input voltage and a supply voltage of an internal control circuit.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit technology, and more specifically to an on-chip integrated charge pump circuit and a boost chip suitable for automotive electronics. Background Technology

[0002] In automotive electronics applications, boost converters are widely used, especially in motor drivers and LED driver chips or modules. The wide voltage range of batteries in automotive electronics places higher demands on the performance of boost converters. Currently, common boost converters generally fall into two categories: BOOST switching power supplies and charge pump modules. BOOST converters utilize the energy storage capacity of inductors, using their loop regulation capabilities to boost the output voltage to a set voltage higher than the input voltage. However, this type of circuit requires off-chip inductors and capacitors, and its output ripple is relatively large, with poor EMI characteristics. Charge pump circuits, on the other hand, utilize the energy storage characteristics of capacitors, transferring charge in stages to obtain an output voltage higher than the input voltage. In light-load applications, capacitors can be directly integrated on-chip, eliminating the need for additional pins or off-chip components. For applications such as LED driver chips, motor driver chips, and switching power supply chips with on-chip integrated switching transistors, charge pumps are a better choice.

[0003] like Figure 1 As shown, this is a common cross-coupled charge pump circuit with an output voltage Vcp of:

[0004] V CP = V IN +V DD - Vth - Io / (f clk * C FLY )

[0005] Where Vth is Figure 1 The threshold voltage of the PMOS transistor, Io is V. CP The output current at the terminal, f clk C is the frequency of the clock input signal CLK. FLY As capacitors, these types of charge pumps present the following problems in automotive electronics:

[0006] 1. When the input voltage V IN At very high voltages (>40V), during charge pump operation, capacitor C... FLY The withstand voltage at both ends is V IN Integrating such high-voltage capacitors on-chip would consume a lot of chip area;

[0007] 2. The output voltage is an open-loop output and does not have dynamic adjustment capability. When the output current Io changes, the output voltage will change significantly.

[0008] 3. If you need to obtain a value greater than V IN Higher output voltage (e.g., V) IN +2*VDD), then for capacitor C FLY The voltage withstand requirements are higher, making on-chip integration impossible.

[0009] Therefore, how to reduce the chip area of ​​the on-chip integrated charge pump circuit while ensuring stable output voltage is a problem that needs to be solved. Summary of the Invention

[0010] The purpose of this invention is to provide an on-chip integrated charge pump circuit and a boost chip suitable for automotive electronics, which can reduce the chip area of ​​the on-chip integrated charge pump circuit and ensure stable output voltage.

[0011] To achieve the above objectives, the present invention provides an on-chip integrated charge pump circuit, comprising:

[0012] The system includes a floating ground potential generation module, a level conversion module, and a two-stage charge pump module, wherein the two-stage charge pump module contains a floating ground capacitor.

[0013] The floating ground potential generation module is used to sample the voltage difference between the input voltage and the output voltage fed back by the two-stage charge pump module, compare the voltage difference with a preset reference value, and adjust the output floating ground potential so that the voltage difference between the output voltage and the input voltage reaches the preset reference value; the floating ground potential is less than the input voltage; the output terminal of the floating ground potential generation module is connected to the input terminal of the level conversion module and the input terminal of the two-stage charge pump module;

[0014] The level conversion module is used to convert the clock input signal in the low-voltage domain to a dynamic high-voltage domain suitable for the two-stage charge pump module, and output it to the two-stage charge pump module.

[0015] The two-stage charge pump module charges and discharges the floating ground capacitor in the two-stage charge pump module according to the input voltage, floating ground potential and the output signal of the level conversion module, so that the output voltage of the two-stage charge pump module is greater than the sum of the input voltage and the power supply voltage of the internal control circuit.

[0016] In an optional embodiment, the floating ground potential generation module includes: a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a fifth PMOS transistor, a sixth PMOS transistor, a seventh PMOS transistor, an eighth PMOS transistor, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a first high-voltage PMOS transistor, a second high-voltage PMOS transistor, a first high-voltage NMOS transistor, a first resistor, a second resistor, and a third resistor;

[0017] The gate and drain of the first PMOS transistor are connected to the gate of the second PMOS transistor and the source of the first high-voltage PMOS transistor; the drain of the second PMOS transistor is connected to the source of the second high-voltage PMOS transistor; the gate and drain of the first high-voltage PMOS transistor are connected to the gate of the second high-voltage PMOS transistor and one end of the first resistor; the other end of the first resistor is connected to the input voltage; the drain of the second high-voltage PMOS transistor is connected to the gate and drain of the second NMOS transistor; the sources of the first PMOS transistor and the sources of the second PMOS transistor are connected to the output terminal of the two-stage charge pump module.

[0018] The gate and drain of the third PMOS transistor are connected to the gate of the fourth PMOS transistor and the source of the fifth PMOS transistor; the drain of the fourth PMOS transistor is connected to the source of the sixth PMOS transistor; the gate and drain of the fifth PMOS transistor are connected to the gate of the sixth PMOS transistor and one end of the second resistor; the other end of the second resistor is grounded; the drain of the sixth PMOS transistor is connected to the drain of the first NMOS transistor and the gate of the third NMOS transistor; the gate of the first NMOS transistor is connected to the gate and drain of the second NMOS transistor; the source of the first NMOS transistor is grounded.

[0019] The gate and drain of the seventh PMOS transistor are connected to the source of the eighth PMOS transistor; the gate and drain of the eighth PMOS transistor are connected to one end of the third resistor, and the other end of the third resistor is connected to the drain of the first high-voltage NMOS transistor, and this connection serves as the output terminal of the floating ground potential generation module; the source of the first high-voltage NMOS transistor is connected to the drain of the third NMOS transistor, and the source of the third NMOS transistor is grounded;

[0020] The source of the seventh PMOS transistor is connected to the input voltage; the sources of the third PMOS transistor, the fourth PMOS transistor, and the gate of the first high-voltage NMOS transistor are all connected to the power supply voltage.

[0021] In an optional embodiment, the level conversion module includes: a ninth PMOS transistor, a tenth PMOS transistor, an eleventh PMOS transistor, a twelfth PMOS transistor, a thirteenth PMOS transistor, a fourteenth PMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor, a second high-voltage NMOS transistor, a third high-voltage NMOS transistor, a first inverter, a second inverter, and a current source;

[0022] The gate and drain of the ninth PMOS transistor are connected to the drain of the tenth PMOS transistor, the gate of the eleventh PMOS transistor, the gate of the fourteenth PMOS transistor, and the drain of the second high-voltage NMOS transistor; the gate of the tenth PMOS transistor is connected to the drain of the eleventh PMOS transistor, the gate and drain of the twelfth PMOS transistor, the gate of the thirteenth PMOS transistor, and the drain of the third high-voltage NMOS transistor; the drain of the thirteenth PMOS transistor is connected to the gate and drain of the fourth NMOS transistor and the gate of the fifth NMOS transistor; the drain of the fourteenth PMOS transistor is connected to the drain of the fifth NMOS transistor, and this connection serves as the output terminal of the level conversion module.

[0023] The sources of the fourth and fifth NMOS transistors are connected to the output terminal of the floating ground potential generation module; the sources of the ninth, tenth, eleventh, twelfth, thirteenth, and fourteenth PMOS transistors are all connected to the input voltage.

[0024] The input terminal of the first inverter is used to input a clock input signal in the low-voltage domain, and the output terminal is connected to the gate of the second high-voltage NMOS transistor and the input terminal of the second inverter. The output terminal of the second inverter is connected to the gate of the third high-voltage NMOS transistor. The source terminals of the second high-voltage NMOS transistor and the third high-voltage NMOS transistor are both connected to the current source, and the other end of the current source is grounded.

[0025] In an optional embodiment, the two-stage charge pump module includes: a fifteenth PMOS transistor, a sixteenth PMOS transistor, a seventeenth PMOS transistor, an eighteenth PMOS transistor, a sixth NMOS transistor, a seventh NMOS transistor, an eighth NMOS transistor, a ninth NMOS transistor, a first floating capacitor, a second floating capacitor, a third floating capacitor, a fourth floating capacitor, a third inverter, and a fourth inverter.

[0026] The input terminal of the third inverter is connected to the output terminal of the level conversion module. The output terminal of the third inverter is connected to the input terminal of the fourth inverter and one end of the second floating capacitor. The other end of the second floating capacitor is connected to one end of the fourth floating capacitor and the drain of the fifteenth PMOS transistor, the drain of the sixth NMOS transistor, the gate of the sixteenth PMOS transistor, and the gate of the seventh NMOS transistor.

[0027] The output terminal of the fourth inverter is connected to one end of the first floating capacitor, and the other end of the first floating capacitor is connected to one end of the third floating capacitor and the drain of the sixteenth PMOS transistor, the gate of the fifteenth PMOS transistor, the gate of the sixth NMOS transistor, and the drain of the seventh NMOS transistor.

[0028] The other end of the third floating capacitor is connected to the drain of the seventeenth PMOS transistor, the drain of the eighth NMOS transistor, the gate of the eighteenth PMOS transistor, and the gate of the ninth NMOS transistor.

[0029] The other end of the fourth floating capacitor is connected to the drain of the eighteenth PMOS transistor, the gate of the seventeenth PMOS transistor, the drain of the ninth NMOS transistor, and the gate of the eighth NMOS transistor.

[0030] The source of the fifteenth PMOS transistor is connected to the source of the eighth NMOS transistor, the source of the sixteenth PMOS transistor, and the source of the ninth NMOS transistor.

[0031] The source of the sixth NMOS transistor and the source of the seventh NMOS transistor are connected, and are connected to the input voltage and the power supply terminals of the third inverter and the fourth inverter; the ground terminals of the third inverter and the fourth inverter are used to input floating ground potential.

[0032] The source of the seventeenth PMOS transistor and the source of the eighteenth PMOS transistor are connected, and the connection point serves as the output terminal of the two-stage charge pump module.

[0033] The present invention also provides a boost chip suitable for automotive electronics, including the above-described on-chip integrated charge pump circuit.

[0034] The beneficial effects of this invention are as follows:

[0035] The on-chip integrated charge pump circuit of the present invention has the characteristics of small area, high integration and stable output voltage, and can be widely used in various chips for automotive electronic applications. Attached Figure Description

[0036] The above and other objects, features and advantages of the present invention will become more apparent from the accompanying drawings, in which like reference numerals generally denote like parts.

[0037] Figure 1 This is a charge pump circuit commonly found in existing technologies.

[0038] Figure 2 This is a schematic diagram of the overall architecture of an on-chip integrated charge pump circuit in one embodiment of the present invention.

[0039] Figure 3 This is a schematic diagram of the overall circuit of an on-chip integrated charge pump circuit in one embodiment of the present invention. Detailed Implementation

[0040] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become clearer from the following description and drawings. However, it should be noted that the concept of the technical solution of the present invention can be implemented in many different forms and is not limited to the specific embodiments described herein. The accompanying drawings are all in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of the present invention.

[0041] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this invention, the first element, component, area, layer, or portion discussed below may be referred to as the second element, component, area, layer, or portion.

[0042] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below” or “under” the other element or feature will be oriented “above” the other element or feature. Therefore, the exemplary terms “below” and “under” can include both upper and lower orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.

[0043] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the invention. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising” and / or “including,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0044] Example 1

[0045] Reference Figure 2 and Figure 3 This embodiment provides an on-chip integrated charge pump circuit, including:

[0046] The system includes a floating ground potential generation module FGND_REG, a level conversion module HV_LVLSHFT, and a two-stage charge pump module HV_CPP_2ST, wherein the two-stage charge pump module HV_CPP_2ST contains a floating ground capacitor.

[0047] The floating ground potential generation module FGND_REG is used to sample the input voltage V. IN The voltage V between the output voltage fed back by the two-stage charge pump module HV_CPP_2ST and the voltage V CP pressure difference V CP_diff and the pressure difference V CP_diff Compared with the preset reference value, adjust the output floating ground potential V. FGND The output voltage V CP and the input voltage V IN The pressure difference reaches a preset reference value; the floating ground potential V FGND Less than the input voltage V IN The output of the floating ground potential generation module FGND_REG is connected to the input of the level conversion module HV_LVLSHFT and the input of the two-stage charge pump module HV_CPP_2ST.

[0048] The level conversion module HV_LVLSHFT is used to convert the low-voltage domain clock input signal CLK to a dynamic high-voltage domain suitable for the two-stage charge pump module HV_CPP_2ST, and output it to the two-stage charge pump module HV_CPP_2ST.

[0049] The two-stage charge pump module HV_CPP_2ST is based on the input voltage and floating ground potential V. FGNDThe output signal of the level conversion module HV_LVLSHFT charges and discharges the floating capacitor in the two-stage charge pump module HV_CPP_2ST, causing the output voltage V of the two-stage charge pump module HV_CPP_2ST to be... CP Greater than the input voltage V IN and the power supply voltage V DD sum.

[0050] Specifically, in this embodiment, the floating ground potential generation module FGND_REG includes: a first PMOS transistor MP1, a second PMOS transistor MP2, a third PMOS transistor MP3, a fourth PMOS transistor MP4, a fifth PMOS transistor MP5, a sixth PMOS transistor MP6, a seventh PMOS transistor MP7, an eighth PMOS transistor MP8, a first NMOS transistor MN1, a second NMOS transistor MN2, a third NMOS transistor MN3, a first high-voltage PMOS transistor HVP1, a second high-voltage PMOS transistor HVP2, a first high-voltage NMOS transistor HVN1, a first resistor R1, a second resistor R2, and a third resistor R3; the gate and drain of the first PMOS transistor MP1 are connected to the gate of the second PMOS transistor MP2 and the source of the first high-voltage PMOS transistor HVP1; the drain of the second PMOS transistor MP2 is connected to the source of the second high-voltage PMOS transistor HVP2; the gate and drain of the first high-voltage PMOS transistor HVP1 are connected to the gate of the second high-voltage PMOS transistor HVP2 and one end of the first resistor R1; the other end of the first resistor R1 is connected to the input voltage V. INThe drain of the second high-voltage PMOS transistor HVP2 is connected to the gate and drain of the second NMOS transistor MN2; the source of the first PMOS transistor MP1 and the source of the second PMOS transistor MP2 are connected to the output terminal of the two-stage charge pump module HV_CPP_2ST; the gate and drain of the third PMOS transistor MP3 are connected to the gate of the fourth PMOS transistor MP4 and the source of the fifth PMOS transistor MP5; the drain of the fourth PMOS transistor MP4 is connected to the source of the sixth PMOS transistor MP6; the gate and drain of the fifth PMOS transistor MP5 are connected to the gate of the sixth PMOS transistor MP6 and one end of the second resistor R2; the other end of the second resistor R2 is grounded; the drain of the sixth PMOS transistor MP6 is connected to the drain of the first NMOS transistor MN1 and the gate of the third NMOS transistor MN3; the gate of the first NMOS transistor MN1 is connected to the output terminal of the second NMOS transistor MP2. The gate and drain of MOS transistor MN2; the source of the first NMOS transistor MN1 and the source of the first NMOS transistor MN1 are grounded; the gate and drain of the seventh PMOS transistor MP7 are connected to the source of the eighth PMOS transistor MP8; the gate and drain of the eighth PMOS transistor MP8 are connected to one end of the third resistor R3, and the other end of the third resistor R3 is connected to the drain of the first high-voltage NMOS transistor HVN1, and this connection serves as the output terminal of the floating ground potential generation module FGND_REG; the source of the first high-voltage NMOS transistor HVN1 is connected to the drain of the third NMOS transistor MN3, and the source of the third NMOS transistor MN3 is grounded; the source of the seventh PMOS transistor MP7 is connected to the input voltage; the sources of the third PMOS transistor MP3, the fourth PMOS transistor MP4, and the gate of the first high-voltage NMOS transistor HVN1 are all connected to the supply voltage V. DD .

[0051] In this embodiment, the level conversion module HV_LVLSHFT includes: a ninth PMOS transistor MP9, a tenth PMOS transistor MP10, an eleventh PMOS transistor MP11, a twelfth PMOS transistor MP12, a thirteenth PMOS transistor MP13, a fourteenth PMOS transistor MP14, a fourth NMOS transistor MN4, a fifth NMOS transistor MN5, a second high-voltage NMOS transistor HVN2, a third high-voltage NMOS transistor HVN3, a first inverter INV1, a second inverter INV2, and a current source IB; the gate and drain of the ninth PMOS transistor MP9 are connected to and connected to the tenth PMOS transistor MP10. The drain of the 10th PMOS transistor MP10, the gate of the 11th PMOS transistor MP11, the gate of the 14th PMOS transistor MP14, and the drain of the second high-voltage NMOS transistor HVN2; the gate of the 10th PMOS transistor MP10 is connected to the drain of the 11th PMOS transistor MP11, the gate and drain of the 12th PMOS transistor MP12, the gate of the 13th PMOS transistor MP13, and the drain of the third high-voltage NMOS transistor HVN3; the drain of the 13th PMOS transistor MP13 is connected to the gate and drain of the fourth NMOS transistor MN4 and the fifth NMOS transistor MN. The gate of the 5th PMOS transistor; the drain of the fourteenth PMOS transistor MP14 is connected to the drain of the fifth NMOS transistor MN5, and this connection serves as the output terminal of the level conversion module HV_LVLSHFT; the source of the fourth NMOS transistor MN4 and the source of the fifth NMOS transistor MN5 are connected to the output terminal of the floating ground potential generation module FGND_REG; the source of the ninth PMOS transistor MP9, the source of the tenth PMOS transistor MP10, the source of the eleventh PMOS transistor MP11, the source of the twelfth PMOS transistor MP12, and the source of the thirteenth PMOS transistor M The source of P13 and the source of the fourteenth PMOS transistor MP14 are both connected to the input voltage; the input terminal of the first inverter INV1 is used to input the low-voltage domain clock input signal CLK, and the output terminal is connected to the gate of the second high-voltage NMOS transistor HVN2 and the input terminal of the second inverter INV2; the output terminal of the second inverter INV2 is connected to the gate of the third high-voltage NMOS transistor HVN3; the source of the second high-voltage NMOS transistor HVN2 and the source of the third high-voltage NMOS transistor HVN3 are both connected to the current source IB, and the other end of the current source IB is grounded.

[0052] In this embodiment, the two-stage charge pump module HV_CPP_2ST includes: a fifteenth PMOS transistor MP15, a sixteenth PMOS transistor MP16, a seventeenth PMOS transistor MP17, an eighteenth PMOS transistor MP18, a sixth NMOS transistor MN6, a seventh NMOS transistor MN7, an eighth NMOS transistor MN8, a ninth NMOS transistor MN9, a first floating ground capacitor CFLY1, a second floating ground capacitor CFLY2, a third floating ground capacitor CFLY3, a fourth floating ground capacitor CFLY4, a third inverter INV3, and a fourth inverter INV4; the input terminal of the third inverter INV3 is connected to the output terminal of the level conversion module HV_LVLSHFT, and the third inverter... The output terminal of inverter INV3 is connected to the input terminal of the fourth inverter INV4 and one end of the second floating capacitor CFLY2. The other end of the second floating capacitor CFLY2 is connected to one end of the fourth floating capacitor CFLY4 and the drain of the fifteenth PMOS transistor MP15, the drain of the sixth NMOS transistor MN6, the gate of the sixteenth PMOS transistor MP16, and the gate of the seventh NMOS transistor MN7. The output terminal of the fourth inverter INV4 is connected to one end of the first floating capacitor CFLY1. The other end of the first floating capacitor CFLY1 is connected to one end of the third floating capacitor CFLY3 and the drain of the sixteenth PMOS transistor MP16. The gate of the fifteenth PMOS transistor MP15, the gate of the sixth NMOS transistor MN6, and the drain of the seventh NMOS transistor MN7; the other end of the third floating capacitor CFLY3 is connected to the drain of the seventeenth PMOS transistor MP17, the drain of the eighth NMOS transistor MN8, the gate of the eighteenth PMOS transistor MP18, and the gate of the ninth NMOS transistor MN9; the other end of the fourth floating capacitor CFLY4 is connected to the drain of the eighteenth PMOS transistor MP18, the gate of the seventeenth PMOS transistor MP17, the drain of the ninth NMOS transistor MN9, and the gate of the eighth NMOS transistor MN8; the fifteenth PMOS transistor MP15... The source of transistor 5 is connected to the source of the eighth NMOS transistor MN8, the source of the sixteenth PMOS transistor MP16, and the source of the ninth NMOS transistor MN9; the source of the sixth NMOS transistor MN6 and the source of the seventh NMOS transistor MN7 are connected, and connected to the input voltage and the power supply terminals of the third inverter INV3 and the fourth inverter INV4; the ground terminals of the third inverter INV3 and the fourth inverter INV4 are used to input floating ground potential; the source of the seventeenth PMOS transistor MP17 and the source of the eighteenth PMOS transistor MP18 are connected, and the connection point serves as the output terminal of the two-stage charge pump module HV_CPP_2ST.

[0053] Input voltage V INThis is a high-voltage input voltage, typically connected directly to the battery in automotive electronics applications. The power supply voltage V for the internal control circuit... DD Typically 5V, the input voltage V during normal operation IN For a voltage higher than the supply voltage V DD High pressure. Figure 2 In this context, the purpose of the floating ground potential generation module FGND_REG is to generate the floating ground potential V. FGND To enable the two-stage charge pump module HV_CPP_2ST to use 5V devices and charge / discharge capacitors, the floating ground potential V FGND Typically, it is higher than the input voltage V. IN The voltage is approximately 4V lower. In this design, it can be dynamically adjusted to make the output voltage V of the subsequent stage... CP The output reaches a stable value. The high-voltage domain two-stage charge pump module HV_CPP_2ST, through the input voltage V... IN and floating ground potential V FGND The charging and discharging of the floating capacitor between the two sources results in an output voltage V. CP Output greater than V IN +V DD The module HV_LVLSFT is a level conversion module whose function is to convert the low-voltage domain clock input signal CLK to V. IN -FGND's dynamic high-voltage domain is designed to meet the charging and discharging requirements of the high-voltage domain two-stage charge pump module HV_CPP_2ST.

[0054] like Figure 3 As shown, the floating ground potential generation module FGND_REG samples the input voltage V through the first PMOS transistor MP1, the second PMOS transistor MP2, the first high-voltage PMOS transistor HVP1, the second high-voltage PMOS transistor HVP2, and the first resistor R1. IN and output voltage V CP Pressure difference V between CP_diff The output floating ground potential V is adjusted by comparing the mirror images of the second NMOS transistor MN2 and the first NMOS transistor MN1 with a preset reference value, and by using the negative feedback of the third NMOS transistor MN3. FGND The voltage, thus causing the output voltage V CP and input voltage V IN The pressure difference reaches the preset reference value. In this scheme, due to the requirements of the two-stage charge pump module in the later stage, R1 = 2 × R2 is taken. When the pressure difference V CP_diff =V CP -V IN When the current decreases, the current on the first NMOS transistor MN1 decreases, therefore the voltage at the REG_G node (at the gate of the third NMOS transistor MN3) increases, and the current in the third NMOS transistor MN3 increases, resulting in an increase in the input voltage V. IN With floating ground potential V FGNDThe pressure difference increases, thus causing the pressure difference V CP_diff Increase; similarly, when the pressure difference V CP_diff =V CP -V IN When the current increases, the current through the first NMOS transistor MN1 increases, therefore the voltage at the REG_G node decreases, the current through the third NMOS transistor MN3 decreases, and the input voltage V... IN With floating ground potential V FGND The pressure difference decreases, thus reducing the pressure difference V. CP_diff It gets smaller.

[0055] The function of the level conversion circuit HV_LVLSHFT is to convert V DD The high-frequency clock signal CLK in the voltage domain is converted into the input voltage V. IN With floating ground potential V FGND The high-voltage domain high-frequency clock signal between the voltage rails is output to the two-stage charge pump module HV_CPP_2ST for use.

[0056] The two-stage charge pump module HV_CPP_2ST is a high-voltage domain two-stage charge pump circuit, whose function is to convert the input voltage V... IN With floating ground potential V FGND The pressure difference is amplified by two times and the energy is transferred through a charge pump, converting it into an output voltage V. CP With input voltage V IN The pressure difference, V CP_diff = V CP -V IN =2×(V IN -V FGND Considering the negative feedback modulation of the floating ground potential generation module FGND_REG, when R1=2×R2, the output voltage V CP Output and input voltage V IN The difference is: V CP_diff =2×V DD -2×V GSP Furthermore, this voltage is adjusted dynamically by the negative feedback of the floating ground potential generation module FGND_REG, and is not affected by the output current Iload. GSP The gate-source voltage difference is the first PMOS transistor MP1, the third PMOS transistor MP3, the fifth PMOS transistor MP5, and the first high-voltage PMOS transistor HVP1.

[0057] The on-chip integrated charge pump circuit proposed in this invention has the following advantages:

[0058] 1. High integration; the module area required to achieve the same performance is smaller than that of traditional charge pumps. Figure 3In this configuration, only HVP1, HVP2, HVN1, HVN2, and HVN3 are high-voltage devices (with a withstand voltage > 40V), while the other NMOS and PMOS transistors are 5V withstand devices, reducing the area of ​​the active devices. Furthermore, the charge pump's charge / discharge floating capacitor C... FLY1 C FLY2 C FLY3 C FLY4 The withstand voltage during operation is V. CFLY =V IN -V FGND This voltage is below 5V, therefore C FLY1 C FLY2 C FLY3 C FLY4 Lower voltage capacitors with higher unit capacitance can be used, further reducing the module area.

[0059] 2. The negative feedback loop stabilizes the output voltage of the charge pump, improving the current output capability while avoiding excessive output voltage variations under different load conditions.

[0060] 3. Through a two-stage or multi-stage charge pump circuit (if multi-stage, repeat the units consisting of MN8, MN9, MP17, MP18, CFLY3, and CFLY4), this architecture can achieve a higher V IN Higher output voltage (e.g., V) IN +2*V DD Furthermore, the voltage withstand capability of the floating capacitor does not increase with higher voltage, making it easy to achieve low-cost on-chip integration.

[0061] The on-chip integrated charge pump circuit proposed in this embodiment, suitable for automotive electronic applications, features small area, high integration, and stable output voltage. This charge pump circuit can be widely used in various chips for automotive electronic applications, such as LED driver chips, motor driver chips, and switching power supply chips.

[0062] The above description is merely a description of preferred embodiments of the present invention and is not intended to limit the scope of the present invention in any way. Any changes or modifications made by those skilled in the art based on the above disclosure shall fall within the protection scope of the claims.

Claims

1. An on-chip integrated charge pump circuit, characterized in that, include: The system includes a floating ground potential generation module, a level conversion module, and a two-stage charge pump module, wherein the two-stage charge pump module contains a floating ground capacitor. The floating ground potential generation module is used to sample the voltage difference between the input voltage and the output voltage fed back by the two-stage charge pump module, compare the voltage difference with a preset reference value, and adjust the output floating ground potential so that the voltage difference between the output voltage and the input voltage reaches the preset reference value; the floating ground potential is less than the input voltage; the output terminal of the floating ground potential generation module is connected to the input terminal of the level conversion module and the input terminal of the two-stage charge pump module; The level conversion module is used to convert the clock input signal in the low-voltage domain to a dynamic high-voltage domain suitable for the two-stage charge pump module, and output it to the two-stage charge pump module. The two-stage charge pump module charges and discharges the floating ground capacitor in the two-stage charge pump module according to the input voltage, floating ground potential and the output signal of the level conversion module, so that the output voltage of the two-stage charge pump module is greater than the sum of the input voltage and the power supply voltage of the internal control circuit.

2. The on-chip integrated charge pump circuit as described in claim 1, characterized in that, The floating ground potential generation module includes: a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a fifth PMOS transistor, a sixth PMOS transistor, a seventh PMOS transistor, an eighth PMOS transistor, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a first high-voltage PMOS transistor, a second high-voltage PMOS transistor, a first high-voltage NMOS transistor, a first resistor, a second resistor, and a third resistor; The gate and drain of the first PMOS transistor are connected to the gate of the second PMOS transistor and the source of the first high-voltage PMOS transistor; the drain of the second PMOS transistor is connected to the source of the second high-voltage PMOS transistor; the gate and drain of the first high-voltage PMOS transistor are connected to the gate of the second high-voltage PMOS transistor and one end of the first resistor; the other end of the first resistor is connected to the input voltage; the drain of the second high-voltage PMOS transistor is connected to the gate and drain of the second NMOS transistor; the sources of the first PMOS transistor and the sources of the second PMOS transistor are connected to the output terminal of the two-stage charge pump module. The gate and drain of the third PMOS transistor are connected to the gate of the fourth PMOS transistor and the source of the fifth PMOS transistor; the drain of the fourth PMOS transistor is connected to the source of the sixth PMOS transistor; the gate and drain of the fifth PMOS transistor are connected to the gate of the sixth PMOS transistor and one end of the second resistor; the other end of the second resistor is grounded; the drain of the sixth PMOS transistor is connected to the drain of the first NMOS transistor and the gate of the third NMOS transistor; the gate of the first NMOS transistor is connected to the gate and drain of the second NMOS transistor; the source of the first NMOS transistor and the source of the second NMOS transistor are grounded; The gate and drain of the seventh PMOS transistor are connected to the source of the eighth PMOS transistor; the gate and drain of the eighth PMOS transistor are connected to one end of the third resistor, and the other end of the third resistor is connected to the drain of the first high-voltage NMOS transistor, and this connection serves as the output terminal of the floating ground potential generation module; the source of the first high-voltage NMOS transistor is connected to the drain of the third NMOS transistor, and the source of the third NMOS transistor is grounded; The source of the seventh PMOS transistor is connected to the input voltage; the sources of the third PMOS transistor, the fourth PMOS transistor, and the gate of the first high-voltage NMOS transistor are all connected to the power supply voltage.

3. The on-chip integrated charge pump circuit as described in claim 1, characterized in that, The level conversion module includes: a ninth PMOS transistor, a tenth PMOS transistor, an eleventh PMOS transistor, a twelfth PMOS transistor, a thirteenth PMOS transistor, a fourteenth PMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor, a second high-voltage NMOS transistor, a third high-voltage NMOS transistor, a first inverter, a second inverter, and a current source; The gate and drain of the ninth PMOS transistor are connected to the drain of the tenth PMOS transistor, the gate of the eleventh PMOS transistor, the gate of the fourteenth PMOS transistor, and the drain of the second high-voltage NMOS transistor; the gate of the tenth PMOS transistor is connected to the drain of the eleventh PMOS transistor, the gate and drain of the twelfth PMOS transistor, the gate of the thirteenth PMOS transistor, and the drain of the third high-voltage NMOS transistor; the drain of the thirteenth PMOS transistor is connected to the gate and drain of the fourth NMOS transistor and the gate of the fifth NMOS transistor; the drain of the fourteenth PMOS transistor is connected to the drain of the fifth NMOS transistor, and this connection serves as the output terminal of the level conversion module. The sources of the fourth and fifth NMOS transistors are connected to the output terminal of the floating ground potential generation module; the sources of the ninth, tenth, eleventh, twelfth, thirteenth, and fourteenth PMOS transistors are all connected to the input voltage. The input terminal of the first inverter is used to input a clock input signal in the low-voltage domain, and the output terminal is connected to the gate of the second high-voltage NMOS transistor and the input terminal of the second inverter. The output terminal of the second inverter is connected to the gate of the third high-voltage NMOS transistor. The source terminals of the second high-voltage NMOS transistor and the third high-voltage NMOS transistor are both connected to the current source, and the other end of the current source is grounded.

4. The on-chip integrated charge pump circuit as described in claim 1, characterized in that, The two-stage charge pump module includes: a fifteenth PMOS transistor, a sixteenth PMOS transistor, a seventeenth PMOS transistor, an eighteenth PMOS transistor, a sixth NMOS transistor, a seventh NMOS transistor, an eighth NMOS transistor, a ninth NMOS transistor, a first floating capacitor, a second floating capacitor, a third floating capacitor, a fourth floating capacitor, a third inverter, and a fourth inverter. The input terminal of the third inverter is connected to the output terminal of the level conversion module. The output terminal of the third inverter is connected to the input terminal of the fourth inverter and one end of the second floating capacitor. The other end of the second floating capacitor is connected to one end of the fourth floating capacitor and the drain of the fifteenth PMOS transistor, the drain of the sixth NMOS transistor, the gate of the sixteenth PMOS transistor, and the gate of the seventh NMOS transistor. The output terminal of the fourth inverter is connected to one end of the first floating capacitor, and the other end of the first floating capacitor is connected to one end of the third floating capacitor and the drain of the sixteenth PMOS transistor, the gate of the fifteenth PMOS transistor, the gate of the sixth NMOS transistor, and the drain of the seventh NMOS transistor. The other end of the third floating capacitor is connected to the drain of the seventeenth PMOS transistor, the drain of the eighth NMOS transistor, the gate of the eighteenth PMOS transistor, and the gate of the ninth NMOS transistor. The other end of the fourth floating capacitor is connected to the drain of the eighteenth PMOS transistor, the gate of the seventeenth PMOS transistor, the drain of the ninth NMOS transistor, and the gate of the eighth NMOS transistor. The source of the fifteenth PMOS transistor is connected to the source of the eighth NMOS transistor, the source of the sixteenth PMOS transistor, and the source of the ninth NMOS transistor. The source of the sixth NMOS transistor and the source of the seventh NMOS transistor are connected, and are connected to the input voltage and the power supply terminals of the third inverter and the fourth inverter; the ground terminals of the third inverter and the fourth inverter are used to input floating ground potential. The source of the seventeenth PMOS transistor and the source of the eighteenth PMOS transistor are connected, and the connection point serves as the output terminal of the two-stage charge pump module.

5. A boost converter chip suitable for automotive electronics, characterized in that, Includes the on-chip integrated charge pump circuit as described in any one of claims 1-4.

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