Chip layout planning rule inspection method, device, equipment and medium

Abstract

The invention discloses a rule checking method and device for chip layout planning, equipment and a medium, and relates to the technical field of integrated circuits. The method comprises the following steps: analyzing a design rule constraint file of a target manufacturing process to extract a rule parameter set; according to the rule parameter set, generating different inspection rules used for performing rule inspection on the chip subjected to layout planning, and according to the inspection rules, constructing a corresponding inspection script; and performing rule inspection on the chip by utilizing the inspection script to output problem items which do not meet the inspection rule, and repairing the problem items to obtain a target chip which conforms to the design rule constraint file. According to the technical scheme, after the layout planning is completed, the corresponding check script is compiled for checking and repairing, the efficiency is improved, and the time period of subsequent iteration is shortened.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuit technology, and in particular to a chip layout planning rule checking method, device, equipment and medium. Background Art

[0002] In chip physical design, floorplanning and layout play a crucial role. The success of a chip design is inextricably linked to it, and a sound floorplan directly determines the smooth progress of subsequent design work. The floorplan determines the chip's available area, routing space, and inter-module communication distances, which in turn impacts chip performance, yield, and reliability. Therefore, whether the floorplan is manually generated or generated using EDA (Electronic Design Automation) tools, it's crucial to perform rule checks after completion to avoid a series of issues later on. For example, the spacing between memory cells could be too large or too small, resulting in wasted resources or routing congestion. Alternatively, design rule checks and advanced process checks could reveal numerous violations, failing to meet the manufacturing requirements of the foundry (the manufacturer responsible for chip production). Returning to the floorplan to correct these issues would be time-consuming.

[0003] Therefore, under advanced technology, it is necessary to check and repair the layout of the chip, whether it is completed manually or using EDA tools. Summary of the Invention

[0004] In view of this, the present invention aims to provide a chip floorplanning rule checking method, apparatus, device, and medium. These methods can take into account wiring resources, space utilization, and foundry manufacturing requirements, and can inspect and repair finished floorplanned chips to avoid later problems that would otherwise waste time and effort, thereby improving efficiency. The specific solution is as follows:

[0005] In a first aspect, the present application discloses a chip layout planning rule checking method, comprising:

[0006] Parsing the design rule constraint file of the target manufacturing process to extract the rule parameter set;

[0007] Generating different checking rules for checking the layout-planned chip based on the rule parameter set, and constructing corresponding checking scripts based on the checking rules;

[0008] The chip is checked for rules using a check script to output problem items that do not meet the check rules, and the problem items are repaired to obtain a target chip that complies with the design rule constraint file.

[0009] Optionally, parse the design rule constraint file for the target manufacturing process to extract the rule parameter set, including:

[0010] Parse the design rule constraint file of the target manufacturing process to extract geometric constraints, positional constraints, and structural constraints. Geometric constraints are used to define the boundary dimensions of functional modules, positional constraints are used to define the spacing between functional modules and chip boundaries, and the spacing between functional modules. Structural constraints are used to define the orientation of functional modules and the arrangement between functional modules.

[0011] Optionally, different check rules for performing rule checking on a chip for which layout planning has been completed are generated based on the rule parameter set, including:

[0012] generating a first checking rule for performing a rule check on a chip for which layout planning has been completed according to the geometric constraint;

[0013] The process of generating the first inspection rule includes:

[0014] The width and height of the chip are required to meet a first threshold standard;

[0015] Based on the target manufacturing process, a corresponding semiconductor device manufacturing technology is selected, and based on the semiconductor device manufacturing technology, it is stipulated that the components in the chip are aligned on the manufacturing grid.

[0016] Optionally, different check rules for performing rule checking on a chip for which layout planning has been completed are generated based on the rule parameter set, including:

[0017] generating a second checking rule for performing a rule check on a chip for which layout planning has been completed according to the position constraint;

[0018] The process of generating the second inspection rule includes:

[0019] It is stipulated that a first horizontal distance and a first vertical distance between the functional module and the chip boundary meet a second threshold standard;

[0020] The distance between the width and height of the memory cell of the chip and the boundary cell of the chip is required to meet a third threshold standard;

[0021] The second horizontal direction spacing and the second vertical direction spacing between the memory cells are required to meet a fourth threshold standard, and based on semiconductor device manufacturing technology, the memory cells are required to be aligned on a manufacturing grid.

[0022] Optionally, stipulating that the second horizontal spacing and the second vertical spacing between the memory cells meet a fourth threshold criterion includes:

[0023] Determining a first size of the boundary unit and a second size of the well connection unit;

[0024] Determine a first winding space according to the width and minimum spacing of the horizontal metal routing layer, and determine a second winding space according to the width and minimum spacing of the vertical metal routing layer;

[0025] Determine a threshold value corresponding to a second horizontal spacing between memory cells based on the first size, the second size, and the size of the first winding space;

[0026] A threshold value corresponding to a second vertical spacing between the memory cells is determined based on the first size and the size of the second winding space.

[0027] Optionally, different check rules for performing rule checking on a chip for which layout planning has been completed are generated based on the rule parameter set, including:

[0028] generating a third checking rule for performing a rule check on a chip for which layout planning has been completed according to the structural constraint;

[0029] The generation process of the third inspection rule includes:

[0030] The arrangement direction of the memory cells is specified according to the arrangement direction of the standard cells in the chip;

[0031] Check the horizontal and vertical offset of the memory cells and specify the alignment of the memory cells based on the offset.

[0032] Optionally, build a corresponding check script based on the check rules, including:

[0033] Converting the inspection rules into discrete command scripts that can be recognized by a preset electronic design automation tool, and encapsulating the discrete command scripts to obtain inspection scripts;

[0034] Accordingly, the chip is checked using a check script to output problem items that do not meet the check rules, and the problem items are repaired to obtain a target chip that complies with the design rule constraint file, including:

[0035] Calling a preset electronic design automation tool to execute a check script, performing rule check on the chip, and outputting problem items that do not meet the check rules;

[0036] Repairing the problem item using a preset electronic design automation tool, and / or obtaining input adjustment parameters based on a human-computer interaction interface, and repairing the problem item using the adjustment parameters;

[0037] When the problem item is repaired, the step of calling the preset electronic design automation tool to execute the inspection script is triggered again. If there is no problem item that does not meet the inspection rules, it is determined that the chip complies with the design rule constraint file and the target chip is obtained.

[0038] In a second aspect, the present application discloses a chip layout planning rule checking device, comprising:

[0039] A file parsing module, used to parse the design rule constraint file of the target manufacturing process to extract a set of rule parameters;

[0040] A script construction module is used to generate different checking rules for performing rule checking on a chip for which layout planning has been completed according to a set of rule parameters, and to construct corresponding checking scripts according to the checking rules;

[0041] The rule checking module is used to perform rule checking on the chip using a checking script to output problem items that do not meet the checking rules and repair the problem items to obtain a target chip that complies with the design rule constraint file.

[0042] In a third aspect, the present application discloses an electronic device, which includes a processor and a memory; wherein the memory is used to store a computer program, and the computer program is loaded and executed by the processor to implement the aforementioned chip layout planning rule checking method.

[0043] In a fourth aspect, the present application discloses a computer-readable storage medium for storing a computer program; wherein the computer program, when executed by a processor, implements the aforementioned chip layout planning rule checking method.

[0044] The present application provides a rule checking method for chip layout planning, comprising: parsing a design rule constraint file of a target manufacturing process to extract a set of rule parameters; generating different checking rules for performing rule checking on a chip for which layout planning has been completed according to the set of rule parameters, and constructing a corresponding checking script according to the checking rules; performing rule checking on the chip using the checking script to output problem items that do not meet the checking rules, and repairing the problem items to obtain a target chip that complies with the design rule constraint file.

[0045] The beneficial effects of this application include prioritizing comprehensive consideration of more physical design constraints, writing layout planning check rules through a design rule constraint file tailored to the target manufacturing process, and generating corresponding check scripts. This check script is then used to perform rule checking and repairs on layout-planned chips. This allows for consideration of wiring resources, space utilization, and foundry manufacturing requirements to repair layout-planned chips, preventing a series of issues that would arise later, consuming more time and effort and making them more difficult to repair. This saves area, reduces the time required for subsequent iterations, and improves efficiency.

[0046] In addition, the present application provides a chip layout planning rule checking device, equipment and storage medium, which correspond to the above-mentioned chip layout planning rule checking method and have the same effect as above. BRIEF DESCRIPTION OF THE DRAWINGS

[0047] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are merely embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without paying any creative work.

[0048] Figure 1 A flow chart of a chip layout planning rule checking method disclosed in this application;

[0049] Figure 2 A schematic diagram of a module boundary of a chip disclosed in this application;

[0050] Figure 3 A schematic diagram of a memory cell distance boundary disclosed in this application;

[0051] Figure 4 A schematic diagram of a memory cell spacing disclosed in this application;

[0052] Figure 5 Schematic diagram of different directions of a memory unit disclosed in this application;

[0053] Figure 6 A schematic diagram of a memory cell offset spacing disclosed in this application;

[0054] Figure 7 This is an overall flow chart of rule checking for a chip layout planning disclosed in this application;

[0055] Figure 8 A schematic diagram of a layout plan that meets the inspection rules disclosed in this application;

[0056] Figure 9This is a schematic structural diagram of a chip layout planning rule checking device disclosed in this application;

[0057] Figure 10 This is a structural diagram of an electronic device disclosed in this application. DETAILED DESCRIPTION

[0058] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of the present invention.

[0059] With the rapid advancement of chip process technology, integrated circuit design is moving towards multifunctionality, high performance, low power consumption, ultra-high speed, portability, high yield, long lifespan, and short design cycles. Simultaneously, device size is shrinking, and the number of transistors that can be placed on a chip is rapidly increasing. Furthermore, the use of IP (Intellectual Property) cores and memories is increasing. Back-end personnel are spending more time on memory placement and floorplanning.

[0060] Despite the widespread automation of chip design, layout planning is still typically done manually. Designers must draw on their extensive design experience to select a near-optimal location for the macrocell layout, but the macrocell's location may not necessarily meet the physical requirements of the manufacturing process.

[0061] The automated solutions provided by EDA tool vendors also have problems after completing automatic layout: (1) Memory distribution is chaotic, resulting in channel segmentation and making power supply network design difficult; (2) The channels between memories are too small, making it impossible to place power supply networks in some channels, and the local density of standard cells in the channels is high, making the subsequent DFT (Design For Testability) logic insertion position unreasonable, resulting in unsatisfactory voltage drop and power consumption design; (3) The uneven placement of memories will lead to space waste and routing congestion at the edge of the layout, and manual adjustment will increase the workload. EDA automation technology is more inclined to the PPA (Performance, Power, Area) results of high-quality layout planning, so it does not comprehensively consider more physical design constraints in the algorithm model, which will lead to an increase in the number of violations in subsequent design rule checks and advanced processes.

[0062] Therefore, under advanced technology, it is necessary to check and repair the layout of the chip, whether it is completed manually or using EDA tools.

[0063] To this end, this application provides a chip layout planning rule checking solution that can take into account winding resources, space utilization, and foundry manufacturing requirements, and inspect and repair the chips that have completed layout planning to avoid problems later, spend more time and energy, and improve efficiency.

[0064] The embodiment of the present invention discloses a chip layout planning rule checking method, see Figure 1 As shown, the method includes:

[0065] Step S11: parsing the design rule constraint file of the target manufacturing process to extract a set of rule parameters.

[0066] The target manufacturing process is used to describe the physical implementation environment of chip manufacturing, and usually refers to the specific technical nodes of integrated circuit manufacturing, such as process capabilities, material properties, etc. In the embodiments of the present application, the target manufacturing process is illustrated by taking the advanced process of nanoscale integrated circuits as an example. In the chip layout planning process, determining the position of each macro unit on the chip is the primary task of floorplan. For advanced processes, the requirements for the physical location of their process manufacturing are also more stringent. Therefore, it is necessary to integrate the manufacturing process rules and perform certain rule checks on the floorplan to make it meet physical requirements.

[0067] In the embodiments of this application, a design rule constraint file is parsed based on the target manufacturing process. This file typically contains some of the manufacturing rule requirements in the foundry's documentation, including the physical constraints imposed by the manufacturing process on the integrated circuit layout. It should be noted that the design rule constraint file conforms to the industry's common format, and the specific parameter values ​​depend on the manufacturing process node.

[0068] Specifically, the rule parameter set mainly includes: geometric constraints, positional constraints, and structural constraints. Geometric constraints are mainly used to define the boundary dimensions of functional modules, usually involving size, shape, etc. Positional constraints are mainly used to define the spacing between functional modules and the chip boundary and the spacing between functional modules, that is, to specify the module spacing. Structural constraints are mainly used to define the direction of functional modules and the arrangement between functional modules, that is, to specify the module layout. Among them, functional modules are pre-defined modules in the chip. They usually have fixed areas and interface locations and need to be properly placed according to timing requirements and data flow. They include Standard Cell, Boundary Cell, Physical Cell, Tap Cell, Memory Cell, etc.

[0069] In one feasible implementation, when parsing the design rule constraint file for the target manufacturing process, semantic segmentation can be used to extract rule parameters from the file, such as minimum line width and spacing. This solves the problem of parsing unstructured documents. Furthermore, to achieve cross-platform compatibility, documents from multiple vendors can be converted into a unified intermediate representation, and then the checking rules can be written. This supports heterogeneous processes and achieves cross-platform compatibility.

[0070] Step S12: generating different checking rules for performing rule checking on the chip for which layout planning has been completed according to the rule parameter set, and constructing corresponding checking scripts according to the checking rules.

[0071] In an embodiment of the present application, after different rule parameters are extracted, the inspection rules for the layout planning are written according to the rule parameter set. Each rule corresponds to at least one script generation logic, and a corresponding inspection script is constructed according to the inspection rules. Specifically: first, syntax adaptation is performed to convert the inspection rules into discrete command scripts that can be recognized by a preset electronic design automation tool. The preset electronic design automation tool can provide automation technology to achieve automatic layout and post-inspection. For example, the preset electronic design automation tool can be an EDA tool. Furthermore, after conversion into commands that can be recognized by the tool, logical encapsulation is performed to encapsulate the discrete command script to obtain an inspection script.

[0072] In a feasible implementation, in order to further improve the efficiency of subsequent rule checking of chips that have completed layout planning using check scripts, rule priority sorting can be introduced for different check rules, and multi-level check scripts can be dynamically generated to shorten verification time and optimize resource usage. At the same time, after the check rules are converted into check scripts that can be called and executed by preset electronic design automation tools to implement rule checking, the feedback of real-time design data can be combined during the execution of the check. For example, based on the rule violation report, design optimization suggestions are automatically generated and fed back to the tool for intelligent repair by dynamically adjusting the inspection granularity. While realizing the check-correction closed loop, excessive inspection is avoided and efficiency is improved. In addition, in order to support multi-version tool compatibility and reduce manual adaptation costs, taking EDA tools as an example, the grammatical structure of the command script can be dynamically adjusted based on the API interface version of the EDA tool.

[0073] Step S13: Perform rule checking on the chip using the checking script to output problematic items that do not meet the checking rules, and repair the problematic items to obtain a target chip that complies with the design rule constraint file.

[0074] In the embodiment of the present application, a rule check is performed on the module that has completed the floorplan, and the items that do not meet the check rules are repaired. After the repair, the floorplan is checked again until all the rule checks are met.

[0075] Specifically, the pre-set electronic design automation tool is first invoked to execute a check script, performing a rule check on the chip and outputting problematic items that do not meet the check rules. The problem items are then fixed using the pre-set electronic design automation tool according to the check rules. Problems that cannot be fixed using tool commands require manual repair. This involves obtaining adjustment parameters input through a human-computer interface and using them to fix the problem items. For example, boundary size and core-to-die spacing are recalculated and adjusted. Finally, once the problem items are fixed, they are rechecked until all rule checks are met, resulting in the target chip.

[0076] The present application provides a rule checking method for chip layout planning, comprising: parsing a design rule constraint file of a target manufacturing process to extract a set of rule parameters; generating different checking rules for performing rule checking on a chip for which layout planning has been completed according to the set of rule parameters, and constructing a corresponding checking script according to the checking rules; performing rule checking on the chip using the checking script to output problem items that do not meet the checking rules, and repairing the problem items to obtain a target chip that complies with the design rule constraint file.

[0077] The beneficial effects of this application include prioritizing comprehensive consideration of more physical design constraints, writing layout planning check rules through a design rule constraint file tailored to the target manufacturing process, and generating corresponding check scripts. This check script is then used to perform rule checking and repairs on layout-planned chips. This allows for consideration of wiring resources, space utilization, and foundry manufacturing requirements to repair layout-planned chips, preventing a series of issues that would arise later, consuming more time and effort and making them more difficult to repair. This saves area, reduces the time required for subsequent iterations, and improves efficiency.

[0078] Based on the above embodiment, this embodiment will specifically explain step S12 in the above embodiment. When writing floorplan checking rules, the rules include: 1) chip boundary size; 2) core-to-die spacing within the chip; 3) spacing between memory cells; 4) spacing between memory and the chip boundary; 5) memory placement orientation; 6) memory alignment, etc.

[0079] In a first feasible implementation, a first check rule for performing rule checking on a chip for which layout planning has been completed is generated based on the geometric constraints. The generation process of the first check rule may include the following steps:

[0080] The width and height of the chip are required to meet a first threshold standard;

[0081] Based on the target manufacturing process, a corresponding semiconductor device manufacturing technology is selected, and based on the semiconductor device manufacturing technology, it is stipulated that the components in the chip are aligned on the manufacturing grid.

[0082] Geometric constraints are primarily used to define the boundaries of functional modules. Boundaries typically refer to the dividing lines between modules within a chip, defining the physical boundaries of the modules. In the embodiments of this application, geometric constraints are used to constrain the overall shape and size of the chip.

[0083] like Figure 2 The figure shows an exemplary inspection rule for specifying the size of a boundary. Boundary refers to the entire chip boundary. The boundary width is specified to meet W1, and the boundary height is specified to meet H1. In other words, W1 and H1 meet the first threshold criterion. For example, using advanced 22nm and below process technology, using FinFET (Fin Field Effect Transistor) technology, all components and boundaries must be aligned with the FinFET fabrication grid.

[0084] In a second feasible implementation, a second check rule for performing rule checking on a chip for which layout planning has been completed is generated based on the position constraint. The generation process of the second check rule may include the following steps:

[0085] It is stipulated that a first horizontal distance and a first vertical distance between the functional module and the chip boundary meet a second threshold standard;

[0086] The distance between the width and height of the memory cell of the chip and the boundary cell of the chip is required to meet a third threshold standard;

[0087] The second horizontal direction spacing and the second vertical direction spacing between the memory cells are required to meet a fourth threshold standard, and based on semiconductor device manufacturing technology, the memory cells are required to be aligned on a manufacturing grid.

[0088] Understandably, advanced processes impose even stricter physical requirements on manufacturing, extending beyond simple DRC (Design Rule Check) violations to include certain spacing requirements between boundary and standard cell areas, as well as requirements for memory placement. As process technology reaches below 20nm, line widths and line spacing shrink further, hindered by lithography resolution. Double patterning techniques are required, and even more restrictions on memory placement and spacing are imposed to achieve lithography accuracy.

[0089] Position constraints are mainly used to define the spacing between functional modules and chip boundaries, as well as the spacing between functional modules. Figure 2 As shown, the spacing between the functional module and the chip boundary is the core-to-die size. Standard cells are the fundamental building blocks used to implement Boolean logic functions in integrated circuit design. They typically have the same height but can vary in width to accommodate different logic function requirements. The boundary here primarily protects the standard cells at the chip boundary from physical damage that may occur during the manufacturing process. The horizontal distance from core to die satisfies W2, and the vertical distance from core to die satisfies H2. In other words, W2 and H2 meet the second threshold standard.

[0090] like Figure 3The figure shows an exemplary check rule for the distance between memory cells and boundary cells. The boundary is defined around the memory to ensure physical consistency in these areas, thus avoiding issues such as timing deviation. The widest distance between the memory and the boundary is specified to meet W3, while the highest distance between the memory and the boundary is specified to meet H3. In other words, W3 and H3 meet the third threshold criterion.

[0091] like Figure 4 The figure shows an exemplary inspection rule for specifying the spacing between memory cells. The horizontal spacing between memories is specified to meet W4, and the vertical spacing between memories is specified to meet H4. Again, using an advanced manufacturing process at 22nm or below, using FinFET (Fin Field Effect Transistor) technology, the memory is required to be aligned to the FinFET manufacturing grid.

[0092] Furthermore, the process of specifying that the second horizontal spacing and the second vertical spacing between the memory cells meet the fourth threshold standard specifically includes the following steps:

[0093] Determining a first size of the boundary unit and a second size of the well connection unit;

[0094] Determine a first winding space according to the width and minimum spacing of the horizontal metal routing layer, and determine a second winding space according to the width and minimum spacing of the vertical metal routing layer;

[0095] Determine a threshold value corresponding to a second horizontal spacing between memory cells based on the first size, the second size, and the size of the first winding space;

[0096] A threshold value corresponding to a second vertical spacing between the memory cells is determined based on the first size and the size of the second winding space.

[0097] In this embodiment, the horizontal spacing between memories is specified to be sufficient to insert two boundary cells and one tap cell, and there is still sufficient winding space. The winding spacing is roughly calculated by the width and minimum spacing of the horizontal metal routing layer. Among them, the tap cell (well connection unit) is mainly used for boundary scan testing of the chip; the vertical spacing between memories is specified to be sufficient to insert two boundary cells, and there is still sufficient winding space. The winding spacing is roughly calculated by the width and minimum spacing of the vertical metal routing layer.

[0098] Assume that the width and height of the boundary cell are Wb and Hb respectively, the width and height of the tap cell are Wt and Ht respectively; the routing metal layers are M0, M1…Mn-1, Mn, the sum of the line width and line spacing is m, and the number of memory pins is n. The required routing space is roughly calculated as ,and , .

[0099] In a third feasible implementation, a third check rule for performing rule checking on a chip for which layout planning has been completed is generated based on the structural constraints. The generation process of the third check rule may include the following steps:

[0100] The arrangement direction of the memory cells is specified according to the arrangement direction of the standard cells in the chip;

[0101] Check the horizontal and vertical offsets of the memory cells and dictate the alignment of the memory cells based on the offsets.

[0102] Structural constraints are mainly used to define the direction of functional modules and the arrangement between functional modules. Figure 5 The following is a diagram showing the directions in which memories can exist. In advanced processes, the poly (polysilicon) direction of the memory should be consistent with the poly direction of the standard cell. Therefore, the direction of the memory cannot be rotated arbitrarily and can only be R0, R180, MY, or MX. Among them, R0 means that the object has not been rotated, that is, it maintains its original direction; R180 means rotating 180° counterclockwise, MX means flipping along the X axis, and MY means flipping along the Y axis. Figure 6 The figure shows an exemplary schematic diagram of a check rule for checking the alignment of memory cells. The check rule is used to check the offset in the horizontal and vertical directions of the memory, and if there is an offset, alignment is performed.

[0103] Further, such as Figure 7 As shown, it is an overall flow chart provided based on the above-mentioned embodiment. By writing corresponding rule scripts to check and repair the floorplan after completing it, efficiency is improved and the time period for subsequent iterations is reduced. It is divided into the following three parts: 1) Writing relevant check scripts for floorplan and converting them into commands that can be recognized by back-end EDA tools; 2) Performing rule checks on modules that have completed floorplans and repairing items that do not meet the rule checks; 3) After repairing, performing rule checks on floorplans again until all rule checks are met. Among them, for more specific content about the above rules, please refer to the corresponding content disclosed in the above-mentioned embodiments, which will not be repeated here.

[0104] It should be noted that after converting the written check rules into commands that can be recognized by the back-end EDA tool, it is necessary to determine the memory type used in the module, and then perform rule checking on the module that has completed floorplan. The purpose of this step is to optimize the performance and resource utilization of the module. By selecting a suitable storage structure for the memory, layout problems can be avoided in the floorplan stage, the number of iterations can be reduced, and design efficiency can be improved. Figure 8 The figure shows the layout after the floorplan rule check is completed, and the target chip obtained satisfies any check rule.

[0105] As can be seen, given the stringent physical placement requirements of advanced process manufacturing, floorplan checking rules are written with a priority on comprehensive consideration of more physical design constraints to meet the foundry's manufacturing requirements and translate them into commands that can be understood by back-end EDA tools. Appropriate checks are performed on completed floorplan modules to prevent a series of issues that may arise later and become more difficult to fix. Re-entering the floorplan step to perform repairs would require additional time and effort, and would also require correcting issues such as excessive or insufficient memory spacing and misalignment that may exist after manual or EDA tool layout.

[0106] It's worth noting that floorplan rules can further consider top-level constraints for things like I / O pads (chip pin processing modules), as well as potential violations for irregular memories. Rules tailored to these constraints can be developed to refine the checking script.

[0107] Correspondingly, the present application also discloses a chip layout planning rule checking device, see Figure 9 As shown, the device includes:

[0108] A file parsing module 11 is used to parse the design rule constraint file of the target manufacturing process to extract a set of rule parameters;

[0109] A script construction module 12 is used to generate different checking rules for performing rule checking on a chip for which layout planning has been completed according to a set of rule parameters, and to construct corresponding checking scripts according to the checking rules;

[0110] The rule checking module 13 is used to perform rule checking on the chip using a checking script to output problem items that do not meet the checking rules and repair the problem items to obtain a target chip that meets the design rule constraint file.

[0111] Among them, for more specific working processes of the above modules, please refer to the corresponding contents disclosed in the aforementioned embodiments, which will not be repeated here.

[0112] It can be seen that the above scheme of this embodiment includes: parsing the design rule constraint file of the target manufacturing process to extract a set of rule parameters; generating different inspection rules for performing rule checks on the chip for which layout planning has been completed according to the rule parameter set, and constructing corresponding inspection scripts according to the inspection rules; using the inspection script to perform rule checks on the chip to output problem items that do not meet the inspection rules, and repairing the problem items to obtain a target chip that complies with the design rule constraint file.

[0113] The beneficial effects of this application include prioritizing comprehensive consideration of more physical design constraints, writing layout planning check rules through a design rule constraint file tailored to the target manufacturing process, and generating corresponding check scripts. This check script is then used to perform rule checking and repairs on layout-planned chips. This allows for consideration of wiring resources, space utilization, and foundry manufacturing requirements to repair layout-planned chips, preventing a series of issues that would arise later, consuming more time and effort and making them more difficult to repair. This saves area, reduces the time required for subsequent iterations, and improves efficiency.

[0114] In a specific embodiment, the file parsing module 11 is specifically configured to:

[0115] Parse the design rule constraint file of the target manufacturing process to extract geometric constraints, positional constraints, and structural constraints. Geometric constraints are used to define the boundary dimensions of functional modules, positional constraints are used to define the spacing between functional modules and chip boundaries, and the spacing between functional modules. Structural constraints are used to define the orientation of functional modules and the arrangement between functional modules.

[0116] In a specific embodiment, the script construction module 12 includes:

[0117] A first rule construction unit is used to generate a first check rule for performing rule check on a chip for which layout planning has been completed according to the geometric constraint;

[0118] A second rule construction unit is used to generate a second check rule for performing rule check on the chip for which layout planning has been completed according to the position constraint;

[0119] A third rule construction unit is used to generate a third check rule for performing rule checking on the chip for which layout planning has been completed according to the structural constraint;

[0120] In a specific embodiment, the script construction module 12 is specifically used to:

[0121] Converting the inspection rules into discrete command scripts that can be recognized by a preset electronic design automation tool, and encapsulating the discrete command scripts to obtain inspection scripts;

[0122] Accordingly, the rule checking module 13 is specifically configured to:

[0123] Calling a preset electronic design automation tool to execute a check script, performing rule check on the chip, and outputting problem items that do not meet the check rules;

[0124] Repairing the problem item using a preset electronic design automation tool, and / or obtaining input adjustment parameters based on a human-computer interaction interface, and repairing the problem item using the adjustment parameters;

[0125] When the problem item is repaired, the step of calling the preset electronic design automation tool to execute the inspection script is triggered again. If there is no problem item that does not meet the inspection rules, it is determined that the chip complies with the design rule constraint file and the target chip is obtained.

[0126] Furthermore, the embodiment of the present application also discloses an electronic device, Figure 10 This is a structural diagram of an electronic device 20 according to an exemplary embodiment, and the content in the diagram cannot be considered as any limitation to the scope of use of the present application.

[0127] Figure 10 This is a schematic diagram of the structure of an electronic device 20 provided in an embodiment of the present application. The electronic device 20 may include: at least one processor 21, at least one memory 22, a power supply 23, a communication interface 24, an input / output interface 25, and a communication bus 26. The memory 22 is used to store a computer program, which is loaded and executed by the processor 21 to implement the relevant steps of the chip floorplan rule checking method disclosed in any of the aforementioned embodiments.

[0128] In this embodiment, the power supply 23 is used to provide operating voltage for each hardware device on the electronic device 20; the communication interface 24 can create a data transmission channel between the electronic device 20 and the external device. The communication protocol it follows is any communication protocol that can be applied to the technical solution of this application and is not specifically limited here; the input and output interface 25 is used to obtain external input data or output data to the outside world. Its specific interface type can be selected according to specific application needs and is not specifically limited here.

[0129] In addition, the memory 22, as a carrier for resource storage, can be a read-only memory, random access memory, a magnetic disk, or an optical disk. The resources stored thereon may include an operating system 221, a computer program 222, and data 223. The data 223 may include various data. The storage method can be temporary storage or permanent storage.

[0130] The operating system 221 is used to manage and control the hardware devices and computer program 222 on the electronic device 20, and can be Windows Server, Netware, Unix, Linux, etc. In addition to including a computer program capable of implementing the chip floorplan rule checking method executed by the electronic device 20 disclosed in any of the aforementioned embodiments, the computer program 222 can further include a computer program capable of implementing other specific tasks.

[0131] Furthermore, the embodiments of the present application also disclose a computer-readable storage medium, wherein the computer-readable storage medium mentioned here includes random access memory (RAM), memory, read-only memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, register, hard disk, magnetic disk or optical disk or any other form of storage medium known in the technical field. Wherein, when the computer program is executed by the processor, the rule checking method of the aforementioned chip layout planning is implemented. For the specific steps of the method, please refer to the corresponding content disclosed in the aforementioned embodiment, and no further details will be given here.

[0132] Furthermore, an embodiment of the present application also provides a computer program product, including a computer program / instruction, which, when executed by a processor, implements any one of the above-mentioned chip layout planning rule checking methods.

[0133] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on its differences from the other embodiments. Reference can be made to the descriptions of the identical or similar parts between the various embodiments. For the devices disclosed in the embodiments, since they correspond to the methods disclosed in the embodiments, the descriptions are relatively simple, and the relevant parts can be referred to the descriptions of the methods.

[0134] The steps of the chip floorplan rule checking method or algorithm described in conjunction with the embodiments disclosed herein can be implemented directly using hardware, a software module executed by a processor, or a combination of the two. The software module can be stored in random access memory (RAM), internal memory, read-only memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, a hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art.

[0135] Finally, it should be noted that, in this document, relational terms such as first and second, etc., are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the terms "comprises," "comprising," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or device comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or device. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of additional identical elements in the process, method, article, or device comprising the element.

[0136] The above is a detailed introduction to the chip layout planning rule checking method, device, equipment and medium provided by the present invention. Specific examples are used herein to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only used to help understand the method of the present invention and its core ideas. At the same time, for those skilled in the art, according to the ideas of the present invention, there will be changes in the specific implementation methods and application scopes. In summary, the content of this specification should not be understood as limiting the present invention.

Claims

1. A chip layout planning rule checking method, characterized in that: include: Parsing the design rule constraint file of the target manufacturing process to extract the rule parameter set; Generating different checking rules for performing rule checking on a chip for which layout planning has been completed according to the rule parameter set, and constructing corresponding checking scripts according to the checking rules; The chip is subjected to rule checking using the checking script to output problematic items that do not meet the checking rules, and the problematic items are repaired to obtain a target chip that complies with the design rule constraint file.

2. The chip floorplanning rule checking method according to claim 1, characterized in that: The step of parsing the design rule constraint file of the target manufacturing process to extract a set of rule parameters includes: Parse the design rule constraint file of the target manufacturing process to extract geometric constraints, positional constraints and structural constraints; wherein the geometric constraints are used to define the boundary size of the functional module, the positional constraints are used to define the spacing between the functional module and the chip boundary and the spacing between the functional modules, and the structural constraints are used to define the direction of the functional module and the arrangement between the functional modules.

3. The chip floorplanning rule checking method according to claim 2, characterized in that: Generating different checking rules for performing rule checking on a chip for which layout planning has been completed according to the rule parameter set includes: generating a first checking rule for performing a rule check on a chip for which layout planning has been completed according to the geometric constraint; The process of generating the first inspection rule includes: stipulating that the width and height of the chip meet a first threshold standard; Based on the target manufacturing process, a corresponding semiconductor device manufacturing technology is selected, and based on the semiconductor device manufacturing technology, it is stipulated that the components in the chip are aligned on the manufacturing grid.

4. The chip floorplanning rule checking method according to claim 3, characterized in that: Generating different checking rules for performing rule checking on a chip for which layout planning has been completed according to the rule parameter set includes: generating, according to the position constraint, a second checking rule for performing a rule check on a chip for which layout planning has been completed; The process of generating the second inspection rule includes: stipulating that a first horizontal distance and a first vertical distance between the functional module and the chip boundary meet a second threshold standard; stipulating that the distance between the width and height of the memory unit of the chip and the boundary unit of the chip meets a third threshold standard; The second horizontal spacing and the second vertical spacing between the memory cells are required to meet a fourth threshold standard, and based on the semiconductor device manufacturing technology, the memory cells are required to be aligned on the manufacturing grid.

5. The chip floorplan rule checking method according to claim 4, characterized in that: The step of specifying that the second horizontal spacing and the second vertical spacing between the memory cells meet a fourth threshold standard includes: Determining a first size of the boundary unit and a second size of the well connection unit; Determine a first winding space according to the width and minimum spacing of the horizontal metal routing layer, and determine a second winding space according to the width and minimum spacing of the vertical metal routing layer; Determining a threshold value corresponding to a second horizontal spacing between the memory cells based on the first size, the second size, and the size of the first winding space; A threshold value corresponding to a second vertical spacing between the memory cells is determined based on the first size and the size of the second winding space.

6. The chip floorplan rule checking method according to claim 4, characterized in that: Generating different checking rules for performing rule checking on a chip for which layout planning has been completed according to the rule parameter set includes: generating a third checking rule for performing a rule check on a chip for which layout planning has been completed according to the structural constraint; The process of generating the third inspection rule includes: Specifying an arrangement direction of the memory cells according to an arrangement direction of standard cells in the chip; The memory unit is checked for offset in the horizontal direction and the vertical direction, and alignment of the memory unit is specified according to the offset.

7. The chip floorplan rule checking method according to any one of claims 1 to 6, characterized in that: The step of constructing a corresponding inspection script according to the inspection rules includes: Converting the inspection rule into a discrete command script recognizable by a preset electronic design automation tool, and encapsulating the discrete command script to obtain the inspection script; Accordingly, the chip is subjected to rule checking using the checking script to output problem items that do not meet the checking rules, and the problem items are repaired to obtain a target chip that complies with the design rule constraint file, including: Calling the preset electronic design automation tool to execute the check script, performing rule check on the chip, and outputting problem items that do not meet the check rules; Repairing the problem item using the preset electronic design automation tool, and / or obtaining input adjustment parameters based on a human-computer interaction interface, and repairing the problem item using the adjustment parameters; When the problem item is repaired, the step of calling the preset electronic design automation tool to execute the inspection script is triggered again. If there is no problem item that does not meet the inspection rules, it is determined that the chip complies with the design rule constraint file and the target chip is obtained.

8. A chip layout planning rule checking device, characterized in that: include: A file parsing module, used to parse the design rule constraint file of the target manufacturing process to extract a set of rule parameters; A script construction module, configured to generate different checking rules for performing rule checking on a chip for which layout planning has been completed according to the rule parameter set, and to construct corresponding checking scripts according to the checking rules; A rule checking module is used to perform rule checking on the chip using the checking script to output problem items that do not meet the checking rules and repair the problem items to obtain a target chip that meets the design rule constraint file.

9. An electronic device, characterized in that: The electronic device includes a processor and a memory; wherein the memory is used to store a computer program, and the computer program is loaded and executed by the processor to implement the chip layout planning rule checking method according to any one of claims 1 to 7.

10. A computer-readable storage medium, characterized in that Used to store a computer program; wherein when the computer program is executed by a processor, the rule checking method for chip layout planning according to any one of claims 1 to 7 is implemented.

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