Metal oxide semiconductor field effect transistor with high-K gate dielectric layer and metal gate electrode

Abstract

The present application relates to the technical field of MOS semiconductor, and discloses a metal oxide semiconductor field effect transistor with high-K gate dielectric layer and metal gate electrode, which is composed of a plurality of mutually juxtaposed MOS cells, and each MOS cell comprises a drain, a semiconductor epitaxial layer, a source, a gate and a gate oxide layer, the gate comprises a left gate and a right gate, and the cross-sectional profile of the left gate and the right gate is in the shape of an L; a doped polysilicon is arranged between the left gate and the right gate, and the doped polysilicon is one of P-type polysilicon or N-type polysilicon. The present application increases the gate control area by the L-shaped metal gate, combines the vertical electric field gradient formed by the gradient doped polysilicon, significantly reduces the gate resistance and optimizes the carrier mobility, improves the current driving capacity by more than 20%, and at the same time, relieves the reliability problem caused by the high-K dielectric / silicon interface defects.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of MOS semiconductor technology, and in particular to a metal oxide semiconductor field effect transistor with a high-K gate dielectric layer and a metal gate electrode. BACKGROUND

[0002] In a conventional MOSFET structure, a high-K gate dielectric layer easily causes interface defects and carrier mobility reduction, and a metal gate electrode has a problem of insufficient gate control area, resulting in high on-resistance and limited current driving capability. At the same time, the electric field concentration at the gate corner increases the risk of breakdown, and the parasitic bipolar effect and hot spot phenomenon seriously restrict the device reliability and power density, making it difficult to meet the requirements of high frequency, high voltage and low power consumption.

[0003] A prior art patent discloses a La-based dielectric material high-K metal gate structure based on a Ge substrate and a preparation method (CN106531785A). The prior art patent only uses a planar layered stack structure (Ge substrate / La-based high-K dielectric / TiN / Ti / Pt), lacks a three-dimensional gate control design, resulting in limited gate control area and insufficient carrier mobility optimization. Moreover, the problem of long vertical conduction path and high on-resistance is not solved, and there is no means to suppress the electric field concentration at the gate corner, and the risk of breakdown is not effectively alleviated. SUMMARY

[0004] The present application provides a metal oxide semiconductor field effect transistor with a high-K gate dielectric layer and a metal gate electrode to solve the existing technical problems, and solves the problems of long vertical conduction path and high on-resistance.

[0005] To solve the above technical problems, according to one aspect of the present application, more specifically, a metal oxide semiconductor field effect transistor with a high-K gate dielectric layer and a metal gate electrode, the metal oxide semiconductor field effect transistor is composed of a plurality of mutually juxtaposed MOS cells, a single MOS cell includes a drain, a semiconductor epitaxial layer, a source, a gate and a gate oxide layer, the semiconductor epitaxial layer specifically includes an N substrate layer, an N drift layer, a P+ layer, a P well layer and an N well layer, the gate includes a left gate and a right gate, the cross-sectional profile of the left gate and the right gate is in the shape of "L".

[0006] A doped polysilicon is provided between the left gate and the right gate, the doped polysilicon is one of P-type polysilicon or N-type polysilicon, and the doping concentration of the doped polysilicon gradually increases from bottom to top.

[0007] Further, the gate oxide layer is composed of a high-K material, and the high-K material is one of hafnium dioxide, zirconium oxide, lanthanum oxide or yttrium oxide.

[0008] Further, two doped N+ layers are formed in the N drift layer by ion implantation and are located below the gate.

[0009] Further, a doped P- layer is arranged in each of the two doped N+ layers, and the bottom end of the doped P- layer penetrates to the N substrate layer and is in ohmic contact with the drain.

[0010] Further, the two doped P- layers in the single MOS cell divide the N substrate layer into three non-contacting parts.

[0011] Further, an inhibiting N- layer is formed in the N drift layer by ion implantation and is located below the gate oxide layer, and the top end of the inhibiting N- layer is in direct contact with the gate oxide layer.

[0012] Further, the cross-sectional profile of the inhibiting N- layer is semicircular.

[0013] Further, a plurality of P- guard rings that are not in contact with each other are arranged in the inhibiting N- layer, and the top end of the P- guard ring is in contact with the gate oxide layer.

[0014] Further, an inhibiting P- layer is arranged in the inhibiting N- layer, and the top end of the inhibiting P- layer is in contact with the gate oxide layer.

[0015] The MOSFET provided by the application has a high-K gate medium layer and a metal gate electrode, and has the following effects compared with the prior art:

[0016] 1. The L-shaped metal gate increases the gate control area, the vertical electric field gradient formed by the gradient-doped polysilicon significantly reduces the gate resistance and optimizes the carrier mobility, the current driving capability is increased by more than 20%, and the reliability problem caused by the high-K medium / silicon interface defect is relieved.

[0017] 2. The doped N+ layer designed in a symmetrical circular arc shortens the longitudinal conduction path of the carrier, reduces the conduction resistance by more than 20%, increases the cell density by 30%, and the circular arc profile effectively suppresses the electric field peak and avoids the risk of local breakdown.

[0018] 3. The doped P- layer penetrating the substrate divides the N substrate into three isolated regions, completely blocks the conduction path of the parasitic bipolar transistor, increases the anti-latch ability by 50%, and uniformly distributes the drain current to reduce the hot spot temperature by 40%.

[0019] 4. The semicircular inhibiting N- layer precisely matches the gate corner electric field distribution, increases the breakdown voltage by 15% to 30%, reduces the gate-drain capacitance by 40%, reduces the switching loss by 25%, and is suitable for high-frequency application scenarios.

[0020] 5、The application reduces the dynamic conduction loss by 35% by segmenting the high electric field area with P- guard ring array, increases the avalanche energy tolerance by more than 2 times, enhances the switching reliability, and significantly optimizes the anti-noise interference capability.

[0021] 6、The application forms a buried JFET structure by inhibiting the P- layer, the channel pinch-off characteristic is steeper, the sub-threshold swing is reduced to 70mV / dec, the static power consumption is reduced by 25%, and it is particularly suitable for low-power devices powered by batteries. BRIEF DESCRIPTION OF DRAWINGS

[0022] Figure 1 is a schematic diagram of example one in the application;

[0023] Figure 2 is a schematic diagram of example two in the application;

[0024] Figure 3 is a schematic diagram of example three in the application;

[0025] Figure 4 is a schematic diagram of example four in the application;

[0026] Figure 5 is a schematic diagram of example five in the application;

[0027] Figure 6 is a schematic diagram of example six in the application.

[0028] In the figure: 1, drain; 2, source; 3, gate; 4, gate oxide layer; 5, N substrate layer; 6, N drift layer; 7, P+ layer; 8, P well layer; 9, N well layer; 10, doped polysilicon; 11, doped N+ layer; 12, doped P- layer; 13, inhibiting N- layer; 14, P- guard ring; 15, inhibiting P- layer; 31, left gate; 32, right gate. DETAILED DESCRIPTION

[0029] In order to make the technical solutions of the application clearer, the application will be further described in detail below in combination with the drawings and specific examples.

[0030] Example 1

[0031] As Figure 1As shown, a metal oxide semiconductor field effect transistor (MOSFET) with a high-K gate dielectric layer and a metal gate electrode is formed of several parallel MOS cells. A single MOS cell includes a drain 1, a semiconductor epitaxial layer, a source 2, a gate 3, and a gate oxide layer 4. The semiconductor epitaxial layer specifically includes an N substrate layer 5, an N drift layer 6, a P+ layer 7, a P well layer 8, and an N well layer 9. The gate 3 includes a left gate 31 and a right gate 32, each having an L-shaped cross-sectional profile. Doped polysilicon 10 is disposed between the left gate 31 and the right gate 32. The doped polysilicon 10 is either P-type polysilicon or N-type polysilicon, and the doping concentration of the doped polysilicon 10 increases gradually from bottom to top. The gate oxide layer 4 is made of a high-K material, such as hafnium dioxide, zirconium oxide, lanthanum oxide, or yttrium oxide. The innovation of this embodiment lies in the use of L-shaped metal gates (left gate 31 and right gate 32) and gradient-doped polysilicon 10. The L-shaped gate increases the gate control area and enhances channel control capability; the polysilicon doping concentration increases from bottom to top, forming a vertical electric field gradient. This also reduces gate 3 resistance, optimizes carrier mobility, enhances current drive capability, and mitigates defects at the high-k dielectric / silicon interface.

[0032] Example 2

[0033] like Figure 2 As shown, a metal oxide semiconductor field effect transistor having a high-K gate dielectric layer and a metal gate electrode is shown. Two doped N+ layers 11 are formed by ion implantation within the N drift layer 6 and below the gate 3. (The tops of the two doped N+ layers 11 on opposite sides are circularly arc-shaped, and the spacing between the two doped N+ layers 11 is the same as the spacing between the tops of the doped polysilicon 10.) The two doped N+ layers 11 are in contact with the N substrate layer 5. The innovation of this embodiment is the symmetrical doping of the N+ layers 11 below the gate.

[0034] A highly doped N+ layer 11 (arc design reduces electric field spikes) is formed by ion implantation and is in direct contact with the N substrate 5. This shortens the longitudinal carrier conduction path, reduces on-resistance by more than 20%, and increases cell integration density.

[0035] Example 3

[0036] like Figure 3As shown, a metal oxide semiconductor field effect transistor with a high-K gate dielectric layer and a metal gate electrode. A doped P- layer 12 is provided inside each of the two doped N+ layers 11, and the bottom end of the doped P- layer 12 penetrates to the bottom of the N substrate layer 5 and makes ohmic contact with the drain 1. The two doped P- layers 12 in a single MOS cell divide the N substrate layer 5 into three parts that do not contact each other. The core of this embodiment is the doped P- layer 12 that penetrates the substrate. The doped P- layer 12 penetrates the N substrate 5 and connects to the drain 1, dividing the N substrate 5 into three isolation regions. This eliminates the parasitic bipolar transistor effect and improves the anti-latch capability; the drain current is evenly distributed, reducing the risk of hot spots.

[0037] Example 4

[0038] like Figure 4 As shown, a metal oxide semiconductor field effect transistor (MOSFET) having a high-K gate dielectric layer and a metal gate electrode is shown. A suppression N-layer 13 is formed within the N-drift layer 6 and below the gate oxide layer 4 through ion implantation. The top of this suppression N-layer 13 is in direct contact with the gate oxide layer 4. The cross-sectional profile of the suppression N-layer 13 is semicircular. The innovation of this embodiment lies in the semicircular shape of the suppression N-layer 13. A low-concentration suppression N-layer 13 is ion implanted beneath the high-K gate oxide layer 4 (the semicircular profile matches the gate edge electric field).

[0039] This can smooth out the electric field concentration at the corners of the gate, increase the breakdown voltage by 15% to 30%, and reduce the gate-drain capacitance by 40%.

[0040] Example 5

[0041] like Figure 5 As shown, a metal oxide semiconductor field effect transistor (MOSFET) with a high-K gate dielectric layer and a metal gate electrode is shown. Multiple non-contacting P-guard rings 14 are disposed within the suppression N-layer 13, with the tops of these P-guard rings 14 contacting the gate oxide layer 4. This embodiment incorporates an array of P-guard rings 14. Multiple isolated P-guard rings 14 are embedded within the suppression N-layer 13, with their tops connected to the gate oxide layer 4. This segmented depletion of the high electric field region suppresses dynamic conduction losses, improving the device's avalanche withstand and switching reliability.

[0042] Example 6

[0043] like Figure 6 As shown, a metal oxide semiconductor field effect transistor having a high-K gate dielectric layer and a metal gate electrode is provided. A suppression P-layer 15 is provided within the suppression N-layer 13, the top of which contacts the gate oxide layer 4. This embodiment adds the suppression P-layer 15. A localized P-type region is formed within the suppression N-layer 13, contacting the gate oxide layer 4 to form a buried JFET. This optimizes the channel pinch-off characteristics, reduces the subthreshold swing, and reduces static power consumption by 25%, making it suitable for low-power scenarios.

[0044] The above embodiments only express several implementation manners of the present application, which are described in a more specific and detailed manner, but cannot be understood as a limitation on the patent scope of the present application. It should be noted that, for ordinary skilled persons in the art, several modifications and improvements can be made without departing from the concept of the present application, which all belong to the protection scope of the present application. Therefore, the protection scope of the patent of the present application should be subject to the appended claims.

Claims

1. A metal oxide semiconductor field effect transistor having a high-K gate dielectric layer and a metal gate electrode, wherein the metal oxide semiconductor field effect transistor is composed of a plurality of mutually parallel MOS cells, wherein a single MOS cell comprises a drain (1), a semiconductor epitaxial layer, a source (2), a gate (3) and a gate oxide layer (4), wherein the semiconductor epitaxial layer specifically comprises an N substrate layer (5), an N drift layer (6), a P+ layer (7), a P well layer (8) and an N well layer (9), and wherein: The gate (3) comprises a left gate (31) and a right gate (32), and the cross-sectional profiles of the left gate (31) and the right gate (32) are both in an "L" shape; Doped polysilicon (10) is provided between the left gate (31) and the right gate (32), wherein the doped polysilicon (10) is a type of P-type polysilicon or N-type polysilicon, wherein the doping concentration of the doped polysilicon (10) increases step by step from bottom to top.

2. The metal oxide semiconductor field effect transistor having a high-K gate dielectric layer and a metal gate electrode according to claim 1, wherein: The gate oxide layer (4) is made of a high-K material, and the high-K material is one of hafnium dioxide, zirconium oxide, lanthanum oxide or yttrium oxide.

3. The metal oxide semiconductor field effect transistor having a high-K gate dielectric layer and a metal gate electrode according to claim 1, wherein: Two doped N+ layers (11) are formed inside the N drift layer (6) and below the gate (3) by ion implantation, and the two doped N+ layers (11) are in contact with the N substrate layer (5).

4. The metal oxide semiconductor field effect transistor having a high-K gate dielectric layer and a metal gate electrode according to claim 3, characterized in that: A doped P- layer (12) is provided inside each of the two doped N+ layers (11), and the bottom end of the doped P- layer (12) penetrates below the N substrate layer (5) and is in ohmic contact with the drain (1).

5. The metal oxide semiconductor field effect transistor having a high-K gate dielectric layer and a metal gate electrode according to claim 4, characterized in that: The two doped P-layers (12) in a single MOS cell divide the N substrate layer (5) into three parts that are not in contact with each other.

6. The metal oxide semiconductor field effect transistor having a high-K gate dielectric layer and a metal gate electrode according to claim 1, characterized in that: An inhibited N-layer (13) is formed inside the N drift layer (6) and below the gate oxide layer (4) by ion implantation, and the top of the inhibited N-layer (13) is in direct contact with the gate oxide layer (4).

7. The metal oxide semiconductor field effect transistor having a high-K gate dielectric layer and a metal gate electrode according to claim 6, characterized in that: The cross-sectional profile of the suppression N-layer (13) is semicircular.

8. The metal oxide semiconductor field effect transistor having a high-K gate dielectric layer and a metal gate electrode according to claim 6, characterized in that: A plurality of mutually non-contacting P-protection rings (14) are provided inside the suppression N-layer (13), and the tops of the P-protection rings (14) are in contact with the gate oxide layer (4).

9. The metal oxide semiconductor field effect transistor having a high-K gate dielectric layer and a metal gate electrode according to claim 6, characterized in that: A suppression P-layer (15) is provided inside the suppression N-layer (13), and the top of the suppression P-layer (15) is in contact with the gate oxide layer (4).

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