Display substrate and display device

Abstract

The embodiment of the invention discloses a display substrate and a display device, which are characterized in that a low-temperature polycrystalline silicon transistor, an oxide transistor, a storage capacitor and a first voltage input bonding pad in a pixel driving circuit manufactured by adopting an LTPO technology are integrated on two sides of a flexible substrate to form a vertically stacked driving back plate structure; therefore, the area occupied by the pixel driving circuit can be reduced, the pixel density is improved, and the high-resolution LTPO driving backboard structure is realized. Moreover, the first polar plate of the storage capacitor is electrically connected with the first voltage input bonding pad through the first via hole penetrating through the flexible substrate, so that the storage capacitor is placed in the first via hole of the flexible substrate, the area of the storage capacitor is increased through the depth of the first via hole of the flexible substrate, and a vertical capacitor is formed. The area of the storage capacitor can be increased in a limited layout space, so that the performance of the LTPO driving backboard is improved.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and in particular to a display substrate and a display device. Background Art

[0002] With the rapid development of display technology, display devices have become increasingly ubiquitous in people's lives. Among them, light-emitting diode-based display panels (such as OLED and Micro-LED) are widely used in display devices such as mobile phones, televisions, and laptops due to their advantages such as self-luminescence, low power consumption, wide viewing angle, fast response speed, and high contrast.

[0003] However, in the related art, the pixel driving circuit of the display panel based on the light emitting diode occupies a large area, which is not conducive to improving the pixel density and the resolution of the display panel. Summary of the Invention

[0004] Embodiments of the present invention provide a display substrate and a display device, which are used to reduce the area occupied by a pixel driving circuit and improve the pixel density and the resolution of a display panel.

[0005] An embodiment of the present invention provides a display substrate, comprising a flexible substrate and a pixel driving circuit disposed on the flexible substrate, wherein the pixel driving circuit comprises a low-temperature polysilicon transistor, an oxide transistor, a storage capacitor, and a first voltage input pad, wherein the low-temperature polysilicon transistor, the oxide transistor, and the storage capacitor are disposed on a first side of the flexible substrate, and the first voltage input pad is disposed on a second side of the flexible substrate, wherein the first side and the second side are disposed opposite each other;

[0006] The first plate of the storage capacitor is electrically connected to the first voltage input pad through a first via hole penetrating the flexible substrate, and the second plate of the storage capacitor is electrically connected to the low-temperature polysilicon transistor.

[0007] Optionally, the display substrate provided in the embodiment of the present invention further includes: a first conductive layer provided on the first side of the flexible substrate, a barrier layer provided on a side of the first conductive layer facing away from the flexible substrate, and a second conductive layer provided on a side of the barrier layer facing away from the flexible substrate; wherein,

[0008] The first conductive layer includes a first plate of the storage capacitor, and the second conductive layer includes a second plate of the storage capacitor and a bottom gate of the low-temperature polysilicon transistor;

[0009] The barrier layer has a groove and a first flat portion surrounding the groove at a position corresponding to the first via hole, and the second electrode plate of the storage capacitor covers the bottom and sidewalls of the groove and a portion of the first flat portion.

[0010] Optionally, the above-mentioned display substrate provided in an embodiment of the present invention further includes a passivation layer arranged between the flexible substrate and the first conductive layer, the passivation layer having a second via hole and a second flat portion surrounding the second via hole at a position corresponding to the first via hole, the orthographic projection of the second via hole on the flexible substrate is located within the orthographic projection range of the first via hole on the flexible substrate, and the first plate of the storage capacitor is electrically connected to the first voltage input pad through the sleeve hole formed by the first via hole and the second via hole.

[0011] Optionally, in the above-mentioned display substrate provided by an embodiment of the present invention, the first electrode plate of the storage capacitor covers the bottom and sidewalls of the casing hole and covers a portion of the second flat portion.

[0012] Optionally, the display substrate provided in the embodiment of the present invention further includes: a first buffer layer provided on a side of the second conductive layer facing away from the flexible substrate, a low-temperature polycrystalline silicon semiconductor layer provided on a side of the first buffer layer facing away from the flexible substrate, a first gate insulating layer provided on a side of the low-temperature polycrystalline silicon semiconductor layer facing away from the flexible substrate, a third conductive layer provided on a side of the first gate insulating layer facing away from the flexible substrate, a second gate insulating layer provided on a side of the third conductive layer facing away from the flexible substrate, a fourth conductive layer provided on a side of the second gate insulating layer facing away from the flexible substrate, a first interlayer insulating layer provided on a side of the fourth conductive layer facing away from the flexible substrate, a second buffer layer provided on a side of the first interlayer insulating layer facing away from the flexible substrate, an oxide semiconductor layer provided on a side of the second buffer layer facing away from the flexible substrate, a third gate insulating layer provided on a side of the oxide semiconductor layer facing away from the flexible substrate, a fifth conductive layer provided on a side of the third gate insulating layer facing away from the flexible substrate, a second interlayer insulating layer provided on a side of the fifth conductive layer facing away from the flexible substrate, and a sixth conductive layer provided on a side of the second interlayer insulating layer facing away from the flexible substrate; wherein,

[0013] The low-temperature polysilicon semiconductor layer includes an active portion of the low-temperature polysilicon transistor, the third conductive layer includes a top gate of the low-temperature polysilicon transistor, the fourth conductive layer includes a bottom gate of the oxide transistor, the oxide semiconductor layer includes an active portion of the oxide transistor, the fifth conductive layer includes a top gate of the oxide transistor, and the sixth conductive layer includes a source and a drain of the low-temperature polysilicon transistor, a source and a drain of the oxide transistor, and a second voltage input pad;

[0014] A region of the second electrode plate of the storage capacitor covering the first flat portion is electrically connected to a top gate of the low-temperature polysilicon transistor.

[0015] Optionally, in the above-mentioned display substrate provided by an embodiment of the present invention, the display substrate further includes a data voltage pad provided on the same layer as the first voltage input pad, the first conductive layer further includes a first transition portion provided corresponding to the data voltage pad, and the third conductive layer further includes a second transition portion provided corresponding to the first transition portion; wherein,

[0016] One of the source electrodes of the sixth conductive layer is electrically connected to the second transfer portion through a via hole that sequentially penetrates the second interlayer insulating layer, the third gate insulating layer, the second buffer layer, the first interlayer insulating layer, and the second gate insulating layer; the second transfer portion is electrically connected to the first transfer portion through a via hole that sequentially penetrates the first gate insulating layer, the first buffer layer, and the barrier layer; and the first transfer portion is electrically connected to the data voltage pad through a via hole that sequentially penetrates the passivation layer and the flexible substrate.

[0017] Optionally, the display substrate provided in the embodiment of the present invention further includes: a rigid substrate provided on a side of the first voltage input pad facing away from the flexible substrate, and a seventh conductive layer provided on a side of the rigid substrate facing the first voltage input pad; wherein,

[0018] The seventh conductive layer includes a data line and a first power line. The data line is electrically connected to the data voltage pad, and the first power line is electrically connected to the first voltage input pad.

[0019] An embodiment of the present invention also provides a display substrate, comprising: a flexible substrate, a low-temperature polysilicon transistor and a storage capacitor arranged on a first side of the flexible substrate, a rigid substrate arranged on a second side of the flexible substrate, and an oxide transistor arranged on a side of the rigid substrate facing the flexible substrate; wherein the first side and the second side are arranged relative to each other, the oxide transistor and the low-temperature polysilicon transistor are interconnected through a via hole passing through the flexible substrate, and the low-temperature polysilicon transistor, the oxide transistor and the storage capacitor constitute a pixel driving circuit.

[0020] Optionally, the display substrate provided in the embodiment of the present invention further includes: a first conductive layer provided on the first side of the flexible substrate, a data voltage pad and at least one fourth transfer portion provided on the second side of the flexible substrate and arranged in the same layer, and a seventh conductive layer provided on the side of the oxide transistor facing the flexible substrate; the low-temperature polysilicon transistor is located on the side of the first conductive layer facing away from the flexible substrate; wherein,

[0021] The seventh conductive layer includes a data line and at least one fifth transfer portion, the data line is electrically connected to the data voltage pad, and the fifth transfer portion is electrically connected to the fourth transfer portion and the oxide transistor respectively;

[0022] The first conductive layer includes a plurality of sixth transfer portions, wherein a side of the sixth transfer portion facing away from the flexible substrate is electrically connected to the bottom gate of the low-temperature polysilicon transistor, and a side of the sixth transfer portion facing the flexible substrate is electrically connected to the fourth transfer portion through a first via hole penetrating the flexible substrate.

[0023] Optionally, the above-mentioned display substrate provided in an embodiment of the present invention further includes a passivation layer arranged between the flexible substrate and the first conductive layer, the passivation layer has a second via at a position corresponding to the first via, the orthographic projection of the second via on the flexible substrate is located within the orthographic projection range of the first via on the flexible substrate, and the sixth adapter is electrically connected to the fourth adapter through a sleeve hole formed by the first via and the second via.

[0024] Optionally, the display substrate provided in the embodiment of the present invention further includes: a barrier layer provided on a side of the first conductive layer facing away from the flexible substrate, a second conductive layer provided on a side of the barrier layer facing away from the flexible substrate, a first buffer layer provided on a side of the second conductive layer facing away from the flexible substrate, a low-temperature polycrystalline silicon semiconductor layer provided on a side of the first buffer layer facing away from the flexible substrate, a first gate insulating layer provided on a side of the low-temperature polycrystalline silicon semiconductor layer facing away from the flexible substrate, a third conductive layer provided on a side of the first gate insulating layer facing away from the flexible substrate, a second gate insulating layer provided on a side of the third conductive layer facing away from the flexible substrate, a fourth conductive layer provided on a side of the second gate insulating layer facing away from the flexible substrate, a first interlayer insulating layer provided on a side of the fourth conductive layer facing away from the flexible substrate, and a sixth conductive layer provided on a side of the first interlayer insulating layer facing away from the flexible substrate; wherein,

[0025] The second conductive layer includes a bottom gate of the low-temperature polysilicon transistor, the low-temperature polysilicon semiconductor layer includes an active portion of the low-temperature polysilicon transistor, the third conductive layer includes a top gate of the low-temperature polysilicon transistor and a second plate of the storage capacitor, the fourth conductive layer includes a first plate of the storage capacitor, and the sixth conductive layer includes a source and a drain of the low-temperature polysilicon transistor and a first voltage input pad and a second voltage input pad;

[0026] The first electrode plate of the storage capacitor is electrically connected to the first voltage input pad.

[0027] Optionally, in the display substrate provided by an embodiment of the present invention, the first conductive layer further includes a first transition portion provided corresponding to the data voltage pad, the second conductive layer further includes a seventh transition portion provided corresponding to the first transition portion, and the third conductive layer further includes a second transition portion provided corresponding to the seventh transition portion; wherein,

[0028] One of the source electrodes of the sixth conductive layer is electrically connected to the second transfer portion through a via hole sequentially penetrating the first interlayer insulating layer and the second gate insulating layer, the second transfer portion is electrically connected to the seventh transfer portion through a via hole sequentially penetrating the first gate insulating layer and the first buffer layer, the seventh transfer portion is electrically connected to the first transfer portion through a via hole penetrating the barrier layer, and the first transfer portion is electrically connected to the data voltage pad through a via hole sequentially penetrating the passivation layer and the flexible substrate.

[0029] Optionally, in the above-mentioned display substrate provided by an embodiment of the present invention, the display substrate further includes: an eighth conductive layer provided between the rigid substrate and the seventh conductive layer, a second buffer layer provided between the eighth conductive layer and the seventh conductive layer, an oxide semiconductor layer provided between the second buffer layer and the seventh conductive layer, a third gate insulating layer provided between the oxide semiconductor layer and the seventh conductive layer, a fifth conductive layer provided between the third gate insulating layer and the seventh conductive layer, and a second interlayer insulating layer provided between the fifth conductive layer and the seventh conductive layer; wherein,

[0030] The eighth conductive layer includes a bottom gate of the oxide transistor, the oxide semiconductor layer includes an active portion of the oxide transistor, and the fifth conductive layer includes a top gate of the oxide transistor;

[0031] The fifth transfer portion is electrically connected to at least one of a bottom gate, a top gate, and an active portion of the oxide transistor.

[0032] Correspondingly, an embodiment of the present invention further provides a display device, comprising the above-mentioned display substrate provided by an embodiment of the present invention.

[0033] The beneficial effects of the embodiments of the present invention are as follows:

[0034] Embodiments of the present invention provide a display substrate and display device that integrates low-temperature polysilicon transistors, oxide transistors, storage capacitors, and first voltage input pads in a pixel drive circuit fabricated using LTPO technology on both sides of a flexible substrate to form a vertically stacked drive backplane structure. This reduces the area occupied by the pixel drive circuit and increases pixel density, thereby achieving a high-resolution LTPO drive backplane structure. Furthermore, because the first plate of the storage capacitor is electrically connected to the first voltage input pad via a first via extending through the flexible substrate, placing the storage capacitor within the first via in the flexible substrate increases the area of ​​the storage capacitor by the depth of the first via in the flexible substrate, forming a vertical capacitor. This increases the area of ​​the storage capacitor within a limited layout space, thereby improving the performance of the LTPO drive backplane. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] Figure 1 A schematic diagram of a cross-sectional structure of a display substrate provided by an embodiment of the present invention;

[0036] Figure 2A-2J Made for the embodiment of the present invention Figure 1 The structure diagram of the display substrate after each step is performed is shown;

[0037] Figure 3 A schematic diagram of another cross-sectional structure of a display substrate provided by an embodiment of the present invention;

[0038] Figures 4A-4L Made for the embodiment of the present invention Figure 3 The diagram shows the structure of the display substrate after each step is performed. DETAILED DESCRIPTION

[0039] In order to make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings of the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. And in the absence of conflict, the embodiments of the present invention and the features in the embodiments can be combined with each other. Based on the described embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0040] Unless otherwise defined, the technical or scientific terms used in the present invention shall have the usual meanings understood by persons of ordinary skill in the field to which the present invention belongs. The words “include” or “comprise” and the like used in the present invention mean that the elements or objects preceding the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Words such as “connect” or “connected” and the like are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. “Inside”, “outside”, “upper”, “lower”, etc. are only used to indicate relative positional relationships. When the absolute position of the object being described changes, the relative positional relationship may also change accordingly.

[0041] It should be noted that the sizes and shapes of the figures in the accompanying drawings, unless otherwise specified, do not reflect the actual scale and are intended only to illustrate the present invention. The same or similar reference numerals throughout the drawings represent the same or similar elements or elements having the same or similar functions.

[0042] An embodiment of the present invention provides a display substrate, such as Figure 1 As shown, it includes a flexible substrate 1 and a pixel driving circuit arranged on the flexible substrate 1, the pixel driving circuit includes a low-temperature polysilicon transistor 2 (LTPS TFT), an oxide transistor 3 (Oxide TFT), a storage capacitor 4 and a first voltage input pad 5, the low-temperature polysilicon transistor 2, the oxide transistor 3 and the storage capacitor 4 are arranged on a first side of the flexible substrate 1, and the first voltage input pad 5 is arranged on a second side of the flexible substrate 1, and the first side and the second side are arranged opposite to each other; wherein,

[0043] The first plate 41 of the storage capacitor 4 is electrically connected to the first voltage input pad 5 through a first via V1 penetrating the flexible substrate 1 , and the second plate 42 of the storage capacitor 4 is electrically connected to the low-temperature polysilicon transistor 2 .

[0044] Specifically, the active layer of low-temperature polysilicon transistors uses low-temperature polysilicon (LTPS), which has advantages such as high mobility and fast charging. The active layer of oxide transistors uses oxide semiconductors (Oxide), such as indium gallium zinc oxide and indium gallium tin oxide. Oxide transistors have advantages such as low leakage current. Based on this, low-temperature polysilicon transistors and oxide transistors are integrated on a display substrate to form a low-temperature polycrystalline oxide (LTPO) display substrate. This can take advantage of the advantages of both, reduce leakage current, lower power consumption, achieve low-frequency drive, and improve display quality.

[0045] Specifically, the first voltage input pad 5 may be a high voltage input pad, used to input the high voltage on the first power line VDD to the pixel driving circuit.

[0046] The display substrate provided by an embodiment of the present invention integrates the low-temperature polysilicon transistors, oxide transistors, storage capacitors, and first voltage input pads in a pixel drive circuit fabricated using LTPO technology on both sides of a flexible substrate, forming a vertically stacked drive backplane structure. This reduces the area occupied by the pixel drive circuit and increases pixel density, thereby achieving a high-resolution LTPO drive backplane structure. Furthermore, since the first plate of the storage capacitor is electrically connected to the first voltage input pad via a first via extending through the flexible substrate, placing the storage capacitor within the first via in the flexible substrate increases the area of ​​the storage capacitor by the depth of the first via in the flexible substrate, forming a vertical capacitor. This increases the area of ​​the storage capacitor within a limited layout space, thereby improving the performance of the LTPO drive backplane.

[0047] In some embodiments, in the above-mentioned display substrate provided by the embodiment of the present invention, as Figure 1 As shown, it also includes: a first conductive layer M1 arranged on a first side of the flexible substrate 1, a barrier layer 6 arranged on a side of the first conductive layer M1 facing away from the flexible substrate 1, and a second conductive layer M2 arranged on a side of the barrier layer 6 facing away from the flexible substrate 1; wherein,

[0048] The first conductive layer M1 includes a first electrode plate 41 of the storage capacitor 4, and the second conductive layer M2 includes a second electrode plate 42 of the storage capacitor 4 and a bottom gate 21 of the low-temperature polysilicon transistor 2. The bottom gate 21 can also serve as a light shield to reduce the risk of threshold voltage shift of the low-temperature polysilicon transistor 2 under exposure to ambient light.

[0049] The barrier layer 6 has a groove 61 and a first flat portion 62 surrounding the groove 61 at a position corresponding to the first via hole V1. The second electrode 42 of the storage capacitor 4 covers the bottom and side walls of the groove 61 and covers part of the first flat portion 62. In this way, the first electrode 41 of the storage capacitor 4 is placed in the first via hole V1 of the flexible substrate 1, and the area of ​​the first electrode 41 is increased by the depth of the first via hole V1 of the flexible substrate 1. The second electrode 42 of the storage capacitor 4 is placed in the groove 61, and the area of ​​the second electrode 42 is increased by the depth of the groove 61. The area of ​​the storage capacitor 4 can be increased within a limited layout space, thereby improving the performance of the LTPO drive backplane.

[0050] Specifically, the material of the first conductive layer M1 and the second conductive layer M2 includes a metal material. For example, the material of the first conductive layer M1 and the second conductive layer M2 includes at least one of molybdenum, magnesium, aluminum, copper, and titanium.

[0051] Specifically, the barrier layer 6 can play a role in preventing water oxygen corrosion, and the material of the barrier layer 6 includes any one of silicon nitride, silicon oxide and silicon oxynitride.

[0052] In some embodiments, in order to improve the adhesion between the first conductive layer and the flexible substrate, in the above-mentioned display substrate provided by the embodiment of the present invention, as Figure 1 As shown, the present invention further includes a passivation layer 7 disposed between the flexible substrate 1 and the first conductive layer M1. The passivation layer 7 has a second via hole V2 and a second flat portion 71 surrounding the second via hole V2 at a position corresponding to the first via hole V1. The orthographic projection of the second via hole V2 on the flexible substrate 1 is located within the orthographic projection range of the first via hole V1 on the flexible substrate 1. The first electrode 41 of the storage capacitor 4 is electrically connected to the first voltage input pad 5 through the sleeve hole V formed by the first via hole V1 and the second via hole V2.

[0053] Specifically, the material of the passivation layer 7 includes any one of silicon nitride, silicon oxide and silicon oxynitride.

[0054] In some embodiments, in the above-mentioned display substrate provided by the embodiment of the present invention, as Figure 1 As shown, the first electrode plate 41 of the storage capacitor 4 covers the bottom and sidewalls of the sleeve hole V and covers part of the second flat portion 71. In this way, the first electrode plate 41 of the storage capacitor 4 is placed in the sleeve hole V, and the area of ​​the first electrode plate 41 is increased by the depth of the sleeve hole V.

[0055] In some embodiments, in the above-mentioned display substrate provided by the embodiment of the present invention, as Figure 1 As shown, it also includes: a first buffer layer 8 arranged on the side of the second conductive layer M2 facing away from the flexible substrate 1, a low-temperature polycrystalline silicon semiconductor layer 9 arranged on the side of the first buffer layer 8 facing away from the flexible substrate 1, a first gate insulating layer GI1 arranged on the side of the low-temperature polycrystalline silicon semiconductor layer 9 facing away from the flexible substrate 1, a third conductive layer M3 arranged on the side of the first gate insulating layer GI1 facing away from the flexible substrate 1, a second gate insulating layer GI2 arranged on the side of the third conductive layer M3 facing away from the flexible substrate 1, a fourth conductive layer M4 arranged on the side of the second gate insulating layer GI2 facing away from the flexible substrate 1, and a second conductive layer M5 arranged on the side of the fourth conductive layer M5 facing away from the flexible substrate 1. a first interlayer insulating layer ILD1, a second buffer layer 10 provided on a side of the first interlayer insulating layer ILD1 facing away from the flexible substrate 1, an oxide semiconductor layer 20 provided on a side of the second buffer layer 10 facing away from the flexible substrate 1, a third gate insulating layer GI3 provided on a side of the oxide semiconductor layer 20 facing away from the flexible substrate 1, a fifth conductive layer M5 provided on a side of the third gate insulating layer GI3 facing away from the flexible substrate 1, a second interlayer insulating layer ILD2 provided on a side of the fifth conductive layer M5 facing away from the flexible substrate 1, and a sixth conductive layer M6 provided on a side of the second interlayer insulating layer ILD2 facing away from the flexible substrate 1; wherein,

[0056] The low-temperature polysilicon semiconductor layer 9 includes an active portion 22 of the low-temperature polysilicon transistor 2. The third conductive layer M3 includes a top gate 23 of the low-temperature polysilicon transistor 2, so that the low-temperature polysilicon transistor 2 forms a dual-gate structure, reducing the risk of leakage current in the low-temperature polysilicon transistor 2. The fourth conductive layer M4 includes a bottom gate 31 of the oxide transistor 3. The oxide semiconductor layer 20 includes an active portion 32 of the oxide transistor 3. The fifth conductive layer M5 includes a top gate 33 of the oxide transistor 3, so that the oxide transistor 3 forms a dual-gate structure, reducing the risk of leakage current in the oxide transistor 3. The sixth conductive layer M6 includes a source S and a drain D of the low-temperature polysilicon transistor 2, a source S and a drain D of the oxide transistor 3, and a second voltage input pad 30.

[0057] The region of the second plate 42 of the storage capacitor 4 that covers the first flat portion 62 is electrically connected to the top gate 23 of the low-temperature polysilicon transistor 2 .

[0058] Specifically, the second voltage input pad 30 may be a low voltage input pad for inputting the low voltage on the second power line VSS to the cathode of the light emitting device.

[0059] Specifically, the materials of the third conductive layer M3, the fourth conductive layer M4, the fifth conductive layer M5 and the sixth conductive layer M6 include metal materials. For example, the materials of the third conductive layer M3, the fourth conductive layer M4, the fifth conductive layer M5 and the sixth conductive layer M6 include at least one of molybdenum, magnesium, aluminum, copper and titanium.

[0060] Specifically, the first buffer layer 8 and the second buffer layer 10 can play a buffering role, and the material of the first buffer layer 8 and the second buffer layer 10 includes any one of silicon nitride, silicon oxide and silicon oxynitride.

[0061] Specifically, the material of the first gate insulating layer GI1 , the second gate insulating layer GI2 , and the third gate insulating layer GI3 includes any one of silicon nitride, silicon oxide, and silicon oxynitride.

[0062] In some embodiments, as Figure 1As shown, the structure of the pixel driving circuit in the embodiment of the present invention includes multiple structures, which can be selected and set according to actual needs. For example, the structure of the pixel driving circuit may include "2T1C", "3T1C", "6T1C", "7T1C", "6T2C" or "7T2C" structures. Among them, "T" represents a transistor, and the number before "T" represents the number of transistors. "C" represents a storage capacitor, and the number before "C" represents the number of storage capacitors. The embodiment of the present invention primarily disposes the first voltage input pad 5 on the second side (back side) of the flexible substrate 1, thereby reducing the area occupied by the pixel driving circuit and increasing the pixel density, thereby realizing a high-resolution LTPO driving backplane structure. Furthermore, the first electrode 41 of the storage capacitor 4 is placed within the first via V1 of the flexible substrate 1, and the area of ​​the first electrode 41 is increased by the depth of the first via V1 of the flexible substrate 1. The second electrode 42 of the storage capacitor 4 is placed within the groove 61, and the area of ​​the second electrode 42 is increased by the depth of the groove 61. This can increase the area of ​​the storage capacitor 4 within a limited layout space, thereby improving the performance of the LTPO driving backplane. The number of low-temperature polysilicon transistors 2 and oxide transistors 3 can be designed according to the structure of the pixel driving circuit, and a stacked structure of the low-temperature polysilicon transistors 2 and oxide transistors 3 can be designed, for example, the orthographic projections of the active portion 22 of the low-temperature polysilicon transistor 2 and the active portion 32 of the oxide transistor 3 on the flexible substrate 1 at least partially overlap, thereby further reducing the area occupied by the pixel driving circuit, increasing the pixel density, and thus improving the resolution of the display substrate.

[0063] In some embodiments, in the above-mentioned display substrate provided by the embodiment of the present invention, as Figure 1 As shown, the display substrate further includes a data voltage pad 40 provided on the same layer as the first voltage input pad 5, the first conductive layer M1 further includes a first transfer portion 50 provided corresponding to the data voltage pad 40, and the third conductive layer M3 further includes a second transfer portion 60 provided corresponding to the first transfer portion 50; wherein,

[0064] A source electrode S of the sixth conductive layer M6 is electrically connected to the second transfer portion 60 via a via hole that sequentially penetrates the second interlayer insulating layer ILD2, the third gate insulating layer GI3, the second buffer layer 10, the first interlayer insulating layer ILD1, and the second gate insulating layer GI2. The second transfer portion 60 is electrically connected to the first transfer portion 50 via a via hole that sequentially penetrates the first gate insulating layer GI1, the first buffer layer 8, and the barrier layer 6. The first transfer portion 50 is electrically connected to the data voltage pad 40 via a via hole that sequentially penetrates the passivation layer 7 and the flexible substrate 1. In this way, the data voltage is transmitted to the pixel driving circuit through the data voltage pad 40, the first transfer portion 50, the second transfer portion 60, and the source electrode S in sequence.

[0065] In some embodiments, in the above-mentioned display substrate provided by the embodiment of the present invention, as Figure 1 As shown, it also includes: a rigid substrate 70 arranged on the side of the first voltage input pad 5 away from the flexible substrate 1, and a seventh conductive layer M7 arranged on the side of the rigid substrate 70 facing the first voltage input pad 5; wherein,

[0066] The seventh conductive layer M7 includes a data line 80 and a first power line VDD. The data line 80 is electrically connected to the data voltage pad 40, and the first power line VDD is electrically connected to the first voltage input pad 5. Specifically, the rigid substrate 70 and the seventh conductive layer M7 in the display substrate provided in the embodiment of the present invention can constitute a PM backplane, while the remaining structure constitutes an AM backplane. In this way, IC signals are transmitted via the PM backplane to the pixel drive circuits of the independent pixel islands on the AM backplane, realizing a combined PM+AM independent pixel island drive mode.

[0067] The following embodiments of the present invention provide Figure 1 The manufacturing method of the display substrate shown in FIG. 1 is described, which specifically includes the following manufacturing steps:

[0068] (1) A metal material is deposited, arranged, and etched on a glass substrate 100 coated with a release layer to form a data voltage pad 40 and a first voltage input pad 5. The metal material may be Ti, Ti / Al, or Mo, and the thickness may be in the range of 500 angstroms to 5000 angstroms. A flexible substrate material is then coated on the data voltage pad 40 and the first voltage input pad 5 and cured to form a flexible substrate 1. A passivation layer 7 is then deposited on the flexible substrate 1. The passivation layer 7 and the flexible substrate 1 are then punched. The punching process may be a photoresist process or a hard-mask process. A first metal layer M1 is then formed on the passivation layer 7. The first metal layer M1 includes a first transition portion 50 and a first electrode 41, as shown in FIG. Figure 2A shown.

[0069] (2) forming a barrier layer 6 on the first metal layer M1, and then forming a second metal layer M2 on the barrier layer 6, wherein the second metal layer M2 includes the bottom gate 21 of the low-temperature polysilicon transistor 2 and the second electrode 42 of the storage capacitor 4, as shown in FIG. Figure 2B shown.

[0070] (3) forming a first buffer layer 8 on the second metal layer M2, forming a low-temperature polysilicon semiconductor layer 9 on the first buffer layer 8, the low-temperature polysilicon semiconductor layer 9 including the active portion 22 of the low-temperature polysilicon transistor 2, and then forming a first gate insulating layer GI1 on the low-temperature polysilicon semiconductor layer 9, and punching the first gate insulating layer GI1, the first buffer layer 8 and the barrier layer 6 to form a via hole corresponding to the first transfer portion 50 and a via hole corresponding to the second electrode 42, as shown in FIG. Figure 2C shown.

[0071] (4) A third conductive layer M3 is formed on the first gate insulating layer GI1. The third conductive layer M3 includes the top gate 23 of the low-temperature polysilicon transistor 2, the second transfer portion 60, and the metal pad at the interconnection, such as Figure 2D shown.

[0072] (5) A second gate insulating layer GI2 is formed on the third conductive layer M3, and a fourth conductive layer M4 is formed on the second gate insulating layer GI2. The fourth conductive layer M4 includes the bottom gate 31 of the oxide transistor 3. Since the storage capacitor 4 has been formed by the first conductive layer M1 and the second conductive layer M2, the fourth conductive layer M4 only serves as the bottom gate 31 of the oxide transistor 3. Figure 2E shown.

[0073] (6) forming a first interlayer insulating layer ILD1 on the fourth conductive layer M4, forming a second buffer layer 10 on the first interlayer insulating layer ILD1, and forming an oxide semiconductor layer 20 on the second buffer layer 10, wherein the oxide semiconductor layer 20 includes an active portion 32 of the oxide transistor 3, as shown in FIG. Figure 2F shown.

[0074] (7) forming a third gate insulating layer GI3 on ​​the oxide semiconductor layer 20, forming a fifth conductive layer M5 on the third gate insulating layer GI3, forming a second interlayer insulating layer ILD2 on the fifth conductive layer M5, and forming a sixth conductive layer M6 on the second interlayer insulating layer ILD2, wherein the fifth conductive layer M5 includes the top gate 33 of the oxide transistor 3, and the sixth conductive layer M6 includes the source S and drain D of the low-temperature polysilicon transistor 2, the source S and drain D of the oxide transistor 3, and the second voltage input pad 30, as shown in FIG. Figure 2G shown.

[0075] (8) Figure 2H As shown, laser technology can be used to Figure 2G The glass substrate 100 is peeled off to obtain Figure 2I The structure shown forms an AM backplane.

[0076] (9) A seventh conductive layer M7 is formed on the rigid substrate 70. The seventh conductive layer M7 includes the data line 80 and the first power line VDD to form a PM backplane. Figure 2J shown.

[0077] (10) Figure 2J The PM backplane shown is Figure 2I The AM backplane shown is bonded so that the data line 80 is electrically connected to the data voltage pad 40, and the first power line VDD is electrically connected to the first voltage input pad 5. Figure 1 shown.

[0078] The embodiment of the present invention further provides a display substrate, such as Figure 3 As shown, it includes: a flexible substrate 1, a low-temperature polysilicon transistor 2 and a storage capacitor 4 arranged on a first side of the flexible substrate 1, a rigid substrate 70 arranged on a second side of the flexible substrate 1, and an oxide transistor 3 arranged on a side of the rigid substrate 70 facing the flexible substrate 1; wherein the first side and the second side are arranged opposite to each other, the oxide transistor 3 and the low-temperature polysilicon transistor 2 are interconnected through a via hole penetrating the flexible substrate 1, and the low-temperature polysilicon transistor 2, the oxide transistor 3 and the storage capacitor 4 constitute a pixel driving circuit.

[0079] The above-mentioned display substrate provided by an embodiment of the present invention integrates the low-temperature polysilicon transistors, storage capacitors and oxide transistors in the pixel driving circuit manufactured using LTPO technology on both sides of the flexible substrate. For example, the low-temperature polysilicon transistors and storage capacitors are integrated on the front side of the flexible substrate, and the oxide transistors are integrated on the back side of the flexible substrate to form a vertically stacked driving backplane structure. This can reduce the area occupied by the pixel driving circuit and increase the pixel density, thereby realizing a high-resolution LTPO driving backplane structure; and the low-temperature polysilicon transistors and the oxide transistors can be manufactured on different substrates respectively and then bonded together. Therefore, the process flows for manufacturing the low-temperature polysilicon transistors and the oxide transistors do not affect each other, so the film deposition conditions and process flows that are optimal for the characteristics of the oxide transistors can be selected, as well as the backplane stacking structure and flow that are optimal for the characteristics of the low-temperature polysilicon transistors can be selected without considering the characteristics of the oxide transistors, thereby improving the performance of the display substrate.

[0080] In some embodiments, in the above-mentioned display substrate provided by the embodiment of the present invention, as Figure 3 As shown, it also includes: a first conductive layer M1 provided on the first side of the flexible substrate 1, a data voltage pad 40 and at least one fourth transfer portion 90 provided on the second side of the flexible substrate 1 and in the same layer, and a seventh conductive layer M7 provided on the side of the oxide transistor 3 facing the flexible substrate 1; the low-temperature polysilicon transistor 2 is located on the side of the first conductive layer M1 facing away from the flexible substrate 1; wherein,

[0081] The seventh conductive layer M7 includes a data line 80 and at least one fifth transfer portion 200 . The data line 80 is electrically connected to the data voltage pad 40 . The fifth transfer portion 200 is electrically connected to the fourth transfer portion 90 and the oxide transistor 3 , respectively.

[0082] The first conductive layer M1 includes multiple sixth transition portions 300. The side of the sixth transition portion 300 facing away from the flexible substrate 1 is electrically connected to the bottom gate 21 of the low-temperature polysilicon transistor 2. The side of the sixth transition portion 300 facing the flexible substrate 1 is electrically connected to the fourth transition portion 90 via a first via V1 that penetrates the flexible substrate 1. In this way, the oxide transistor 3 is electrically connected to the bottom gate 21 of the low-temperature polysilicon transistor 2 via the fifth transition portion 200, the fourth transition portion 90, and the sixth transition portion 300 in sequence, thereby interconnecting the oxide transistor 3 and the low-temperature polysilicon transistor 2.

[0083] In some embodiments, in order to improve the adhesion between the first conductive layer and the flexible substrate, in the above-mentioned display substrate provided by the embodiment of the present invention, as Figure 3 As shown, the present invention further includes a passivation layer 7 disposed between the flexible substrate 1 and the first conductive layer M1. The passivation layer 7 has a second via hole V2 at a position corresponding to the first via hole V1. The orthographic projection of the second via hole V2 on the flexible substrate 1 is located within the range of the orthographic projection of the first via hole V1 on the flexible substrate 1. The sixth adapter 300 is electrically connected to the fourth adapter 90 via a sleeve hole V formed by the first via hole V1 and the second via hole V2.

[0084] Specifically, the material of the passivation layer 7 includes any one of silicon nitride, silicon oxide and silicon oxynitride.

[0085] In some embodiments, in the above-mentioned display substrate provided by the embodiment of the present invention, as Figure 3 As shown, the present invention further includes: a barrier layer 6 disposed on a side of the first conductive layer M1 facing away from the flexible substrate 1, a second conductive layer M2 disposed on a side of the barrier layer 6 facing away from the flexible substrate 1, a first buffer layer 8 disposed on a side of the second conductive layer M2 facing away from the flexible substrate 1, a low-temperature polycrystalline silicon semiconductor layer 9 disposed on a side of the first buffer layer 8 facing away from the flexible substrate 1, a first gate insulating layer GI1 disposed on a side of the low-temperature polycrystalline silicon semiconductor layer 9 facing away from the flexible substrate 1, a third conductive layer M3 disposed on a side of the first gate insulating layer GI1 facing away from the flexible substrate 1, a second gate insulating layer GI2 disposed on a side of the third conductive layer M3 facing away from the flexible substrate 1, a fourth conductive layer M4 disposed on a side of the second gate insulating layer GI2 facing away from the flexible substrate 1, a first interlayer insulating layer ILD1 disposed on a side of the fourth conductive layer M4 facing away from the flexible substrate 1, and a sixth conductive layer M6 disposed on a side of the first interlayer insulating layer ILD1 facing away from the flexible substrate 1; wherein,

[0086] The second conductive layer M2 includes the bottom gate 21 of the low-temperature polysilicon transistor 2, the low-temperature polysilicon semiconductor layer 9 includes the active portion 22 of the low-temperature polysilicon transistor 2, the third conductive layer M3 includes the top gate 23 of the low-temperature polysilicon transistor 2 and the second electrode plate 42 of the storage capacitor 4, so that the low-temperature polysilicon transistor 2 forms a dual-gate structure, reducing the risk of leakage current of the low-temperature polysilicon transistor 2, wherein the bottom gate 21 can also play a light-shielding role, reducing the risk of threshold voltage shift of the low-temperature polysilicon transistor 2 under the irradiation of external ambient light, the fourth conductive layer M4 includes the first electrode plate 41 of the storage capacitor 4, and the sixth conductive layer M6 includes the source S and drain D of the low-temperature polysilicon transistor 2 and the first voltage input pad 5 and the second voltage input pad 30;

[0087] The first electrode 41 of the storage capacitor 4 is electrically connected to the first voltage input pad 5 .

[0088] Specifically, the first voltage input pad 5 can be a high voltage input pad, used to input the high voltage on the first power line VDD to the pixel driving circuit; the second voltage input pad 30 can be a low voltage input pad, used to input the low voltage on the second power line VSS to the cathode of the light-emitting device.

[0089] Specifically, the materials of the first conductive layer M1, the second conductive layer M2, the third conductive layer M3, the fourth conductive layer M4, the fifth conductive layer M5 and the sixth conductive layer M6 include metal materials. For example, the materials of the first conductive layer M1, the second conductive layer M2, the third conductive layer M3, the fourth conductive layer M4, the fifth conductive layer M5 and the sixth conductive layer M6 include at least one of molybdenum, magnesium, aluminum, copper and titanium.

[0090] Specifically, the barrier layer 6 can play a role in preventing water oxygen corrosion, and the material of the barrier layer 6 includes any one of silicon nitride, silicon oxide and silicon oxynitride.

[0091] Specifically, the first buffer layer 8 and the second buffer layer 10 can play a buffering role, and the material of the first buffer layer 8 and the second buffer layer 10 includes any one of silicon nitride, silicon oxide and silicon oxynitride.

[0092] Specifically, the material of the first gate insulating layer GI1 , the second gate insulating layer GI2 , and the third gate insulating layer GI3 includes any one of silicon nitride, silicon oxide, and silicon oxynitride.

[0093] In some embodiments, in the above-mentioned display substrate provided by the embodiment of the present invention, as Figure 3 As shown, the first conductive layer M1 further includes a first transition portion 50 corresponding to the data voltage pad 40, the second conductive layer M2 further includes a seventh transition portion 400 corresponding to the first transition portion 50, and the third conductive layer M3 further includes a second transition portion 60 corresponding to the seventh transition portion 400; wherein,

[0094] A source electrode S of the sixth conductive layer M6 is electrically connected to the second transfer portion 60 via a via hole sequentially penetrating the first interlayer insulating layer ILD1 and the second gate insulating layer GI2. The second transfer portion 60 is electrically connected to the seventh transfer portion 400 via a via hole sequentially penetrating the first gate insulating layer GI1 and the first buffer layer 8. The seventh transfer portion 400 is electrically connected to the first transfer portion 50 via a via hole penetrating the barrier layer 6. The first transfer portion 50 is electrically connected to the data voltage pad 40 via a via hole sequentially penetrating the passivation layer 7 and the flexible substrate 1. In this manner, the data voltage is transmitted to the pixel driving circuit via the data line 80, the data voltage pad 40, the first transfer portion 50, the seventh transfer portion 400, the second transfer portion 60, and the source electrode S.

[0095] In some embodiments, in the above-mentioned display substrate provided by the embodiment of the present invention, as Figure 3 As shown, the present invention further includes: an eighth conductive layer M8 disposed between the rigid substrate 70 and the seventh conductive layer M7, a second buffer layer 10 disposed between the eighth conductive layer M8 and the seventh conductive layer M7, an oxide semiconductor layer 20 disposed between the second buffer layer 10 and the seventh conductive layer M7, a third gate insulating layer GI3 disposed between the oxide semiconductor layer 20 and the seventh conductive layer M7, a fifth conductive layer M5 disposed between the third gate insulating layer GI3 and the seventh conductive layer M7, and a second interlayer insulating layer GI2 disposed between the fifth conductive layer M5 and the seventh conductive layer M7; wherein,

[0096] The eighth conductive layer M8 includes the bottom gate 31 of the oxide transistor 3, the oxide semiconductor layer 20 includes the active portion 32 of the oxide transistor 3, and the fifth conductive layer M5 includes the top gate 33 of the oxide transistor 3, so that the oxide transistor 3 forms a dual-gate structure, reducing the risk of leakage current in the oxide transistor 3;

[0097] The fifth transfer portion 200 is electrically connected to at least one of the bottom gate 31 , the top gate 33 , and the active portion 32 of the oxide transistor 3 .

[0098] In some embodiments, as Figure 3As shown, the structure of the pixel driving circuit in the embodiment of the present invention includes multiple structures, which can be selected and set according to actual needs. For example, the structure of the pixel driving circuit may include "2T1C", "3T1C", "6T1C", "7T1C", "6T2C" or "7T2C" structures. Among them, "T" represents a transistor, and the number before "T" represents the number of transistors. "C" represents a storage capacitor, and the number before "C" represents the number of storage capacitors. The embodiment of the present invention mainly arranges the low-temperature polysilicon transistor 2 on the first side (front side) of the flexible substrate 1, and arranges the oxide transistor 3 on the second side (back side) of the flexible substrate 1, which can reduce the area occupied by the pixel driving circuit and improve the pixel density, thereby realizing a high-resolution LTPO driving backplane structure; wherein, the number of the low-temperature polysilicon transistor 2 and the oxide transistor 3 can be designed according to the structure of the pixel driving circuit, and a structure in which the low-temperature polysilicon transistor 2 and the oxide transistor 3 are stacked can be designed, for example, the active part 22 of the low-temperature polysilicon transistor 2 and the active part 32 of the oxide transistor 3 have at least partially overlapping orthographic projections on the flexible substrate 1, so as to further reduce the area occupied by the pixel driving circuit, improve the pixel density, and thus improve the resolution of the display substrate.

[0099] The following embodiments of the present invention provide Figure 3 The manufacturing method of the display substrate shown in FIG. 1 is described, which specifically includes the following manufacturing steps:

[0100] (1) A metal material is deposited, arranged, and etched on a glass substrate 100 coated with a release layer to form a data voltage pad 40 and a fourth transition portion 90. The metal material may be Ti, Ti / Al, or Mo, and the thickness may be in the range of 500 angstroms to 5000 angstroms. A flexible substrate material is then coated on the data voltage pad 40 and the fourth transition portion 90 and cured to form a flexible substrate 1. A passivation layer 7 is then deposited on the flexible substrate 1. The passivation layer 7 and the flexible substrate 1 are then punched. The punching process may be a photoresist process or a hard-mask process. A first metal layer M1 is then formed on the passivation layer 7. The first metal layer M1 includes a first transition portion 50 and a sixth transition portion 300. Figure 4A shown.

[0101] (2) forming a barrier layer 6 on the first metal layer M1 and punching holes in the barrier layer 6, such as Figure 4B shown.

[0102] (3) A second metal layer M2 is formed on the barrier layer 6. The second metal layer M2 includes the bottom gate 21 of the low-temperature polysilicon transistor 2 and the seventh transfer portion 400. Figure 4C shown.

[0103] (4) forming a first buffer layer 8 on the second metal layer M2, and forming a low-temperature polysilicon semiconductor layer 9 on the first buffer layer 8, wherein the low-temperature polysilicon semiconductor layer 9 includes an active portion 22 of the low-temperature polysilicon transistor 2, as shown in FIG. Figure 4D shown.

[0104] (5) forming a first gate insulating layer GI1 on the low-temperature polysilicon semiconductor layer 9, and punching the first gate insulating layer GI1 and the first buffer layer 8 to form a via hole corresponding to the seventh transfer portion 400 and a via hole corresponding to the bottom gate 21 of the low-temperature polysilicon transistor 2, as shown in FIG. Figure 4E shown.

[0105] (6) A third conductive layer M3 is formed on the first gate insulating layer GI1. The third conductive layer M3 includes the top gate 23 of the low-temperature polysilicon transistor 2, the second transfer portion 60, and the second plate 42 of the storage capacitor 4. Figure 4F shown.

[0106] (7) A second gate insulating layer GI2 is formed on the third conductive layer M3, a fourth conductive layer M4 is formed on the second gate insulating layer GI2, a first interlayer insulating layer ILD1 is formed on the fourth conductive layer M4, and a sixth conductive layer M6 is formed on the first interlayer insulating layer ILD1. The fourth conductive layer M4 includes the first electrode 41 of the storage capacitor 4. Since the oxide transistor 3 has been transferred to the rigid substrate 70, the fourth conductive layer M4 only serves as the first electrode 41 of the storage capacitor 4. The sixth conductive layer M6 includes the source S and drain D of the low-temperature polysilicon transistor 2, the first voltage input pad 5, and the second voltage input pad 30. Figure 4G shown.

[0107] (8) An eighth conductive layer M8 is formed on the rigid substrate 70. The eighth conductive layer M8 includes the bottom gate 31 of the oxide transistor 3. The material of the eighth conductive layer M8 can be metal such as Mo, Ti or Al. Figure 4H shown.

[0108] (9) forming a second buffer layer 10 on the eighth conductive layer M8, forming an oxide semiconductor layer 20 on the second buffer layer 10, forming a third gate insulating layer GI3 on ​​the oxide semiconductor layer 20, and forming a fifth conductive layer M5 on the third gate insulating layer GI3, wherein the oxide semiconductor layer 20 includes the active portion 32 of the oxide transistor 3, and the fifth conductive layer M5 includes the top gate 33 of the oxide transistor 3, as shown in FIG. Figure 4I shown.

[0109] (10) A second interlayer insulating layer ILD2 is formed on the fifth conductive layer M5, and a seventh conductive layer M7 is formed on the second interlayer insulating layer ILD2. The seventh conductive layer M7 includes the data line 80 and the fifth transfer portion 200. Figure 4J shown.

[0110] (11) Figure 4K As shown, laser technology can be used to Figure 4H The glass substrate 100 is peeled off to obtain Figure 4L The structure shown forms an AM backplane.

[0111] (12) Figure 4J The PM backplane shown is Figure 4L The AM backplane shown is bonded so that the data line 80 is electrically connected to the data voltage pad 40, and the fifth transition portion 200 is electrically connected to the fourth transition portion 90. Figure 3 As shown, the signal input on the PM backplane and the interconnection between the oxide transistor 3 and the temperature structure transistor 2 are realized.

[0112] In some embodiments, as Figure 1 and Figure 3 As shown, the flexible substrate 1 in the embodiment of the present invention can be a polyethylene terephthalate (PET) substrate, a polyethylene naphthalate two formal acid glycol ester (PEN) substrate, or a polyimide (PI) substrate; the rigid substrate 70 can be a glass substrate or a polymethyl methacrylate (PMMA) substrate.

[0113] In some embodiments, the above embodiments of the present invention provide Figure 1 and Figure 3 The display substrate shown includes various types, which can be selected according to actual needs. For example, the display substrate can be a micro light emitting diode (MicroLED) display substrate, an organic light emitting diode (OLED) display substrate, a quantum dot light emitting diode (QLED) display substrate, etc., which is not limited in the embodiment of the present invention.

[0114] In specific implementation, the display substrate provided in the embodiment of the present invention may further include other functional film layers well known to those skilled in the art, which will not be described in detail here.

[0115] Based on the same inventive concept, embodiments of the present invention further provide a display device comprising any of the aforementioned display substrates provided by embodiments of the present invention. The principles of this display device are similar to those of the aforementioned display substrates, and thus the implementation of this display device can refer to the implementation of the aforementioned display substrates, and any repetitions will not be repeated here.

[0116] In specific implementations, the display device provided in the embodiments of the present invention can be any product or component with a display function, such as a full-screen mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigation system. Other essential components of the display device are well understood by those skilled in the art and are not detailed here, nor should they be construed as limitations of the present invention.

[0117] Embodiments of the present invention provide a display substrate and display device that integrates low-temperature polysilicon transistors, oxide transistors, storage capacitors, and first voltage input pads in a pixel drive circuit fabricated using LTPO technology on both sides of a flexible substrate to form a vertically stacked drive backplane structure. This reduces the area occupied by the pixel drive circuit and increases pixel density, thereby achieving a high-resolution LTPO drive backplane structure. Furthermore, because the first plate of the storage capacitor is electrically connected to the first voltage input pad via a first via extending through the flexible substrate, placing the storage capacitor within the first via in the flexible substrate increases the area of ​​the storage capacitor by the depth of the first via in the flexible substrate, forming a vertical capacitor. This increases the area of ​​the storage capacitor within a limited layout space, thereby improving the performance of the LTPO drive backplane.

[0118] Obviously, those skilled in the art may make various changes and modifications to the present invention without departing from the spirit and scope of the present invention. Thus, if such changes and modifications fall within the scope of the claims and their equivalents, the present invention is intended to include such changes and modifications.

Claims

1. A display substrate, characterized in that: The invention comprises a flexible substrate and a pixel driving circuit provided on the flexible substrate, wherein the pixel driving circuit comprises a low-temperature polysilicon transistor, an oxide transistor, a storage capacitor and a first voltage input pad, wherein the low-temperature polysilicon transistor, the oxide transistor and the storage capacitor are provided on a first side of the flexible substrate, and the first voltage input pad is provided on a second side of the flexible substrate, and the first side and the second side are provided opposite to each other; wherein, The first plate of the storage capacitor is electrically connected to the first voltage input pad through a first via hole penetrating the flexible substrate, and the second plate of the storage capacitor is electrically connected to the low-temperature polysilicon transistor.

2. The display substrate according to claim 1, wherein Also includes: A first conductive layer is provided on a first side of the flexible substrate, a barrier layer is provided on a side of the first conductive layer facing away from the flexible substrate, and a second conductive layer is provided on a side of the barrier layer facing away from the flexible substrate; wherein, The first conductive layer includes a first plate of the storage capacitor, and the second conductive layer includes a second plate of the storage capacitor and a bottom gate of the low-temperature polysilicon transistor; The barrier layer has a groove and a first flat portion surrounding the groove at a position corresponding to the first via hole, and the second electrode plate of the storage capacitor covers the bottom and sidewalls of the groove and a portion of the first flat portion.

3. The display substrate according to claim 2, wherein: The present invention also includes a passivation layer arranged between the flexible substrate and the first conductive layer, the passivation layer having a second via hole and a second flat portion surrounding the second via hole at a position corresponding to the first via hole, the orthographic projection of the second via hole on the flexible substrate being located within the orthographic projection range of the first via hole on the flexible substrate, and the first plate of the storage capacitor being electrically connected to the first voltage input pad through a sleeve hole formed by the first via hole and the second via hole.

4. The display substrate according to claim 3, wherein: The first electrode plate of the storage capacitor covers the bottom and sidewalls of the sleeve hole and covers a portion of the second flat portion.

5. The display substrate according to claim 4, wherein: Also includes: a first buffer layer disposed on a side of the second conductive layer facing away from the flexible substrate, a low-temperature polycrystalline silicon semiconductor layer disposed on a side of the first buffer layer facing away from the flexible substrate, a first gate insulating layer disposed on a side of the low-temperature polycrystalline silicon semiconductor layer facing away from the flexible substrate, a third conductive layer disposed on a side of the first gate insulating layer facing away from the flexible substrate, a second gate insulating layer disposed on a side of the third conductive layer facing away from the flexible substrate, a fourth conductive layer disposed on a side of the second gate insulating layer facing away from the flexible substrate, a first interlayer insulating layer disposed on a side of the fourth conductive layer facing away from the flexible substrate, a second buffer layer disposed on a side of the first interlayer insulating layer facing away from the flexible substrate, an oxide semiconductor layer disposed on a side of the second buffer layer facing away from the flexible substrate, a third gate insulating layer disposed on a side of the oxide semiconductor layer facing away from the flexible substrate, a fifth conductive layer disposed on a side of the third gate insulating layer facing away from the flexible substrate, a second interlayer insulating layer disposed on a side of the fifth conductive layer facing away from the flexible substrate, and a sixth conductive layer disposed on a side of the second interlayer insulating layer facing away from the flexible substrate; wherein, The low-temperature polysilicon semiconductor layer includes an active portion of the low-temperature polysilicon transistor, the third conductive layer includes a top gate of the low-temperature polysilicon transistor, the fourth conductive layer includes a bottom gate of the oxide transistor, the oxide semiconductor layer includes an active portion of the oxide transistor, the fifth conductive layer includes a top gate of the oxide transistor, and the sixth conductive layer includes a source and a drain of the low-temperature polysilicon transistor, a source and a drain of the oxide transistor, and a second voltage input pad; A region of the second electrode plate of the storage capacitor covering the first flat portion is electrically connected to a top gate of the low-temperature polysilicon transistor.

6. The display substrate according to claim 5, wherein: The display substrate further includes a data voltage pad provided on the same layer as the first voltage input pad, the first conductive layer further includes a first transfer portion provided corresponding to the data voltage pad, and the third conductive layer further includes a second transfer portion provided corresponding to the first transfer portion; wherein One of the source electrodes of the sixth conductive layer is electrically connected to the second transfer portion through a via hole that sequentially penetrates the second interlayer insulating layer, the third gate insulating layer, the second buffer layer, the first interlayer insulating layer, and the second gate insulating layer; the second transfer portion is electrically connected to the first transfer portion through a via hole that sequentially penetrates the first gate insulating layer, the first buffer layer, and the barrier layer; and the first transfer portion is electrically connected to the data voltage pad through a via hole that sequentially penetrates the passivation layer and the flexible substrate.

7. The display substrate according to claim 6, wherein: Also includes: a rigid substrate disposed on a side of the first voltage input pad facing away from the flexible substrate, and a seventh conductive layer disposed on a side of the rigid substrate facing the first voltage input pad; wherein, The seventh conductive layer includes a data line and a first power line. The data line is electrically connected to the data voltage pad, and the first power line is electrically connected to the first voltage input pad.

8. A display substrate, characterized in that: include: A flexible substrate, a low-temperature polysilicon transistor and a storage capacitor disposed on a first side of the flexible substrate, a rigid substrate disposed on a second side of the flexible substrate, and an oxide transistor disposed on a side of the rigid substrate facing the flexible substrate; wherein the first side and the second side are disposed opposite each other, the oxide transistor and the low-temperature polysilicon transistor are interconnected via vias penetrating the flexible substrate, and the low-temperature polysilicon transistor, the oxide transistor, and the storage capacitor constitute a pixel driving circuit.

9. The display substrate according to claim 8, wherein: Also includes: A first conductive layer is provided on the first side of the flexible substrate, a data voltage pad and at least one fourth transfer portion are provided on the second side of the flexible substrate and in the same layer, and a seventh conductive layer is provided on the side of the oxide transistor facing the flexible substrate; the low-temperature polysilicon transistor is located on the side of the first conductive layer facing away from the flexible substrate; wherein, The seventh conductive layer includes a data line and at least one fifth transfer portion, the data line is electrically connected to the data voltage pad, and the fifth transfer portion is electrically connected to the fourth transfer portion and the oxide transistor respectively; The first conductive layer includes a plurality of sixth transfer portions, wherein a side of the sixth transfer portion facing away from the flexible substrate is electrically connected to the bottom gate of the low-temperature polysilicon transistor, and a side of the sixth transfer portion facing the flexible substrate is electrically connected to the fourth transfer portion through a first via hole penetrating the flexible substrate.

10. The display substrate according to claim 9, wherein The present invention also includes a passivation layer arranged between the flexible substrate and the first conductive layer, the passivation layer having a second via hole at a position corresponding to the first via hole, the orthographic projection of the second via hole on the flexible substrate being located within the orthographic projection range of the first via hole on the flexible substrate, and the sixth adapter being electrically connected to the fourth adapter via a sleeve hole formed by the first via hole and the second via hole.

11. The display substrate according to claim 10, wherein: Also includes: a barrier layer disposed on a side of the first conductive layer facing away from the flexible substrate, a second conductive layer disposed on a side of the barrier layer facing away from the flexible substrate, a first buffer layer disposed on a side of the second conductive layer facing away from the flexible substrate, a low-temperature polycrystalline silicon semiconductor layer disposed on a side of the first buffer layer facing away from the flexible substrate, a first gate insulating layer disposed on a side of the low-temperature polycrystalline silicon semiconductor layer facing away from the flexible substrate, a third conductive layer disposed on a side of the first gate insulating layer facing away from the flexible substrate, a second gate insulating layer disposed on a side of the third conductive layer facing away from the flexible substrate, a fourth conductive layer disposed on a side of the second gate insulating layer facing away from the flexible substrate, a first interlayer insulating layer disposed on a side of the fourth conductive layer facing away from the flexible substrate, and a sixth conductive layer disposed on a side of the first interlayer insulating layer facing away from the flexible substrate; wherein, The second conductive layer includes a bottom gate of the low-temperature polysilicon transistor, the low-temperature polysilicon semiconductor layer includes an active portion of the low-temperature polysilicon transistor, the third conductive layer includes a top gate of the low-temperature polysilicon transistor and a second plate of the storage capacitor, the fourth conductive layer includes a first plate of the storage capacitor, and the sixth conductive layer includes a source and a drain of the low-temperature polysilicon transistor and a first voltage input pad and a second voltage input pad; The first electrode plate of the storage capacitor is electrically connected to the first voltage input pad.

12. The display substrate according to claim 11, wherein The first conductive layer further includes a first transfer portion corresponding to the data voltage pad, the second conductive layer further includes a seventh transfer portion corresponding to the first transfer portion, and the third conductive layer further includes a second transfer portion corresponding to the seventh transfer portion; wherein, One of the source electrodes of the sixth conductive layer is electrically connected to the second transfer portion through a via hole sequentially penetrating the first interlayer insulating layer and the second gate insulating layer, the second transfer portion is electrically connected to the seventh transfer portion through a via hole sequentially penetrating the first gate insulating layer and the first buffer layer, the seventh transfer portion is electrically connected to the first transfer portion through a via hole penetrating the barrier layer, and the first transfer portion is electrically connected to the data voltage pad through a via hole sequentially penetrating the passivation layer and the flexible substrate.

13. The display substrate according to claim 12, wherein: Also includes: an eighth conductive layer provided between the rigid substrate and the seventh conductive layer, a second buffer layer provided between the eighth conductive layer and the seventh conductive layer, an oxide semiconductor layer provided between the second buffer layer and the seventh conductive layer, a third gate insulating layer provided between the oxide semiconductor layer and the seventh conductive layer, a fifth conductive layer provided between the third gate insulating layer and the seventh conductive layer, and a second interlayer insulating layer provided between the fifth conductive layer and the seventh conductive layer; wherein, The eighth conductive layer includes a bottom gate of the oxide transistor, the oxide semiconductor layer includes an active portion of the oxide transistor, and the fifth conductive layer includes a top gate of the oxide transistor; The fifth transfer portion is electrically connected to at least one of a bottom gate, a top gate, and an active portion of the oxide transistor.

14. A display device, characterized in that: The display substrate comprises the display substrate according to any one of claims 1 to 13.

Images