Power cycle test circuit and method of semiconductor device, electronic equipment and medium

Abstract

The embodiment of the invention discloses a power cycle test circuit and method of a semiconductor device, electronic equipment and a medium, the power cycle test circuit comprises a plurality of parallel test branches, and each test branch comprises two tested devices which are reversely connected in series. Each tested device is composed of an insulated gate bipolar transistor with an anti-parallel diode, and the insulated gate bipolar transistor of one tested device and the anti-parallel diode of the other tested device form a current path. And the anti-parallel diode of one tested device and the insulated gate bipolar transistor of the other tested device form another current path. By adopting the embodiment of the invention, the thermal coupling effect of the anti-parallel diode and the IGBT device under the actual condition can be fitted, so that the temperature measurement result of the IGBT device is closer to the actual condition, and the service life evaluation of the power device is more accurate.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor device reliability testing, and in particular to a power cycle testing circuit, method, electronic equipment and medium for a semiconductor device. Background Art

[0002] Power cycling testing simulates device junction temperature fluctuations during operation by heating with load current and switching on and off. This accelerated aging process exposes device package weaknesses in advance and assesses the impact of differences in the thermal expansion coefficient of packaging materials on device life. This is the most important reliability test for assessing power device package reliability and is fundamental for establishing device life models and lifetime assessments. Therefore, accurate junction temperature measurement is crucial in power cycling testing, directly impacting test results and conclusions. Accurate junction temperature measurement enables status detection and overheat protection, thereby improving system reliability.

[0003] In existing power cycling test methods, the diode connected in anti-parallel to the insulated-gate bipolar transistor (IGBT) will generate heat through freewheeling current. This will cause thermal coupling with the IGBT device, causing the measured temperature of the IGBT device to be higher than the actual temperature, resulting in inaccurate life assessment. Summary of the Invention

[0004] The embodiments of the present application provide a power cycle test circuit, method, electronic device and medium for a semiconductor device, which can fit the thermal coupling effect between an anti-parallel diode and an IGBT device under actual conditions, so that the temperature measurement results of the IGBT device are closer to reality, thereby making the power device life assessment more accurate.

[0005] A first aspect of an embodiment of the present application provides a power cycle test circuit for a semiconductor device, the power cycle test circuit comprising a plurality of parallel test branches, each of the test branches comprising two anti-series-connected devices under test, each of the devices under test comprising an insulated gate bipolar transistor having an anti-parallel diode, wherein the insulated gate bipolar transistor of one of the devices under test and the anti-parallel diode of another of the devices under test constitute a current path, and the anti-parallel diode of one of the devices under test and the insulated gate bipolar transistor of another of the devices under test constitute another current path.

[0006] Optionally, the power cycle test circuit also includes an AC power supply, and each test branch is connected to the AC power supply to form a closed loop; when the large current output by the AC power supply is the positive half cycle of the load current, the junction temperature of the insulated gate bipolar transistor of one of the devices under test and the anti-parallel diode of the other device under test increases, and when the large current output by the AC power supply is the negative half cycle of the load current, the junction temperature of the anti-parallel diode of one of the devices under test and the insulated gate bipolar transistor of the other device under test increases.

[0007] Optionally, each of the test branches further includes a controllable switch, wherein the controllable switch enables the large current to flow sequentially through the insulated gate bipolar transistor of one of the devices under test and the anti-parallel diode of another of the devices under test when the current output by the AC power supply is the positive half cycle of the load current; and the controllable switch enables the large current to flow sequentially through the anti-parallel diode of one of the devices under test and the insulated gate bipolar transistor of another of the devices under test when the current output by the AC power supply is the negative half cycle of the load current.

[0008] Optionally, the controllable switch is composed of two insulated gate bipolar transistor switches with anti-parallel diodes connected in anti-series. When the large current output by the AC power supply is the positive half cycle of the load current, one of the insulated gate bipolar transistor switches is closed and the other insulated gate bipolar transistor switch is disconnected; when the large current output by the AC power supply is the negative half cycle of the load current, one of the insulated gate bipolar transistor switches is disconnected and the other insulated gate bipolar transistor switch is closed.

[0009] Optionally, the power cycle test circuit also includes an external switch connected to each of the test branches, and the external switch is used to allow the large current output by the AC power supply to flow through each of the test branches according to a specified turn-on time, so that when one of the test branches performs current testing, the other test branches are cooled down.

[0010] Optionally, the external switch is an insulated gate bipolar transistor switch or a single diode switch with different switching timings, and the switching timings are controlled by a program.

[0011] Optionally, each of the measurement power supplies is connected to two ends of the device under test to measure the voltage of the device under test.

[0012] A second aspect of an embodiment of the present application provides a power cycling test method for a semiconductor device, which is applied to the power cycling test circuit as described in the first aspect. The method includes: Applying a small current to the device under test through the AC power supply at multiple temperature points, and measuring the saturation voltage drops corresponding to the multiple temperature points through the measurement power supply to obtain a corresponding relationship between temperature and saturation voltage drop; Running the power cycle test circuit under normal operating conditions to heat up the device under test, quickly switching the AC power supply to a low current mode, and measuring the saturation voltage drop of the device under test; The junction temperature of the device under test is determined according to the saturation voltage drop of the device under test and the corresponding relationship between the temperature and the saturation voltage drop.

[0013] A third aspect of the present application provides a power cycling test device for a semiconductor device, which is applied to the power cycling test circuit as described in the first aspect. The device includes: a calibration unit, configured to apply a small current to the device under test through the AC power supply at multiple temperature points, and measure the saturation voltage drops corresponding to the multiple temperature points through the measurement power supply to obtain a corresponding relationship between temperature and saturation voltage drop; a detection unit, configured to operate the power cycle test circuit under normal operating conditions to increase the temperature of the device under test, quickly switch the AC power supply to a low current mode, and measure a saturation voltage drop of the device under test; A calculation unit is used to determine the junction temperature of the device under test according to the saturation voltage drop of the device under test and the corresponding relationship between the temperature and the saturation voltage drop.

[0014] A fourth aspect of the embodiments of the present application provides an electronic device, including: a processor and a memory; The processor is connected to the memory, wherein the memory is used to store the computer program, and the processor is used to call the computer program to execute the method in the first aspect of the embodiment of the present application.

[0015] A fifth aspect of an embodiment of the present application provides a computer-readable storage medium, which stores a computer program. The computer program includes program instructions. When the program instructions are executed by a processor, the method in the first aspect of the embodiment of the present application is executed.

[0016] The power cycle test circuit in the present application includes multiple parallel test branches, each of which includes two anti-series DUTs, each of which is composed of an insulated gate bipolar transistor with an anti-parallel diode, wherein the insulated gate bipolar transistor of one of the DUTs and the anti-parallel diode of another DUT form a current path, and the anti-parallel diode of one of the DUTs and the insulated gate bipolar transistor of another DUT form another current path. In this way, when a large current is passed, the current will flow through the insulated gate bipolar transistor of one of the DUTs and the anti-parallel diode of the other DUT, causing the anti-parallel diode of the other DUT to generate heat. The heat generated by the diode can generate a thermal coupling effect with the anti-parallel insulated gate bipolar transistor to simulate the circuit under actual working conditions, so that the measured temperature of the insulated gate bipolar transistor of the other DUT is closer to the actual temperature, thereby making the life assessment of the power device more accurate. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0018] Figure 1 A schematic diagram of a conventional power cycle test circuit provided by an embodiment of the present application is shown; Figure 2 A schematic diagram of a power cycle test circuit for a semiconductor device provided by one embodiment of the present application is shown; Figure 3 shows a specific control timing diagram of each component in the test branch 1 provided by an embodiment of the present application; Figure 4 shows a specific control timing diagram of each component in the test branch 2 provided by an embodiment of the present application; Figure 5 A schematic flow chart of a power cycle testing method for a semiconductor device provided by one embodiment of the present application is shown; Figure 6 A schematic structural diagram of a power cycle testing device for a semiconductor device provided by one embodiment of the present application is shown; Figure 7 A schematic structural diagram of a computer device provided in one embodiment of the present application is shown. DETAILED DESCRIPTION

[0019] The following will be combined with the drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are only part of the embodiments of this application, not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0020] Current research focuses on power cycle circuit topology, broadly categorizing them into DC power cycles, DC power cycles with switching losses, AC power cycles, and PWM power cycles. The DC power cycle is the oldest and simplest circuit, accurately measuring the junction temperature of the device under test. However, it only measures conduction losses, preventing high junction temperature fluctuations for some low-voltage drop devices, which can accelerate aging. The DC power cycle with switching losses was developed to address this issue, combining the advantages of a simple DC power cycle circuit with accurate junction temperature measurement. The DC power cycle test circuit only heats the device through conduction losses generated during current flow. In practical applications, power devices actively switch and experience high voltages during the off-state phase, which cannot be assessed with a DC power cycle. This is why AC or PWM power cycles have emerged. Based on the type of losses and the voltage stress on the device, AC and PWM power cycles can be categorized together. In these cases, devices experience both conduction losses and switching losses during the power cycle. Compared to DC power cycles, AC power cycles operate under the same operating conditions as actual applications. The modules' switching states are controlled by gates, resulting in switching losses during frequent switching and high voltages after shutdown. The aforementioned prior art also suffers from the problem of anti-parallel diodes not heating when no current flows.

[0021] Please refer to Figure 1 , which shows a schematic diagram of a conventional power cycling test circuit provided by an embodiment of the present application. The conventional power cycling test circuit includes multiple parallel test branches and a DC power supply, each test branch being connected to the DC power supply to form a closed loop. Each test branch includes a test switch, two devices under test, and a measurement power supply. The test switch and the two devices under test are connected in series, and the measurement power supply is connected across the two devices under test to measure the voltage of the devices under test. Each device under test is composed of an insulated gate bipolar transistor with an anti-parallel diode.

[0022] For example, Figure 1The figure shows a schematic diagram of two test branches. Test branch 1 includes test switch S1, DUT 1, DUT 2, and measurement power supply 1. Test switch S1, DUT 1, and DUT 2 are connected in series. Measurement power supply 1 is used to measure the voltage of DUT 1 or DUT 2. DUT 1 consists of an insulated gate bipolar transistor Q1 with an antiparallel diode D1. DUT 2 consists of an insulated gate bipolar transistor Q2 with an antiparallel diode D2.

[0023] Similarly, test branch 1 includes a test switch S2, a device under test 3, a device under test 4, and a measurement power supply 2. Test switch S2, device under test 3, and device under test 4 are connected in series. Measurement power supply 2 is used to measure the voltage of device under test 3 or device under test 4. Device under test 3 is composed of an insulated gate bipolar transistor Q3 with an antiparallel diode D3. Device under test 4 is composed of an insulated gate bipolar transistor Q4 with an antiparallel diode D4.

[0024] It can be seen that in a conventional power cycle test circuit, when test switch S1 is closed and test switch S2 is open, the DC power supply applies a large current to test branch 1, causing the device junction temperature to reach the specified junction temperature. Test switch S1 is then disconnected, and test switch S2 is closed to cool test branch 1. That is, test branch 2 uses the cooling time of test branch 1 to heat up, thereby saving aging test time. However, during the period when test switch S1 is disconnected, diode D1, which is anti-parallel to insulated gate bipolar transistor Q1, and diode D2, which is anti-parallel to insulated gate bipolar transistor Q2, do not undergo the freewheeling process seen in an actual inverter circuit and thus do not generate heat. At this time, no thermal coupling occurs with the IGBT device, resulting in the measured temperature of the IGBT being related only to the IGBT itself and inconsistent with the actual circuit operation, leading to inaccurate life assessment.

[0025] In response to the above technical problems, the embodiments of the present application provide a power cycle test circuit, method, electronic device and medium for semiconductor devices, which can fit the thermal coupling effect of the anti-parallel diode and the IGBT device under actual conditions, so that the temperature measurement results of the IGBT device are closer to reality, thereby making the power device life assessment more accurate.

[0026] Please refer to Figure 2 , which shows a schematic diagram of a power cycling test circuit for a semiconductor device provided by one embodiment of the present application. The power cycling test circuit may include multiple parallel test branches, each of which includes two anti-series DUTs, each of which is composed of an insulated gate bipolar transistor with an anti-parallel diode, wherein the insulated gate bipolar transistor of one DUT and the anti-parallel diode of another DUT form a current path, and the anti-parallel diode of one DUT and the insulated gate bipolar transistor of another DUT form another current path.

[0027] For example, Figure 2 A schematic diagram of two test branches is shown in Figure 1. Test branch 1 includes two anti-series connected devices under test (DUTs) 1 and 2. DUT 1 consists of an insulated gate bipolar transistor (IGBT) Q1 with an anti-parallel diode (DUT) D1, and DUT 2 consists of an insulated gate bipolar transistor (IGBT) Q2 with an anti-parallel diode (DUT) D2. IGBT Q1 and anti-parallel diode (DUT) D2 form one current path, while anti-parallel diode (DUT) D1 and IGBT Q2 form another current path.

[0028] Similarly, test branch 2 includes two devices under test 3 and 4 connected in anti-series. Device under test 3 is composed of an insulated gate bipolar transistor Q3 with an anti-parallel diode D3, and device under test 4 is composed of an insulated gate bipolar transistor Q4 with an anti-parallel diode D4. The insulated gate bipolar transistor Q3 and the anti-parallel diode D4 form one current path, and the anti-parallel diode D3 and the insulated gate bipolar transistor Q4 form another current path.

[0029] It can be seen that in the embodiment of the present application, for each test branch, when a large current is passed, the current will flow through the insulated gate bipolar transistor of one of the devices under test and the anti-parallel diode of the other device under test, causing the anti-parallel diode of the other device under test to generate heat. The heat generated by the diode can produce a thermal coupling effect with the anti-parallel insulated gate bipolar transistor to simulate the circuit under actual working conditions, so that the measured temperature of the insulated gate bipolar transistor of the other device under test is closer to the actual temperature, thereby making the life assessment of the power device more accurate.

[0030] For example, when a large current flows through test branch 1, if the current flows through the insulated gate bipolar transistor Q1 and the anti-parallel diode D2, the anti-parallel diode D1 can generate heat. The heat generated by the anti-parallel diode D1 can thermally couple with the insulated gate bipolar transistor Q1, thereby simulating the circuit under actual operating conditions. This makes the measured temperature of the insulated gate bipolar transistor Q2 closer to the actual temperature, thereby making the power device life assessment more accurate. If the current flows through the insulated gate bipolar transistor Q2 and the anti-parallel diode D1, the anti-parallel diode D2 can generate heat. The heat generated by the anti-parallel diode D2 can thermally couple with the insulated gate bipolar transistor Q2, thereby simulating the circuit under actual operating conditions. This makes the measured temperature of the insulated gate bipolar transistor Q2 closer to the actual temperature, thereby making the power device life assessment more accurate.

[0031] For another example, when a large current flows through test branch 2, if the current flows through the insulated gate bipolar transistor Q3 and the anti-parallel diode D4, the anti-parallel diode D3 can generate heat. The heat generated by the anti-parallel diode D3 can thermally couple with the insulated gate bipolar transistor Q3, thereby simulating the circuit under actual operating conditions, making the measured temperature of the insulated gate bipolar transistor Q4 closer to the actual temperature, thereby making the power device life assessment more accurate. If the current flows through the insulated gate bipolar transistor Q4 and the anti-parallel diode D3, the anti-parallel diode D4 can generate heat. The heat generated by the anti-parallel diode D4 can thermally couple with the insulated gate bipolar transistor Q4, thereby simulating the circuit under actual operating conditions, thereby making the measured temperature of the insulated gate bipolar transistor Q4 closer to the actual temperature, thereby making the power device life assessment more accurate.

[0032] Further, see Figure 2 The power cycle test circuit also includes an AC power supply, and each of the test branches is connected to the AC power supply to form a closed loop; when the large current output by the AC power supply is the positive half cycle of the load current, the junction temperature of the insulated gate bipolar transistor of one of the devices under test and the anti-parallel diode of the other device under test increases; when the large current output by the AC power supply is the negative half cycle of the load current, the junction temperature of the anti-parallel diode of one of the devices under test and the insulated gate bipolar transistor of the other device under test increases.

[0033] For example, the AC power supply forms a closed loop with test branch 1 and test branch 2, respectively. In the closed loop formed with test branch 1, when the large current output by the AC power supply is the positive half-cycle of the load current, the junction temperature of the insulated gate bipolar transistor Q1 and the anti-parallel diode D2 increases; when the large current output by the AC power supply is the negative half-cycle of the load current, the junction temperature of the anti-parallel diode D1 and the insulated gate bipolar transistor Q2 increases. In the closed loop formed with test branch 2, when the large current output by the AC power supply is the positive half-cycle of the load current, the junction temperature of the insulated gate bipolar transistor Q3 and the anti-parallel diode D4 increases; when the large current output by the AC power supply is the negative half-cycle of the load current, the junction temperature of the anti-parallel diode D3 and the insulated gate bipolar transistor Q4 increases.

[0034] Furthermore, each of the test branches also includes a controllable switch, which allows the large current to flow sequentially through the insulated gate bipolar transistor of one of the devices under test and the anti-parallel diode of another of the devices under test when the current output by the AC power supply is the positive half cycle of the load current; and the controllable switch allows the large current to flow sequentially through the anti-parallel diode of one of the devices under test and the insulated gate bipolar transistor of another of the devices under test when the current output by the AC power supply is the negative half cycle of the load current.

[0035] For example, see Figure 2 The controllable switch can be composed of two insulated gate bipolar transistor switches with anti-parallel diodes connected in anti-series. When the large current output by the AC power supply is the positive half cycle of the load current, one of the insulated gate bipolar transistor switches is closed and the other is disconnected; when the large current output by the AC power supply is the negative half cycle of the load current, one of the insulated gate bipolar transistor switches is disconnected and the other is closed.

[0036] For example, the controllable switch in test branch 1 is composed of an insulated gate bipolar transistor S1 switch with an anti-parallel diode D5 and an insulated gate bipolar transistor S2 switch with an anti-parallel diode D6 connected in anti-series; the controllable switch in test branch 2 is composed of an insulated gate bipolar transistor S3 switch with an anti-parallel diode D7 and an insulated gate bipolar transistor S4 switch with an anti-parallel diode D8 connected in anti-series.

[0037] In test branch 1, when the large current output by the AC power supply is in the positive half cycle of the load current, the insulated gate bipolar transistor S1 is closed and the insulated gate bipolar transistor S2 is opened, so that the large current flows through the insulated gate bipolar transistor Q1 and the anti-parallel diode D2 in sequence, causing their junction temperature to rise; when the large current output by the AC power supply is in the negative half cycle of the load current, the insulated gate bipolar transistor S1 is opened and the insulated gate bipolar transistor S2 is closed, so that the large current flows through the anti-parallel diode D1 and the insulated gate bipolar transistor Q2 in sequence, causing their junction temperature to rise. The specific control timing of each component in test branch 1 is as follows: Figure 3 shown.

[0038] In test branch 2, when the large current output by the AC power supply is in the positive half cycle of the load current, the insulated gate bipolar transistor S3 is closed and the insulated gate bipolar transistor S4 is opened, so that the large current flows through the insulated gate bipolar transistor Q3 and the anti-parallel diode D4 in sequence, causing their junction temperature to rise; when the large current output by the AC power supply is in the negative half cycle of the load current, the insulated gate bipolar transistor S3 is opened and the insulated gate bipolar transistor S4 is closed, so that the large current flows through the anti-parallel diode D3 and the insulated gate bipolar transistor Q4 in sequence, causing their junction temperature to rise. The specific control timing of each component in test branch 2 is as follows: Figure 4 shown.

[0039] Furthermore, the power cycle test circuit also includes an external switch connected to each of the test branches, and the external switch is used to allow the large current output by the AC power supply to flow through each of the test branches according to the specified opening time, so that when one of the test branches performs current testing, the other test branches are cooled down.

[0040] The external switch can be Figure 2 The controllable switch shown in the figure can also be other types of newly added switches. Figure 2 The controllable switch shown can be an insulated gate bipolar transistor switch or a single diode switch with different switching timings, and the switching timings are controlled by a program.

[0041] As can be seen, by controlling the on / off timing of the external switch so that the high current output by the AC power supply flows through each test branch according to the specified on / off time, while one test branch is performing current testing, the other test branches are cooling down. This embodiment can effectively improve testing efficiency and system heat dissipation efficiency.

[0042] Further, see Figure 2 Each of the measurement power supplies can also be connected to two ends of the device under test to measure the voltage of the device under test.

[0043] Please refer to Figure 5 , which shows a schematic flow chart of a power cycle test method for a semiconductor device provided by an embodiment of the present application. Figure 2 The power cycle test circuit shown, the method includes: Step 501: applying a small current to the device under test through the AC power supply at multiple temperature points, and measuring the saturation voltage drops corresponding to the multiple temperature points through the measurement power supply to obtain a corresponding relationship between temperature and saturation voltage drop.

[0044] For example, a high-precision constant temperature oven or hot plate can be used, with a temperature control accuracy of ≤±1°C (to ensure temperature uniformity). A current source can be used to provide a stable low current (e.g., 1mA to 10mA), with a current fluctuation of ≤±0.1%. The saturation voltage drop corresponding to the multiple temperature points is then measured using a digital multimeter (Keysight 34465A) or a source-meter-meter (SMU). Each temperature point can be measured at least three times, and the average value is taken to eliminate random errors. The voltage drop values ​​corresponding to each temperature point are then organized into a table. The data in the table is fitted using methods such as least squares, polynomials, or exponentials to obtain the corresponding relationship between temperature and saturation voltage drop.

[0045] Step 502: Run the power cycle test circuit under normal working conditions to increase the temperature of the device under test, quickly switch the AC power supply to a low current mode, and measure the saturation voltage drop of the device under test.

[0046] Step 503: Determine the junction temperature of the device under test according to the saturation voltage drop of the device under test and the corresponding relationship between the temperature and the saturation voltage drop.

[0047] For example, the corresponding relationship between temperature and saturation pressure drop is: , in, is the saturation pressure drop, is the reference temperature The conduction voltage drop under is the set temperature point, and k is the temperature coefficient.

[0048] According to the corresponding relationship between temperature and saturation voltage drop, the formula for determining junction temperature can be derived as follows: .

[0049] Therefore, once the saturation voltage drop of the device under test is determined, the junction temperature of the device under test can be determined.

[0050] Figure 6 The schematic diagram of the power cycle test device for semiconductor devices provided by one embodiment of the present application is shown. Figure 2 The power cycle test circuit shown includes: a calibration unit 601 configured to apply a low current to the device under test through the AC power supply at multiple temperature points, and measure the saturation voltage drops corresponding to the multiple temperature points through the measurement power supply to obtain a corresponding relationship between temperature and saturation voltage drop; The detection unit 602 is configured to operate the power cycling test circuit under normal operating conditions to increase the temperature of the device under test, quickly switch the AC power supply to a low current mode, and measure the saturation voltage drop of the device under test; The calculation unit 603 is configured to determine the junction temperature of the device under test according to the saturation voltage drop of the device under test and the corresponding relationship between the temperature and the saturation voltage drop.

[0051] Figure 7 A structural schematic diagram of a computer device provided in one embodiment of the present application is shown, which includes a memory and a processor. The memory stores a computer program, and when the processor executes the computer program, it implements the functions of a computer system of the power cycle testing method for semiconductor devices in any of the above-mentioned embodiments.

[0052] An embodiment of the present application further provides a computer-readable storage medium having a computer program stored thereon. When the computer program is executed by a computer, the computer executes the functions of the computer system of the power cycle testing method for a semiconductor device in any of the above embodiments.

[0053] The embodiments of the present application further provide a computer program product comprising instructions, which, when executed by a computer, enables the computer to perform the functions of the computer system of the power cycle testing method for a semiconductor device in any of the above embodiments.

[0054] It should be understood that the specific examples in this application are only intended to help those skilled in the art better understand the embodiments of this application, rather than to limit the scope of the present invention.

[0055] It can be understood that in the various implementation methods of this application, the size of the serial number of each process does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the implementation method of this application.

[0056] It can be understood that the various embodiments described in this application can be implemented individually or in combination, and the embodiments of this application are not limited to this.

[0057] Unless otherwise indicated, all technical and scientific terms used in the embodiments of the present application have the same meaning as those commonly understood by those skilled in the art in the technical field of the present application. The terms used in this application are only for the purpose of describing specific embodiments and are not intended to limit the scope of this application. The term "and / or" used in this application includes any and all combinations of one or more related listed items. The singular forms "a", "above", and "the" used in the embodiments of the present application and the appended claims are also intended to include plural forms, unless the context clearly indicates otherwise.

[0058] It is understood that the processor in the embodiments of the present application can be an integrated circuit chip with signal processing capabilities. During implementation, each step of the above-mentioned method embodiment can be completed by hardware integrated logic circuits in the processor or software instructions. The above-mentioned processor can be a general-purpose processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field programmable gate array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components. The various methods, steps, and logic block diagrams disclosed in the embodiments of the present application can be implemented or executed. The general-purpose processor can be a microprocessor or any conventional processor. The steps of the method disclosed in the embodiments of the present application can be directly implemented and executed by a hardware decoding processor, or by a combination of hardware and software modules in the decoding processor. The software module can be located in a storage medium mature in the art, such as random access memory, flash memory, read-only memory, programmable read-only memory, electrically erasable programmable memory, registers, etc. The storage medium is located in the memory, and the processor reads the information in the memory and, in conjunction with its hardware, completes the steps of the above-mentioned method.

[0059] It will be understood that the memory in the embodiments of the present application may be a volatile memory or a non-volatile memory, or may include both volatile and non-volatile memories. Among them, the non-volatile memory may be a read-only memory (ROM), a programmable read-only memory (programmable ROM, PROM), an erasable programmable read-only memory (erasable PROM, EPROM), an electrically erasable programmable read-only memory (EEPROM) or flash memory. The volatile memory may be a random access memory (RAM). It should be noted that the memory of the systems and methods described herein is intended to include, but is not limited to, these and any other suitable types of memory.

[0060] Those skilled in the art will appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0061] Those skilled in the art will clearly understand that, for the convenience and brevity of description, the specific working processes of the above-described systems, devices and units can refer to the corresponding processes in the aforementioned method implementation methods and will not be repeated here.

[0062] In the several embodiments provided in this application, it should be understood that the disclosed systems, devices, and methods can be implemented in other ways. For example, the device embodiments described above are merely illustrative. For example, the division of units is merely a logical function division. In actual implementation, there may be other division methods, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.

[0063] Units described as separate components may or may not be physically separate, and components shown as units may or may not be physical units, that is, they may be located in one place or distributed across multiple network units. Some or all of these units may be selected to achieve the purpose of this embodiment according to actual needs.

[0064] In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.

[0065] If the function is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application, or the part that contributes to the prior art, or the part of the technical solution, can be embodied in the form of a software product. The computer software product is stored in a storage medium and includes several instructions for enabling a computer device (which can be a personal computer, server, or network device, etc.) to execute all or part of the steps of the various implementation methods of the present application. The aforementioned storage medium includes: various media that can store program codes, such as a USB flash drive, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk, or an optical disk.

[0066] The above are only specific embodiments of the present application, but the scope of protection of the present invention is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this application should be included in the scope of protection of this application. Therefore, the scope of protection of the present invention should be based on the scope of protection of the claims.

Claims

1. A power cycle test circuit for a semiconductor device, characterized in that: The power cycling test circuit includes multiple parallel test branches, each of which includes two anti-series DUTs, each of which is composed of an insulated gate bipolar transistor with an anti-parallel diode, wherein the insulated gate bipolar transistor of one DUT and the anti-parallel diode of another DUT form a current path, and the anti-parallel diode of one DUT and the insulated gate bipolar transistor of another DUT form another current path.

2. The power cycle test circuit according to claim 1, characterized in that: The power cycle test circuit also includes an AC power supply, and each test branch is connected to the AC power supply to form a closed loop; when the large current output by the AC power supply is the positive half cycle of the load current, the junction temperature of the insulated gate bipolar transistor of one of the devices under test and the anti-parallel diode of the other device under test increases; when the large current output by the AC power supply is the negative half cycle of the load current, the junction temperature of the anti-parallel diode of one of the devices under test and the insulated gate bipolar transistor of the other device under test increases.

3. The power cycle test circuit according to claim 2, characterized in that: Each of the test branches also includes a controllable switch, which allows the large current to flow sequentially through the insulated gate bipolar transistor of one of the devices under test and the anti-parallel diode of another of the devices under test when the current output by the AC power supply is the positive half cycle of the load current; and the controllable switch allows the large current to flow sequentially through the anti-parallel diode of one of the devices under test and the insulated gate bipolar transistor of another of the devices under test when the current output by the AC power supply is the negative half cycle of the load current.

4. The power cycle test circuit according to claim 3, characterized in that: The controllable switch is composed of two insulated gate bipolar transistor switches with anti-parallel diodes connected in anti-series. When the large current output by the AC power supply is in the positive half cycle of the load current, one of the insulated gate bipolar transistor switches is closed and the other is opened; when the large current output by the AC power supply is in the negative half cycle of the load current, one of the insulated gate bipolar transistor switches is opened and the other is closed.

5. The power cycle test circuit according to claim 2, wherein: The power cycle test circuit also includes an external switch connected to each of the test branches, and the external switch is used to allow the large current output by the AC power supply to flow through each of the test branches according to a specified turn-on time, so that when one of the test branches is undergoing current testing, the other test branches are cooled.

6. The power cycle test circuit according to claim 4, characterized in that: The external switch is an insulated gate bipolar transistor switch or a single diode switch with different switching timings, and the switching timings are controlled by a program.

7. The power cycle test circuit according to claim 4, characterized in that: Each of the measurement power supplies is connected to two ends of the device under test to measure the voltage of the device under test.

8. A power cycle test method for a semiconductor device, characterized in that: Applied to the power cycling test circuit according to claim 7, the method comprises: Applying a small current to the device under test through the AC power supply at multiple temperature points, and measuring the saturation voltage drops corresponding to the multiple temperature points through the measurement power supply to obtain a corresponding relationship between temperature and saturation voltage drop; Running the power cycle test circuit under normal operating conditions to increase the temperature of the device under test, quickly switching the AC power supply to a low current mode, and measuring the saturation voltage drop of the device under test; The junction temperature of the device under test is determined according to the saturation voltage drop of the device under test and the corresponding relationship between the temperature and the saturation voltage drop.

9. An electronic device, characterized in that: include: processor and memory; The processor is connected to a memory, wherein the memory is used to store a computer program, and the processor is used to call the computer program to execute the method according to claim 8.

10. A computer-readable storage medium, characterized in that The computer-readable storage medium stores a computer program, wherein the computer program includes program instructions, and when the program instructions are executed by a processor, the method according to claim 8 is performed.

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