GNSS anti-interference receiver system based on radio frequency front end-INS combined assistance

Abstract

The invention provides a GNSS (Global Navigation Satellite System) anti-interference receiver system based on radio frequency front end-INS (Inertial Navigation System) combined assistance, which adopts a dual-core ARM Cortex-A9 and a programmable logic unit for layered decoupling, and realizes real-time receiving and processing of a high-bandwidth data stream, closed-loop control of an interference suppression link and quick response of a navigation path and a strategy decision. All the modules efficiently cooperate through AXI-Lite register mapping, interrupt signals, a shared state buffer area and a timer synchronization mechanism. By controlling bus and state buffer mapping to keep consistency and supporting a module-level independent debugging and system-level soft reset mechanism under hot start, the expandability of subsystem cascade debugging, fault module positioning and online updating is realized. In the aspects of module architecture, data channels and cooperation mechanisms, the structure order, efficient communication and control closed loop are realized, and an embedded multi-module cooperation anti-interference platform which is suitable for a high-interference environment, multi-channel fusion processing and navigation task real-time response is constructed.

Description

Technical Field

[0001] The present invention relates to the technical field of global satellite navigation systems, and in particular to a GNSS anti-interference receiver system based on radio frequency front-end-INS joint assistance. Background Art

[0002] As the core of modern navigation and positioning, the Global Navigation Satellite System (GNSS) has been widely used in numerous key areas, including aerospace, maritime transportation, geographic surveying and mapping, power communications, traffic management, and military defense. Thanks to the continued development of high-precision atomic clocks, miniature inertial sensors, and wireless communication technologies, the positioning accuracy and breadth of GNSS applications continue to improve. However, due to the long propagation paths of GNSS signals in space and their low initial transmission power, the signals are extremely weak when they finally reach the ground, making them susceptible to severe interference from the natural environment and man-made signal sources. These interference signals, including high-power suppressive interference and deceptive interference from structural camouflage, can prevent receivers from properly calculating valid position information, thereby affecting the overall availability and reliability of the system and potentially causing serious safety incidents.

[0003] To address GNSS's susceptibility to interference, existing technologies have proposed various anti-interference strategies across multiple links in the receiver chain. Antenna-side anti-interference strategies typically utilize array structures to suppress interference sources through spatial directional filtering. However, these approaches require significant modifications to the receiver antenna system, resulting in complex hardware, high costs, and high power consumption, making them difficult to implement in traditional devices with limited space or enclosed structures. Baseband anti-interference strategies, such as detecting changes in correlator outputs and capturing drops in channel signal-to-noise ratio, also require significant modifications to the receiver's internal architecture. These strategies rely on mid- and back-end processes where the signal has already been demodulated, resulting in limited timeliness in interference response and difficulty implementing fast, proactive anti-interference control. In contrast, RF front-end anti-interference technology, which identifies and pre-suppresses signals before they enter the receiver's core processing unit, offers advantages such as simple structure, rapid response, manageable costs, and ease of modular deployment, making it more suitable as a front-end "line of defense" for traditional receivers. However, no single anti-interference approach can fully cover all types of interference scenarios. The RF front end can effectively suppress narrowband interference in the form of continuous waves, but its ability to identify deceptive interference is limited; and although the INS auxiliary mechanism can identify abnormal changes in positioning results at the back end, if the interference causes complete signal loss at the front end, the inertial system will gradually drift and lose its compensation effect. Summary of the Invention

[0004] In response to the shortcomings of the existing technology, the purpose of the present invention is to provide a GNSS anti-interference receiver system based on RF front-end-INS joint assistance to solve the problems raised in the above background technology. Through modular access and multi-level interference processing mechanism, the present invention effectively solves the core problems of the current system such as difficult identification, delayed suppression, and weak anti-interference when facing suppression interference, deceptive interference, and multi-source complex interference. Without reconstructing the original structure, the anti-interference capability is substantially enhanced.

[0005] In order to achieve the above-mentioned purpose, the present invention is implemented through the following technical solutions: a GNSS anti-interference receiver system based on RF front-end-INS joint assistance, the hardware architecture of the system includes a signal down-conversion board and a signal processing board, the signal down-conversion board is used to down-convert the multi-frequency RF signals received by the GNSS antenna, and output two pairs of analog IQ intermediate frequency signals to provide original input for the subsequent anti-interference processing; the signal processing board integrates a ZYNQ programmable SoC chip, an analog-to-digital / digital-to-analog converter, an inertial navigation module communication interface and a signal output unit to complete intermediate frequency signal sampling, anti-interference digital processing, navigation fusion solution and path management functions. The system uses an external GNSS measurement antenna to receive navigation satellite signals from multiple frequency bands. The signal first passes through a front-end low-noise amplifier and a T-type attenuator to complete gain control and power conditioning. The conditioned RF signal is divided into four channels by a four-power splitter and enters the RF anti-interference path of the corresponding frequency point respectively; the software architecture of the system is built on ZYNQ XC7Z020 On the SoC platform, a software-hardware collaborative processing mechanism is adopted to effectively decouple the high-parallel anti-interference processing of GNSS signals and navigation fusion reasoning, which are completed by the programmable logic unit and the embedded processing system unit respectively.

[0006] Furthermore, the baseband signal after interference suppression processing is resynthesized into an intermediate frequency signal through digital up-conversion and sent to the DAC from the PL end through the LVCMOS interface to complete the digital-to-analog conversion. The signal is then up-converted through the local oscillator-mixer structure to restore it to the original frequency band, and finally output to the GNSS receiver signal input port through the power amplifier, completing the closed-loop transmission of RF-level anti-interference processing.

[0007] Furthermore, it also includes an inertial navigation module, which communicates with the ZYNQ PS end through the TTL serial port to provide three-axis angular velocity and acceleration information; the GNSS receiver module is connected to the ZYNQ PS end through the TTL serial port to output RTCM3 format data. The ZYNQ PS end runs the GNSS / INS tightly integrated navigation filter, extracts the filter innovation residual based on the IMU data and pseudorange solution results, identifies pseudorange drift anomalies and assists in judging potential deceptive interference.

[0008] Furthermore, it also includes the PL-side processing flow, in which the programmable logic unit is responsible for the sampling, processing and interference suppression tasks of the GNSS signal at the physical layer, and constructs an adaptive notch filter processing path driven by spectrum analysis. The processing flow is composed of several functional modules in sequence, and the signal data is transmitted between the modules through the on-chip interconnection bus, forming a highly parallel and pipelined anti-interference signal processing chain. The functional modules include an analog-to-digital conversion input module, a digital down-conversion module, a time-frequency analysis and interference detection module, an adaptive notch filter module, and a signal synthesis and loopback link module.

[0009] Furthermore, the analog-to-digital conversion input module is the starting module of the system's PL-side signal processing link, deployed in the programmable logic unit of the ZYNQ SoC platform, and is used to receive external analog signal sampling results and complete initial digital format processing. The system supports receiving GNSS intermediate frequency signals of four frequency channels: B1, L1, G1, and B3. The front-end RF link uses a superheterodyne architecture to perform IQ demodulation and frequency conversion on each frequency signal, and outputs an I / Q dual-channel analog signal with a center frequency of 4.096 MHz. A total of 8 analog intermediate frequency signals are used as input sources. Each channel signal is connected to 4 dual-channel analog-to-digital converters, with a sampling rate of 65 MHz per channel, a quantization accuracy of 14 bits, and an output interface in the LVCMOS standard parallel digital format. During module operation, a complete input anomaly detection mechanism is included, and all abnormal states are mapped to the AXI-Lite address space through the status register group for real-time access and monitoring by the PS side.

[0010] The digital down-conversion module is deployed in the programmable logic unit of the ZYNQ SoC platform, located after the analog-to-digital conversion input module. It is used to perform digital frequency shifting and bandwidth compression on the four complex IQ intermediate frequency signals output by the module, and output standardized complex baseband signals for use by the subsequent interference detection and suppression module. The input signal is complex intermediate frequency data with a sampling rate of 65 MSPS and 14-bit accuracy, and the center frequency is 4.096 MHz. The module output signal is a complex baseband IQ data stream with a sampling rate of 4.0625 MSPS and 16-bit accuracy. The bandwidth is controlled within 4 MHz to meet the spectrum fidelity and dynamic range requirements of GNSS baseband signal processing; the module is equipped with frequency lock status detection logic to monitor the operating stability of the NCO local oscillator frequency. The lock status is determined by the phase observer and written into the status register for use by the PS end scheduling or fault identification.

[0011] Furthermore, the time-frequency analysis and interference detection module is deployed in the programmable logic unit of the ZYNQ SoC platform, located after the digital down-conversion module. It is mainly used for interference detection and parameter extraction based on power spectrum perturbations, and provides dynamic control information for the subsequent adaptive notch filtering module. The module's input signal is four complex baseband IQ data streams from the digital down-conversion module, with a sampling rate of 4.0625 MSPS and a data format of 16-bit fixed-point complex numbers. The system configures an independent spectrum analysis path for each channel and builds a four-channel parallel processing structure to support multi-frequency signal input. The module uses a 256-point fast Fourier transform to implement sliding window spectrum analysis with a window step of 128 points, forming a 50% overlapping sliding window structure to improve the time resolution of spectral perturbations. The input data is uniformly multiplied by a Hamming window function for shaping before being sent to the FFT. The window function coefficients are loaded by ROM during system initialization.

[0012] The adaptive notch filter module is deployed in the programmable logic unit of the ZYNQ SoC platform, located between the time-frequency analysis module and the system signal loopback link. It is mainly used to construct a notch filter based on dynamic interference parameters to achieve real-time suppression of strong interference at the target frequency point. The module receives the interference parameters output by the analysis module, including the center frequency index, bandwidth control word, and intensity factor information, filters the original baseband IQ signal by reconstructing the notch filter coefficients, and outputs the suppressed complex signal for use in the subsequent loopback link. The module supports independent operation of four channels: B1, L1, G1, and B3. The input of each channel is a complex IQ data stream with a sampling rate of 4.0625 MSPS and a data format of 16-bit fixed-point complex numbers. Each channel is internally configured with two sets of series-connected reconfigurable notch filter paths to support parallel suppression of multiple clusters of interference. Each set of notches adopts a second-order IIR structure and has the ability to construct frequency domain notches, which is suitable for suppressive interference suppression scenarios.

[0013] The center frequency of the notch filter is converted by the frequency index in the interference parameter to calculate the normalized frequency ω. The formula is:

[0014]

[0015] The normalized frequency is used to calculate the cos(ω) term in the notch filter transfer function. The system obtains the required value through a lookup table and linear interpolation mechanism. The LUT uses the Q1.15 fixed-point format with a resolution of 1 / 1024, which can achieve an interpolation error better than ±0.001, ensuring that the notch frequency control accuracy is higher than 1 / 512 of the sampling frequency. The transfer function of each notch filter group is as follows:

[0016] H(z)=

[0017] Where r is the pole radius, which is used to control the bandwidth and depth of the filter. The system converts its value based on the bandwidth control word. The bandwidth calculation formula is:

[0018] -

[0019] Where EBW is the estimated bandwidth, Fs is the sampling rate, and r typically ranges from 0.95 to 0.99. The filter coefficients are quantized using the Q2.14 format and mapped to the DSP48E1 arithmetic unit inside the PL through a pipeline structure.

[0020] Furthermore, the signal synthesis and loopback link module is deployed in the programmable logic unit of the ZYNQ SoC platform, located after the adaptive notch filter module. It is mainly used to complete frequency up-conversion, weighted synthesis and digital-to-analog conversion operations on the complex baseband signal after four-channel interference suppression, and output a standardized analog intermediate frequency signal, which is sent back to the system RF front end to build a closed-loop output path for the anti-interference processing link; the module input is the four-way complex IQ data stream output by the previous notch filter module, which corresponds to the four frequency points B1, L1, G1, and B3 of the GNSS signal respectively. The system configures an independent digital up-conversion path for each channel, including a digitally controlled oscillator, a complex rotation unit and a modulator, which is used to up-convert the baseband signal to a preset intermediate frequency point.

[0021] Furthermore, it also includes a processing system in the ZYNQ SoC platform, which is used to manage the register read and write of each module of the programmable logic unit, the fusion processing of inertial and GNSS observation data, the execution of deception interference identification logic, and the unified scheduling and output control of the system status. In order to improve the parallelism and modular management efficiency of system operation, the PS side is constructed with a dual-core heterogeneous structure, with two ARM Cortex-A9 cores independently undertaking different functional tasks. The processing system in the ZYNQ SoC platform includes a variety of PS-side functional modules, including PL register configuration and task scheduling module, GNSS / IMU data acquisition and observation preprocessing module, combined navigation filtering module, interference detection and navigation status management module, system status output and remote interface module.

[0022] Furthermore, the PL register configuration and task scheduling module is deployed on the ARM Cortex-A9 core CPU0 of the Zynq SoC platform. As the main scheduling unit for system operation control, it is fully responsible for register configuration writing, operation status polling, interrupt event response, and sharing and output of system status information for each functional module of the programmable logic unit (PL), realizing unified control and stable scheduling of the anti-interference functional link;

[0023] The GNSS / IMU data acquisition and observation preprocessing module is deployed on the ARM Cortex-A9 core CPU1 of the Zynq SoC platform. As the data input front end of the integrated navigation system, it is responsible for receiving, formatting, timing synchronization, reconstructing cache and sharing updates of observation data provided by external GNSS receivers and inertial measurement units, providing the navigation filter with high-efficiency observation information with a unified structure.

[0024] The integrated navigation filtering module is deployed on the ARM Cortex-A9 core CPU1 of the ZYNQ SoC platform. As the core functional unit of the integrated navigation solution, it adopts the extended Kalman filter algorithm structure to achieve the fusion and state estimation of multi-source navigation information, continuously output high-precision position, velocity and attitude information, and provide new information judgment basis and state residual support for the subsequent interference identification and path control modules.

[0025] The interference detection and navigation status management module is deployed on the ARM Cortex-A9 core CPU1 of the ZYNQ SoC platform. As the upper-level control logic unit of the integrated navigation system, it is responsible for comprehensively analyzing interference information and navigation status quality indicators, completing pseudo-range channel shielding, path mode switching, navigation credibility output and system status management functions. The module operates in coordination with the navigation filter module, maintaining a 10Hz update cycle, and realizing the system's anti-interference intelligent scheduling and path steady-state switching capabilities.

[0026] The system status output and remote interface module is deployed on the ARM Cortex-A9 core CPU0 of the ZYNQ SoC platform. It serves as the output channel for external delivery of system operation results and synchronization of remote information. It is responsible for uniformly encapsulating the system's current navigation status, interference detection results, path control flags and key operation information of credibility assessment, and sending them to the external platform through the serial port or Ethernet interface, supporting remote logging, link access control or system operation loopback verification.

[0027] Furthermore, each processing module on the PL side adopts a strict signal flow design. Starting from the analog-to-digital acquisition and reception module in module 1, it completes digital down-conversion, interference detection, adaptive notch filtering, digital up-conversion, and channel synthesis in sequence. Each module achieves cascade communication through structured complex signal channels and synchronous control signals. Key signal nodes are equipped with control registers and status feedback interfaces. The interference detection module and the notch filter configuration module interact through an internal parameter bus to achieve automatic filter parameter updates. All key PL registers are mapped to the AXI-Lite bus and integrated into the PS address space. They are configured and accessed in real time by CPU0.

[0028] The PS adopts a dual-core architecture. ARM CPU0 is responsible for system control and management tasks, including PL register access, shared memory construction, interference flag forwarding, status encapsulation output, and remote communication control. ARM CPU1 is dedicated to high-frequency integrated navigation filtering tasks and innovation residual calculation and judgment logic, ensuring navigation accuracy and minimizing path control response latency.

[0029] The system interrupt mechanism is uniformly triggered by the PL-side event-driven module, including sampling interrupts, data anomalies, and interference event key states. The interrupt signal is sent to CPU0 through the GIC controller. The interrupt service routine quickly identifies the register status bit and executes the corresponding processing logic, and updates the shared memory structure. The synchronization mechanism uses a two-level timer management. The main timer drives the GNSS / IMU data update rhythm, and the sub-timer is responsible for PL status polling and output scheduling.

[0030] Beneficial effects of the present invention:

[0031] This GNSS anti-interference receiver system, based on a combined RF front-end and INS assistance system, features a modular, enhanced design based on the Zynq SoC platform. This system leverages programmable logic and embedded processing to create a front-end and back-end separated, collaborative anti-interference architecture. By mapping the multi-channel RF processing chain and INS-assisted navigation module to the PL and PS sides, respectively, this system integrates multiple functions, including signal enhancement, interference identification, information fusion, and positioning fault tolerance, without changing the original receiver architecture. This ensures stable operation of the original system logic while improving its overall anti-interference performance.

[0032] This GNSS anti-interference receiver system, based on a combined RF front-end and INS assistance, features a multi-frequency parallel anti-interference architecture. The RF front-end divides the incoming GNSS signal into multiple frequency channels, where multi-stage bandpass filtering and downconversion are performed, effectively isolating interference components from different frequency bands. Each downconverted analog IF signal is synchronously acquired by the ZYNQ SoC's PL side via a multi-channel ADC and fed into the digital processing chain, where it undergoes anti-interference processing, including digital downconversion, joint time-frequency analysis, and adaptive interference identification. The processed clean IF signal is then upconverted back to the original GNSS receiver signal channel via a high-speed DAC driven by the PL side, forming a complete closed-loop path of "multi-frequency parallel processing - interference suppression - signal recovery - system feedback." This architecture simultaneously establishes clean channels across multiple frequencies, addressing the inability of traditional single-frequency anti-interference systems to ensure stable multi-constellation reception. It is particularly suitable for engineering scenarios targeting multi-frequency converged navigation systems such as B1 and L1.

[0033] 3. This GNSS anti-interference receiver system, based on RF front-end-INS joint assistance, introduces an adaptive notch filter algorithm based on spectrum estimation. Combined with the results of joint time-frequency analysis, it adjusts the filter center frequency, bandwidth, and order in real time to adapt to the spectral variation characteristics of suppression interference. This mechanism supports accurate filtering of typical signals such as dynamic narrowband interference, swept frequency interference, single-tone interference, and pulse-modulated interference. The filter algorithm is implemented with parallel logic on the PL side of ZYNQ, featuring channel independence, fast response, and flexible adjustment. The notch filter parameters can be independently configured according to the characteristics of the received signals in different channels, ensuring that the system still has high suppression rate and low signal distortion rate in complex interference environments, thereby improving the continuous operation capability of the GNSS system under complex suppression interference.

[0034] 4. The present invention introduces a new information discrimination mechanism based on combined navigation filtering on the PS side. Under normal conditions, the new information sequence should show zero mean, Gaussian distribution characteristics, and stable variance; when the GNSS signal is interfered by pseudorange manipulation or position guidance deception, the deviation between the predicted value and the measured value will continue to accumulate, and the new information sequence will show a sudden change in statistical characteristics, such as mean drift, increased fluctuation or frequent extreme anomalies. This system combines the inertial navigation unit to build a GNSS / INS tight combination structure, and performs dynamic statistical analysis on the new information sequence through a multi-epoch sliding window. It monitors the trend of the new information mean and variance in real time, and assists in identifying hidden pseudorange offsets or trajectory drift anomalies in GNSS observation data. On this basis, the system further jointly analyzes the dynamic characteristics of the new information obtained on the PS side with the front-end spectrum detection and interference parameter estimation results on the PL side to build a cross-level judgment mechanism. This mechanism can identify deceptive interference signals with "legitimate signal structures but abnormal information", thereby circumventing the limitations of traditional GNSS receivers that rely solely on signal quality indicators and cannot identify deception. It significantly improves the system's detection capability and response time to slowly changing, non-destructive deceptive interference.

[0035] 5. This invention establishes a dynamic adjustment mechanism driven by interference perception. At the front end, it continuously senses the interference situation through spectrum monitoring, energy determination, and channel quality estimation. At the back end, it combines filter state feedback with navigation residual information to determine system stability in real time. The system automatically adjusts filter paths, signal weights, and control parameters based on interference intensity, deception characteristics, and solution confidence, achieving a closed-loop response of "front-end active suppression—back-end fault-tolerant solution—and real-time state switching," effectively improving the system's adaptability and robustness in non-static interference environments.

[0036] 6. This system utilizes the ZYNQ-7Z020 SoC platform to create a decoupled hardware and software computing architecture. RF signal processing tasks (such as joint time-frequency analysis, notch filtering, and digital frequency conversion) are performed in the logic resources on the PL side, while the integrated navigation algorithm and interference discrimination mechanism are implemented on the PS side. This platform integrates multi-level collaboration, parallel computing, and low-latency processing, ensuring high-performance anti-interference processing while significantly reducing system size and power consumption. It is suitable for deployment in scenarios where both anti-interference performance and resource efficiency are critical. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] Figure 1 This is a front view of the signal down-conversion board in the hardware architecture of the system of the present invention;

[0038] Figure 2 This is a back view of the signal down-conversion board in the hardware architecture of the system of the present invention;

[0039] Figure 3 This is a front view of the signal processing board in the hardware architecture of the system of the present invention;

[0040] Figure 4 This is a back view of the signal processing board in the hardware architecture of the system of the present invention;

[0041] Figure 5 This is a block diagram of the hierarchical structure of the system software of the present invention;

[0042] Figure 6 This is the spectrum comparison before and after interference injection in the embodiment;

[0043] Figure 7 Spectrum comparison before and after notch filtering in an embodiment of the present invention;

[0044] Figure 8 The positioning error varies with the interference intensity in the embodiment of the present invention;

[0045] Figure 9 This is a flowchart of navigation path switching under interference suppression in an embodiment of the present invention;

[0046] Figure 10 This is a graph showing the trend of innovation residuals of the integrated navigation system according to an embodiment of the present invention;

[0047] Figure 11 This is a comparison diagram of positioning trajectory deviation in an embodiment of the present invention;

[0048] Figure 12 This is a timing diagram of navigation path switching under deception interference in an embodiment of the present invention;

[0049] Figure 13 This is the energy change trend diagram of the BeiDou B1 channel power spectrum;

[0050] Figure 14 Output statement format for the system;

[0051] Figure 15 Spectrum comparison diagram before and after L1 frequency point interference suppression in an embodiment of the present invention;

[0052] Figure 16 This is a flow chart of key time points in interference response processing under composite interference in an embodiment of the present invention. DETAILED DESCRIPTION

[0053] In order to make the technical means, creative features, objectives and effects achieved by the present invention easier to understand, the present invention is further described below in conjunction with specific implementation methods.

[0054] Example 1

[0055] See also Figures 1 to 16 The present invention provides the following technical solutions: a GNSS anti-interference receiver system based on RF front-end-INS joint assistance, the hardware architecture of the system is as follows Figure 1 , 2, 3, 4 shown, Figure 1 and Figure 2 The front and back views of the signal downconversion board designed in this invention are schematic diagrams, respectively. This board is primarily used to downconvert the multi-frequency RF signals received by the GNSS antenna, outputting two pairs (four channels) of analog IQ intermediate frequency (IF) signals, which provide the raw input for subsequent anti-interference processing. The diagram shows the component layout and wiring structure of the input SMA connector, mixer, local oscillator module, and filtering and power conditioning circuits. Figure 3 and Figure 4 The front and back views of the signal processing board of the present invention are schematic diagrams, respectively. This board integrates a ZYNQ programmable SoC chip, analog-to-digital / digital-to-analog converters, an inertial navigation module communication interface, and a signal output unit. It performs intermediate frequency signal sampling, anti-interference digital processing, navigation fusion solution, and path management, serving as the core processing platform of the system. The board layout illustrates the layout of various peripheral connection units, including SMA input and output interfaces, an ADC / DAC chip array, power conditioning circuitry, and Ethernet / serial ports. Together, they form a closed-loop GNSS anti-interference system for suppressing and deceiving jammers.

[0056] The system uses an external GNSS measurement antenna to receive navigation satellite signals from multiple frequency bands (B1, L1, G1, and B3). The signals first pass through a front-end low-noise amplifier (SGL0622Z) and a T-type attenuator (HMC652LP2E) for gain control and power conditioning. The conditioned RF signal is then divided into four channels by a quad-power splitter (HT-SC4PS-33+), each of which enters the RF anti-interference path at the corresponding frequency.

[0057] Each channel utilizes a superheterodyne downconversion solution with the same architecture, including two-stage amplification (SGL0622Z) and multi-stage bandpass filtering (KH-SAWF158A) for frequency band isolation. A mixer (AD8347ARU) and a configurable local oscillator (ADF4360-4) then perform I / Q downconversion, outputting analog IF (I / Q) signals centered at 4.096 MHz. The ZYNQXC7Z020 SoC's power supply (PS) uses an SPI interface to configure the four local oscillator frequencies, enabling channel selection and control at different frequencies.

[0058] The resulting downconversion generates eight analog IF signals (4 frequency points x 2 IQ channels), which are sampled in parallel by four dual-channel ADCs (AD9248) at a sampling rate of 65 MHz. The data is then transmitted to the ZYNQ chip's PL side via an LVCMOS interface. The PL side first performs digital downconversion (DDC) on each signal, converting the IF signal to baseband. The signals are then fed into the joint time-frequency analysis module and the adaptive notch filter module for interference feature extraction and suppression filtering. For typical suppression interference such as dynamic narrowband interference, single-tone interference, and pulse modulation, the system generates multiple sets of notch filters in real time for multi-channel, frequency-independent adaptive filtering.

[0059] After interference suppression, the baseband signal is resynthesized into an IF signal through a digital upconversion (DUC) and fed from the PL side via an LVCMOS interface to a DAC (AD9767) for digital-to-analog conversion. The signal is then upconverted back to its original frequency band using the same local oscillator-mixer structure as the front-end. Finally, it is output to the GNSS receiver's signal input port via a power amplifier (AD8057), completing the closed-loop transmission of RF-level interference mitigation.

[0060] The system's inertial navigation module is a domestically produced high-update MEMS IMU (data output rate 2000Hz), which communicates with the ZYNQ PS via a TTL serial port, providing triaxial angular velocity and acceleration information. The domestically produced GNSS receiver module, with a 10 Hz update rate, connects to the ZYNQ PS via a TTL serial port and outputs data in RTCM3 format. The ZYNQ PS runs a tightly integrated GNSS / INS navigation filter, extracting filter innovation residuals from IMU data and pseudorange solution results, identifying pseudorange drift anomalies and assisting in the identification of potential deceptive interference. The system supports dynamic GNSS weight adjustment, path reconstruction, and navigation status output.

[0061] The PL and PS exchange status information via the AXI bus and DMA channels. The PL is responsible for performing joint time-frequency analysis and interference detection, uploading processed results such as interference strength and spectrum distribution to the PS. Based on GNSS measurements and INS inertial navigation information, the PS runs a combined navigation filter to calculate innovations and identify spoofing interference. It can also adjust GNSS measurement weights or control strategies based on navigation status feedback. The PL and PS collaborate to achieve a closed-loop function for signal processing and navigation solution, but both the combined navigation and interference discrimination logic are centralized on the PS.

[0062] In addition, the system integrates an Ethernet debug interface and a serial output port, supporting the transmission of positioning results, interference detection flags, navigation status, and other information for host computer communication, remote monitoring, and experimental verification. The entire system utilizes a highly integrated single-board design with standardized interfaces, a compact layout, and clear functional modules, making it suitable for deployment in complex GNSS application environments such as drones, emergency platforms, power facilities, and mobile measurement equipment.

[0063] This embodiment also provides a software architecture built on the ZYNQ XC7Z020 SoC platform. It uses a hardware-software collaborative processing mechanism to effectively decouple the high-parallel anti-interference processing of GNSS signals from navigation fusion reasoning, which are respectively completed by the programmable logic unit (PL) and the embedded processing system unit (PS). The two interact with each other through the AXI standard bus interface for data and control commands, forming a clearly defined embedded anti-interference system structure with clear hierarchical responsibilities. The system software layered structure block diagram is shown below. Figure 5 shown.

[0064] In this system's software architecture, the programmable logic unit (PL) handles the parallel acquisition, interference identification, and suppression of multi-frequency GNSS intermediate frequency (IF) signals, serving as the physical layer core for the system's anti-jamming capabilities. The downconverted IF analog signal is first sampled by an analog-to-digital converter (ADC) and input to the PL, where it enters the digital downconversion module. This module, based on a numerically controlled oscillator (NCO) and a comb-integrator filter (CIC), converts the IF signal into a complex baseband signal. The baseband signal is then input to the spectrum detection module, which employs a short-time Fourier transform (STFT) architecture to perform time-frequency analysis within a fixed time window. Energy spectrum estimation identifies potential interference frequencies and their energy characteristics. The detection results are fed into the adaptive notch filter module, which employs a second-order IIR filter structure and supports online adjustment of notch frequency, bandwidth, and depth. The core control logic dynamically generates filter parameters based on the interference identification results. In the presence of frequency offset, frequency hopping, or multi-frequency interference, the system can deploy multiple notch filters to form a parallel filter array, achieving interference suppression across a wide spectrum. The filtered baseband signal is restored to an intermediate frequency signal through a digital up-conversion module, and then output as an analog signal through a digital-to-analog converter (DAC). This signal is then fed into the subsequent up-conversion circuit and sent back to the GNSS receiver, completing a physical closed-loop front-end anti-interference processing. The PL side also receives configuration commands from the PS side through the AXI-Lite interface to control module states such as signal channels and notch parameters. Information such as interference detection status, center frequency estimation, and filter operation status is then transmitted back to the PS side through the AXI-Stream or DMA mechanism, providing a basis for navigation layer path decisions. Through the above structure, the PL side constructs an adaptive notch filter processing path driven by spectrum detection. This path features module reconfiguration, configurable parameters, and high processing parallelism, making it a key support unit for the system to achieve signal domain anti-interference capabilities.

[0065] The PS runs an embedded navigation fusion and control algorithm, performing system-level state determination and control management. The PS connects to the inertial navigation unit and GNSS receiver module via a serial port, periodically collecting IMU three-axis angular velocity and acceleration information, as well as GNSS pseudorange solution results. The PS internally runs a GNSS / INS integrated navigation filter, employing an extended Kalman filter (EKF) algorithm to fuse multi-source information and output high-precision position, velocity, and attitude estimates. Based on this, the system extracts filter innovation residuals to determine the consistency and physical plausibility of GNSS pseudorange observations. When anomalies such as innovation drift or trajectory jumps are detected, the system triggers a spoofing interference detection mechanism, dynamically assesses the trustworthiness of the GNSS signal, and implements path switching strategies, such as reducing GNSS measurement weight or switching to an inertial navigation-dominated solution path.

[0066] Data and control interaction between the PL and PS is implemented using Zynq's internal AXI architecture. The PS controls PL internal module parameters, including channel selection, notch filter switching, and filter parameter settings, through the AXI-Lite configuration interface. The PL transmits intermediate variables such as interference detection status, spectrum estimation results, and signal strength information back to the PS via AXI-Stream channels or DMA. These variables assist the navigation layer algorithm in state fusion and policy updates. The control path supports interrupt triggering and polling mechanisms to ensure that critical state variables are transmitted and responded to within processing time limits.

[0067] Through this division of labor, the PL implements high-speed interference suppression in the physical signal domain, while the PS is responsible for spurious signal identification and policy control at the navigation information layer. These two functions work together to form a multi-level embedded anti-interference system architecture that combines suppressive interference suppression with deceptive interference identification. This architecture features clear functionality, standardized interfaces, strong scalability, and high real-time processing, making it suitable for a wide range of high-robustness GNSS applications.

[0068] This embodiment also provides a specific PL end processing flow

[0069] In this system, the programmable logic unit (PL) handles GNSS signal sampling, processing, and interference suppression at the physical layer. It implements an adaptive notch filtering process driven by spectrum analysis. The processing flow consists of several functional modules that are sequentially organized. Signal data is transmitted between modules via an on-chip interconnect bus, forming a highly parallel and pipelined anti-interference signal processing chain.

[0070] 1. Analog-to-digital conversion input module

[0071] This module is the starting module of the system's PL-side signal processing chain. Deployed within the programmable logic unit (PL) of the ZYNQ SoC platform, it receives external analog signal sampling results and performs initial digital formatting. The system supports reception of GNSS intermediate frequency (IF) signals from four frequency channels: B1, L1, G1, and B3. The front-end RF chain uses a superheterodyne architecture for I / Q demodulation and frequency conversion on each frequency channel, outputting a dual-channel I / Q analog signal with a center frequency of 4.096 MHz. A total of eight analog IF signals serve as input sources. Each channel's signal is fed into four dual-channel AD9248 ADCs, each with a 65 MHz sampling rate and 14-bit quantization accuracy. The output interface uses a standard LVCMOS parallel digital format.

[0072] The PL receives ADC output data through dedicated I / O ports. Input data reception and synchronization logic are used to align sampling clocks and reassemble data across channels. The system combines each I / Q channel group into a complex data structure, and uniformly organizes the channel index and valid bit. To improve data stability and avoid read / write conflicts, the module employs a dual-buffered "ping-pong" architecture. Two independent FIFOs operate alternately: one buffer is used for data acquisition, while the other is asynchronously read by downstream modules. On-chip control logic controls the switching between buffers. The module integrates channel status control and parameter configuration logic, supporting single-channel or multi-channel operation on demand. Channel enable is configured via a 4-bit control register, with each bit corresponding to the enable state of a channel. Sampling synchronization is triggered by a dedicated synchronization start bit. Upon enable, the module uniformly resets the internal sampling timing counter to establish start alignment. A timing constraint mechanism is implemented in the PL logic to ensure consistent sampling of multi-channel ADC data using a common reference clock. Timing constraints are set in the XDC constraint file of the Vivado project. The set_input_delay function is used to precisely control the sampling edges, and the set_multicycle_path constraint is configured on the multi-channel FIFO write path to ensure stable data transfer and alignment with channel timing, preventing sampling interleaving or data misalignment during high-bandwidth acquisition in the system.

[0073] The module includes a comprehensive input anomaly detection mechanism during operation. All abnormal conditions are mapped to the AXI-Lite address space via status registers, providing real-time access and monitoring on the PS side. The module is assigned an independent AXI-Lite slave interface, with a base address uniformly defined in the system address map file (e.g., 0x43C00000). All register accesses are performed using address offsets. The system defines three types of abnormal events: sampling interruption, channel desynchronization, and data reception anomalies, each of which is recorded in multiple status registers. The STATUS_ERR_FLAG (address offset 0x00) is used to flag sampling interruptions. It is an 8-bit flag, one per channel. The STATUS_DESYNC_FLAG (address offset 0x04) is used to record channel sampling desynchronization and is set if the update timing is detected to be out of tolerance. The STATUS_DATA_ERR (address offset 0x08) identifies abnormal conditions such as constant values ​​or no response in the ADC input data channels. The PS side enables the specified exception source as an interrupt trigger condition by writing IRQ_MASK (address offset 0x10). If an exception event occurs and is not masked, IRQ_STATUS (address offset 0x14) will be automatically set and the interrupt signal IRQ_INPUT_ERR will be triggered and output to the ZYNQ PS side GIC controller; after the interrupt response, the PS clears the corresponding interrupt flag by writing IRQ_CLEAR (address offset 0x18), completing the closed loop of exception event processing.

[0074] The module's output interfaces include: 1. a standard structured complex IQ digital data stream (four groups, 14-bit real and imaginary components, 65 MSPS), which serves as the main data signal for subsequent digital down-conversion modules to receive and process; 2. a status register group and a unified interrupt output signal IRQ_INPUT_ERR, which are used for system anomaly monitoring and control linkage.

[0075] 2. Digital down-conversion module (DDC)

[0076] This module is deployed in the programmable logic (PL) of the Zynq SoC platform, following the analog-to-digital converter input module. It performs digital frequency shifting and bandwidth compression on the four complex IQ IF signals it outputs, producing standardized complex baseband signals for use by the subsequent interference detection and mitigation module. The input signal is complex IF data with a sampling rate of 65 MSPS and 14-bit accuracy, centered at 4.096 MHz. The module outputs a complex baseband IQ data stream with a sampling rate of 4.0625 MSPS and 16-bit accuracy, with a bandwidth limited to 4 MHz to meet the spectral fidelity and dynamic range requirements of GNSS baseband signal processing.

[0077] The module incorporates four independent digital down-conversion chains, each channel comprising a local numerically controlled oscillator (NCO), a complex mixer, a cascaded integrator-comb filter (CIC), a FIR compensation filter, and rate control logic. The NCO utilizes a 32-bit phase accumulator structure, with an independent frequency control word (FCW) per channel. This generates a complex local oscillator (LO) signal corresponding to the input signal, enabling precise spectral shifting. The mixer performs complex multiplication of the input IF signal with the NCO output, converting the spectrum from 4.096 MHz to 0 Hz while preserving the original bandwidth. The mixing result is then passed through the CIC filter for downsampling and anti-aliasing filtering. The CIC filter is set to a decimation ratio of 16, resulting in an output sampling rate of 4.0625 MSPS.

[0078] To correct for the nonideal frequency response of the CIC filter, the module implements a 64th-order FIR compensation filter after each channel. This filter employs a symmetrical structure, with a passband edge of 1.5 MHz, a stopband start of 2 MHz, and out-of-band attenuation better than 60 dB. The FIR coefficients are loaded from an on-chip ROM and automatically written to the filter register structure at system startup. The FIR module operates in a parallel multiply-add structure, outputting 16-bit complex pairs that match the CIC output rate.

[0079] The module is equipped with frequency lock detection logic to monitor the operating stability of the NCO local oscillator frequency. The lock status is determined by a phase observer and written to the status register for use by the PS for scheduling or fault identification. The module's control and status interface is built based on the AXI-Lite protocol. All registers are 32 bits wide, with an address space starting at offset 0x20, avoiding the 0x00-0x18 range used by previous modules and maintaining a consistent register allocation across the system. Specific register definitions are as follows: DDC0_FCW_LOW through DDC3_FCW_LOW (address offsets 0x20, 0x24, 0x28, and 0x2C) are the frequency control word registers for channels 0 through 3, respectively, used to configure the NCO local oscillator frequency. DDC_CFG_CONTROL (address offset 0x30) is the module startup and synchronization control register; bit 0 is the startup flag, and the remaining bits are reserved. DDC_STATUS (address offset 0x34) is the NCO lock status feedback register; the lower four bits indicate the lock status of each of the four channels; the upper bits are reserved. The PS side sets the frequency and controls module startup by writing to the above registers, and can obtain the operating status of each channel NCO in real time by reading the DDC_STATUS register, realizing dynamic configuration and operation monitoring.

[0080] The module's output interface includes four complex baseband IQ data streams (16-bit complex format, 4.0625 MSPS) and a set of lock status flags, which are used to drive the subsequent interference detection module and support PS-side system management decisions. The overall module structure features strong independence, high configurability, and precise bandwidth adaptation, meeting the accuracy and stability requirements of the GNSS IF-to-baseband processing link.

[0081] 3. Time-frequency analysis and interference detection module

[0082] This module is deployed in the Zynq SoC platform's programmable logic (PL), located after the digital downconversion module. It primarily performs interference detection and parameter extraction based on power spectrum perturbations, providing dynamic control information for the subsequent adaptive notch filtering module. The module's input signals are four complex baseband IQ data streams from the digital downconversion module, sampled at a rate of 4.0625 MSPS and formatted as 16-bit fixed-point complex numbers. The system configures an independent spectrum analysis path for each channel, creating a four-channel parallel processing architecture to support multi-frequency signal input.

[0083] The module uses a 256-point fast Fourier transform (FFT) for sliding window spectrum analysis with a window step size of 128 points, forming a 50% overlapping sliding window structure to improve the temporal resolution of spectral perturbations. Input data is uniformly multiplied by a Hamming window function for shaping before entering the FFT. The window coefficients are loaded from a ROM during system initialization. The FFT calculation is based on the Xilinx FFT IP core, which uses fixed-point input and a pipelined architecture. It continuously outputs 256-point complex spectrum results and, in conjunction with the frame completion signal, drives subsequent power spectrum calculations.

[0084] The power spectrum calculation module receives the FFT output and performs a point-by-point amplitude square operation, retaining only the first 128 points of the positive frequency range for subsequent interference detection analysis. The frame update period matches the sliding window step size, generating a power spectrum frame for every 128 sampling points, with a time resolution of approximately 31.5 μs. The resulting spectrum is written to a buffer and used as interference detection input.

[0085] Because the signal power of GNSS signals under normal conditions is far below the thermal noise density, even after front-end filtering and low-noise amplification, it is difficult to directly discern the carrier component in the spectrum. Therefore, this module uses an interference detection method based on power spectrum perturbation. This method does not rely on the presence of valid GNSS signals, but instead identifies suppressive interference by monitoring the locations of short-term abnormal energy increases in the frequency domain.

[0086] The module constructs a frequency-domain background power baseline within each channel to characterize the power spectrum distribution of that channel under non-interference conditions. The background estimation path utilizes a dual-branch structure, consisting of a sliding average filter and a historical minimum filter. After parallel calculations, the smaller value is taken point by point as the final baseline input, balancing response speed and anti-interference stability. The sliding average filter is implemented using a first-order IIR structure, dynamically updating the power spectrum data for each frame using an exponentially weighted method. A configurable smoothing factor determines its sensitivity to short-term power fluctuations. This filter effectively reflects the steady-state variation of the ambient background noise level. The historical minimum filter maintains a sliding window with a depth of 64 frames at each frequency, corresponding to a time span of approximately 2.016 milliseconds (calculated at a 31.5 μs per frame). This path records the minimum power value at each frequency within the specified window, characterizing the background lower limit under the "quietest" conditions over a period of time, providing strong interference resistance. During each frame, the system compares the two estimated results frequency by frequency, selecting the smaller of the two as the current frame's background power baseline and inputting it into the decision maker for spectral disturbance threshold detection. This joint estimation structure can not only quickly respond to subtle fluctuations in the channel background, but also effectively avoid background increases caused by strong interference, thereby improving the system's robustness and detection sensitivity to sudden interference.

[0087] After the background baseline is formed, the system compares the power spectrum of the current frame with the baseline point by point. If the power value of a frequency point exceeds the product of the corresponding background value and the set threshold factor, it is marked as a suspected interference point. All frequency points that exceed the limit will enter the frequency clustering logic, and the system will merge them into interference clusters based on the continuity and energy consistency of the frequency index. For each interference cluster, the system extracts three characteristic parameters: the center frequency is calculated by the weighted frequency mean, the bandwidth is estimated by the frequency span, and the intensity factor is the ratio of the maximum power in the cluster to the background value. Each frame and each channel outputs up to two sets of the highest intensity interference parameters to control resources and interface loads. If there is no effective interference in the current frame, the corresponding parameter output flag is automatically cleared.

[0088] Interference parameters are packaged in a structured data bus, including center frequency (16 bits), bandwidth (8 bits), intensity factor (8 bits), valid flag, update flag, and channel number fields. Each channel has an independent on-chip BRAM buffer for temporary parameter storage, and an update trigger signal notifies the notch module to read the parameters. Parameter reading uses a polling mechanism, and the update flag is automatically cleared after the read is completed to prevent parameter conflicts.

[0089] To support PS access, the system implements a parameter mapping register set, TF_PARAM0 through TF_PARAM3 (offsets 0x50 to 0x5C), at offset 0x50 in the AXI-Lite address space. Each register is 32 bits long and contains, in order, the center frequency index (upper 16 bits), bandwidth (middle 8 bits), and intensity factor (lower 8 bits). Furthermore, to further support the observation of spectrum intensity trends and back-end fusion modeling, the module outputs an additional spectral energy estimate per channel, representing the squared integral of the amplitude of the first 128 points in the power spectrum of the current frame. The system also implements read-only registers, TF_POWER0 through TF_POWER3, at offsets 0x60 to 0x6C, to store this spectral energy value, with 16 bits per channel. The PS can periodically read this value to assess interference field strength changes, adjust integrated navigation filter weights, or model historical interference patterns.

[0090] The module also features independent control and status registers, starting at offset 0x38 and each register being 32 bits wide. These registers include: TF_CTRL (0x38) for the startup and reset control register; TF_THRES_CFG (0x3C) for the spectrum perturbation threshold setting register; TF_STATUS (0x40) for interference detection status feedback, with the lower four bits indicating the presence of interference on each channel; TF_INT_MASK (0x44), TF_INT_STATUS (0x48), and TF_INT_CLEAR (0x4C) for interrupt masking, status flagging, and interrupt clearing, respectively. The PS reads and writes these registers via the AXI-Lite interface, enabling closed-loop status acquisition and processing using either polling or interrupt modes.

[0091] The module's final output consists of two data paths: an interference analysis result path, which outputs a per-channel interference parameter bus (center frequency, bandwidth, intensity factor, and spectral energy estimate) for subsequent notch filter configuration and interference environment assessment; and a baseband signal pass-through path, which forwards the input four-channel complex IQ data (16-bit fixed-point per channel, sampling rate 4.0625 MSPS) directly to subsequent modules without any modification or truncation, without delay. This dual-path output structure decouples interference detection from signal transmission, making it a key analysis module in the system's frequency-domain anti-interference chain.

[0092] 4. Adaptive notch filter module

[0093] This module, deployed in the programmable logic (PL) of the Zynq SoC platform, lies between the time-frequency analysis module and the system's signal return link. It primarily constructs a notch filter based on dynamic interference parameters, enabling real-time suppression of strong interference at the target frequency. The module receives the interference parameters output by the analysis module, including the center frequency index, bandwidth control word, and intensity factor. It then filters the original baseband IQ signal by reconstructing the notch filter coefficients and outputs the suppressed complex signal for subsequent use in the return link.

[0094] The module supports independent operation of four channels: B1, L1, G1, and B3. Each channel input is a complex IQ data stream with a sampling rate of 4.0625 MSPS and a 16-bit fixed-point complex data format. Each channel is equipped with two sets of cascaded reconfigurable notch filter paths to support parallel suppression of multiple clusters of interference. Each notch filter uses a second-order IIR structure, capable of creating frequency domain notches, making it suitable for suppressive interference suppression scenarios.

[0095] The center frequency of the notch filter is converted to the normalized frequency ω by using the frequency index (Freq_Index, ranging from 0 to 127) in the interference parameter. The formula is:

[0096]

[0097] The normalized frequency is used to calculate the cos(ω) term in the notch filter transfer function. The system obtains the required value through a lookup table (LUT) and linear interpolation. The LUT uses a Q1.15 fixed-point format with a resolution of 1 / 1024, achieving an interpolation error better than ±0.001, ensuring that the notch frequency is controlled with an accuracy greater than 1 / 512 of the sampling frequency. The transfer function for each notch filter is:

[0098] H(z)=

[0099] Where r is the pole radius, which is used to control the filter bandwidth and depth. The system converts its value based on the bandwidth control word. The bandwidth calculation formula is:

[0100] -

[0101] Where EBW (Estimated Bandwidth) is the estimated bandwidth (in Hz), Fs is the sampling rate (4.0625 MHz), and r typically ranges from 0.95 to 0.99. Filter coefficients are quantized using the Q2.14 format (16-bit fixed-point) and mapped to the DSP48E1 arithmetic unit within the PL through a pipelined architecture, ensuring real-time operation at high sampling rates.

[0102] The estimated bandwidth (EBW) is output by the preceding "Time-Frequency Analysis and Interference Detection Module." Its calculation method is based on frequency clustering within the power spectrum's disturbance zone. After detecting consecutive frequency points exceeding the limit, the system groups them into interference clusters, and the span between their start and end frequencies is used as the frequency width of the cluster. This frequency span is converted to the actual bandwidth (Hz) using the frequency resolution, which serves as the bandwidth reference value used when configuring the notch filter in this module. This approach dynamically matches the actual width of the interference cluster, enabling adaptive adjustment of the notch filter's frequency coverage area and improving filtering accuracy and effectiveness.

[0103] To prevent unstable response during parameter switching, the module incorporates a "parameter valid flag + frame synchronous loading" mechanism. After detecting interference at the end of the current frame and setting the parameter update flag, the new notch filter coefficients are loaded synchronously at the beginning of the next frame, ensuring stable configuration timing and data processing. If the center frequency is detected to vary by more than two frequency points (greater than 31.25 kHz), the system activates an interpolation buffer mechanism, gradually updating the notch filter coefficients over a four-frame period to achieve smooth dynamic response control.

[0104] The scheduling strategy for multiple notch filter paths is based on a power intensity factor priority ranking mechanism. After extracting all valid interference clusters from the time-frequency analysis results of each frame, the system first sorts them from high to low according to their power intensity factors to identify the most significant interference sources. If more than two interference clusters are detected in a single channel, the system automatically selects the two with the strongest power for notch configuration. Furthermore, to improve resource utilization and avoid filter response overlap, the system evaluates the frequency spacing between interference clusters during parameter screening. If the center frequency spacing between two clusters is less than three frequency points (corresponding to approximately 47.8 kHz), they are considered adjacent or overlapping clusters and merged. After merging, a weighted average is used to estimate the center frequency, and the bandwidth parameters are expanded to cover the original clusters, enabling a single filter to suppress multiple interference sources. Finally, based on the sorting results and merging judgment, the system dynamically configures up to two notch filter paths and writes the results to the effective parameter register. The parameter update flag completes the real-time filter reconstruction process.

[0105] Each notch filter parameter within the module is configured as a register, recording fields such as the current effective parameter, control word, and update time. These registers are mapped via the AXI-Lite interface and made available to the PS for query and access, enabling operations such as operational status monitoring and parameter review. During operation, the system can read back the configuration status of each channel's notch filter in real time, assisting with navigation path scheduling and system health assessment. To support PS-side monitoring and control of the notch filters, the module is equipped with a set of control and status registers accessible via the AXI-Lite interface. These registers are uniformly 32 bits wide, with the address space starting at offset 0x70. Among them, NF_CTRL (0x70) is the module control register, with bit 0 controlling the startup enable and bit 1 controlling the start and stop of the notch function. NF_STATUS (0x74) is the notch status feedback register, with the lower 4 bits indicating whether channels 0 to 3 have valid configurations. NF_UPDATE_FLAG (0x78) is the parameter refresh event flag register, which is used to record the channel number of the most recently completed parameter update. NF_PARAM0 to NF_PARAM3 (address range 0x7C to 0x88) are the current notch filter effective parameter registers for each channel. The structure is 32 bits and includes the center frequency index (high 16 bits), bandwidth control word (middle 8 bits), and intensity factor (lower 8 bits). NF_DEBUG (0x8C) is the debugging and status log register, which is used to record the filter configuration history and operation information to facilitate operation status tracking and system debugging analysis.

[0106] After filtering, the module synchronously outputs the processed complex IQ signals of the four channels, with the same data structure as the input (16-bit fixed-point complex number, sampling rate of 4.0625 MSPS), for reception by the fifth module loopback link, ensuring the continuity and signal consistency of the processing chain after frequency domain suppression.

[0107] 5. Signal synthesis and loopback link module

[0108] This module is deployed in the programmable logic unit (PL) of the ZYNQ SoC platform, located after the adaptive notch filter module. It is mainly used to complete frequency up-conversion, weighted synthesis and digital-to-analog conversion operations on the complex baseband signal after four-channel interference suppression, and output a standardized analog intermediate frequency signal. It is sent back to the system's RF front-end to establish a closed-loop output path for the anti-interference processing link.

[0109] The module inputs four complex IQ data streams (sampling rate 4.0625MSPS, 16-bit fixed-point format) output by the pre-stage notch filter module, corresponding to the B1, L1, G1, and B3 frequencies of the GNSS signal. Each channel is equipped with an independent digital up-conversion (DUC) path, including a numerically controlled oscillator (NCO), a complex rotation unit, and a modulator, to up-convert the baseband signal to a preset intermediate frequency. All up-conversion paths are precisely aligned using a shared reference clock and frame synchronization mechanism. In the module's engineering implementation, the set_input_delay and set_multicycle_path constraints in the XDC constraint file are used to control the path delay and edge sampling window timing, ensuring strict time consistency among the four data paths before synthesis.

[0110] After upconversion, the four complex IF signals are modulated outputs corresponding to each frequency channel, each in a 16-bit fixed-point complex format. To unify the output format and complete the conversion from multiple channels to a single path, the module is equipped with a dedicated complex signal weighted synthesizer. This synchronizes and weights the four IF signals, outputting a single complex IF signal as the system's final digital baseband output.

[0111] The synthesizer module utilizes a parallel architecture. Input signals undergo time-domain synchronization and data format normalization before entering the synthesizer. Each channel's I and Q components are multiplied by their corresponding gain coefficients, expressed in 8-bit fixed-point format and written to configuration registers by the PS during system initialization or operation. After multiplication, the channel results are summed term by term in the complex domain to form a weighted complex signal. To ensure that bit width truncation errors are not introduced during the synthesis process, the system utilizes a bit-width expansion strategy during multiplication and addition. Saturation control logic is used to return the output to 16-bit fixed-point values, and the output amplitude is constrained to within a valid range.

[0112] The synthesis control and scheduling unit performs unified scheduling and timing synchronization for the entire path, ensuring logical consistency of the four-channel data during synthesis. Precise multi-cycle paths and input delay constraints are applied in the PL engineering to ensure data alignment and prevent phase drift or channel asymmetry. Gain configuration uses a packed register approach, written to the SYNTH_GAIN_CFG register (offset address 0x9C), with each channel occupying 8 bits, for a total of 32 bits, which are used to adjust the signal energy contribution ratio at each frequency point. The system supports dynamic modification of gain coefficients during operation, adaptively adjusting based on the navigation scheduling strategy or signal-to-noise ratio estimation results.

[0113] The synthesized digital intermediate frequency signal enters the digital-to-analog conversion path, driving the dual-channel high-speed DAC chip (AD9767) to convert the I and Q paths of the complex signal into analog signals respectively. The I / Q analog signal output by the DAC enters the analog up-conversion module, and the AD8347 analog mixer is used to complete the multiplication and mixing operation with the local oscillator signal. The module local oscillator signal is generated by the ADF4360-4 local oscillator chip. The output frequency can be configured and controlled by the PS end through the SPI bus to adapt to the output requirements of different target frequency bands. The up-conversion structure is consistent with the front-end down-conversion solution in module (1), which facilitates the consistency of system design structure symmetry and spectrum mapping accuracy.

[0114] The analog RF signal output after mixing is a standard GNSS signal frequency band signal, which is output to the receiver front end through the system's RF power amplifier, completing the closed-loop structure from signal acquisition, processing, interference suppression to signal feedback.

[0115] To support the configuration management and operation monitoring of the module by the PS side, the module sets a set of control and status registers based on the AXI-Lite protocol. The register width is 32 bits, and the address space is divided from the offset address 0x90, as follows:

[0116] The module control and status interface includes SYNTH_CTRL (address offset 0x90), which is used to control module startup and function start and stop. Bit 0 indicates overall startup enable, and bit 1 controls the IF synthesis function status. SYNTH_STATUS (address offset 0x94) is the module operation status feedback register. The lower 4 bits indicate whether the current upconversion path of the four channels is working properly. SYNTH_FREQ_CFG (address offset 0x98) is the IF local oscillator frequency configuration register. The frequency index value is written to set the NCO output frequency. SYNTH_GAIN_CFG (address offset 0x9C) is the channel gain configuration register, which is used to set the weighted proportional factor when synthesizing each channel.

[0117] The module ultimately outputs a complex intermediate frequency analog signal (I / Q path). This signal is converted to a GNSS RF signal via the RF front-end's analog upconversion path and fed back to the receiver system's front-end signal interface, achieving a closed-loop transmission chain for interference-resistant signal transmission. All control registers are accessible in real time by the PS for operational monitoring, parameter configuration, and system path management.

[0118] In summary, this module implements the synchronous up-conversion, standardized synthesis, and analog RF loopback functions of multi-channel signals after interference suppression. It is a key output module for building a frequency-domain anti-interference closed-loop link in this system, ensuring the integrity of the system signal path, modulation consistency, and loopback compatibility.

[0119] Table 1: PL side register mapping table

[0120]

[0121] This embodiment also provides a specific PS end processing flow as follows:

[0122] The processing system (PS) within the Zynq SoC platform handles the system's core control and navigation algorithms. It manages register read and write operations within the programmable logic (PL) modules, integrates inertial and GNSS observation data, executes spoofing and jamming detection logic, and provides unified system status scheduling and output control. To enhance system parallelism and modular management efficiency, the PS utilizes a dual-core heterogeneous architecture, with two ARM Cortex-A9 cores independently performing different functional tasks.

[0123] The CPU0 core runs the system scheduling and configuration management module, primarily responsible for register configuration of various PL modules during initialization, status monitoring and interrupt response during operation, interference status identification and reporting, and external data output and interface management, forming the control backbone of the system. The CPU1 core is dedicated to running the integrated navigation solution and interference identification module. This module, based on the extended Kalman filter algorithm, integrates pseudorange information provided by the inertial measurement unit (IMU) and GNSS module, and combines it with PL-side interference detection results for residual analysis and spoofing detection, achieving high-precision and high-stability integrated navigation.

[0124] The PS establishes a data exchange link with peripherals via multiple communication paths. These include receiving RTCM observation data from the GNSS module (update frequency 10 Hz, baud rate 921600) via a serial port; receiving six-axis inertial data from the IMU (update frequency 2000 Hz, baud rate 921600) via a serial port, and processing it through mean smoothing to generate inertial observation data with a 100 Hz update frequency for use by the navigation filter. Simultaneously, the control and status registers of various functional modules on the PL side are accessed via the AXI-Lite bus, establishing configuration writes, status polling, and interrupt response mechanisms. The dual cores establish an intercommunication buffer via shared on-chip memory (OCM), enabling the exchange and synchronization of key data such as navigation status information, interference flags, and innovation sequence statistics.

[0125] This section details the PS-side functional modules based on the system software architecture, covering core processes such as register configuration and scheduling, IMU data management, GNSS observation analysis, integrated navigation filtering and interference identification strategies, and data output and system status release. All modules are numbered and segmented according to processing order and functional boundaries, forming a clearly structured and logically closed operation path.

[0126] (A1) PL register configuration and task scheduling module

[0127] This module is deployed on the ARM Cortex-A9 core CPU0 of the ZYNQ SoC platform. As the main scheduling unit for system operation control, it is fully responsible for register configuration writing, operation status polling, interrupt event response, and sharing and output of system status information of each functional module of the programmable logic unit (PL), realizing unified control and stable scheduling of anti-interference functional links.

[0128] During system initialization, the module configures each PL functional module register item by item according to preset startup parameters. The input acquisition module's channel enable flags and sampling synchronization startup control are controlled via dedicated control registers. The frequency control words for each channel of the digital downconversion module are configured in registers DDC0_FCW_LOW to DDC3_FCW_LOW (offset addresses 0x20 to 0x2C), respectively. The startup command is written to register DDC_CFG_CONTROL (0x30). Local oscillator lock status feedback is provided by register DDC_STATUS (0x34). The notch filter module's startup control is controlled via register NF_CTRL (0x70), and filter status feedback is provided by NF_STATUS (0x74). Current notch filter configuration parameters can be read via registers NF_PARAM0 to NF_PARAM3 (0x7C to 0x88). The signal synthesis module's output control is configured using SYNTH_CTRL (0x90). The local oscillator frequency is set in SYNTH_FREQ_CFG (0x98). The output gain of each channel is set in SYNTH_GAIN_CFG (0x9C). Module operating status feedback is obtained through SYNTH_STATUS (0x94). The interference detection module's interference status is provided by register INTF_FLAG (0x44). The interference detection parameters for each channel are stored in registers INTF_PARAM_CH0 to INTF_PARAM_CH3 (0x48 to 0x54). The current spectrum energy estimate is output by PSD_POWER_LEVEL (0x58). The unified interrupt control module enables interrupt sources using register IRQ_MASK (0x10), reports interrupt event status via IRQ_STATUS (0x14), and clears interrupts via IRQ_CLEAR (0x18).

[0129] During operation, the module uses a 10-millisecond periodic task triggered by a PS-side timer to consistently poll and read the status registers of each functional module. It continuously monitors key indicators such as sampling status, channel synchronization, downconversion local oscillator lock, interference detection status, notch parameter updates, and signal output stability, ensuring real-time system status perception and scheduling link reliability. Furthermore, the module has enabled a unified interrupt response mechanism. When any PL module detects a sampling interruption, channel desynchronization, or parameter anomaly, it issues an interrupt request to CPU0 via the unified interrupt signal line IRQ_INPUT_ERR. During the interrupt response process, the module reads the IRQ_STATUS register to identify the source of the exception, completes exception logging and fault-tolerant response, and clears the interrupt flag via IRQ_CLEAR after the response, ensuring the system's closed-loop responsiveness under abnormal conditions.

[0130] To achieve operational coordination between the dual-core processing systems, the module constructs a structured shared buffer in the PS-side on-chip memory (OCM), with the base address set to 0xFFFF0000. Key system status fields are organized in a unified format. This shared buffer contains the interference detection flag (intf_detect_flag_ch) (a four-bit flag for each channel), the interference detection parameter snapshot (intf_param_ch) (center frequency, bandwidth, and strength factor for each channel), the current notch filter configuration parameters (notch_param_ch) (center frequency and bandwidth for each channel), the GNSS frequency mask control flag (gnss_mask_bitmap) (a four-bit bitmap corresponding to B1 / L1 / G1 / B3), the navigation path switching status word (nav_mode_flag) (indicating whether integrated navigation mode or pure inertial mode), and the system operation timestamp (timestamp_ms) (a reference time in milliseconds for task scheduling). After each register polling cycle, CPU0 writes this status data to a shared buffer, which CPU1 then reads during navigation filtering, interference identification, or path switching. This ensures that all computing units maintain a consistent understanding of the system's operating status. Shared memory reads and writes are coordinated using frame synchronization flags to ensure data consistency and mutual exclusion during cross-core access.

[0131] In addition, the module also outputs system operation status frames through the serial port at a fixed frequency. The frames contain timestamps, key module status, new information statistics, interference detection estimates, and navigation credibility levels, which are used for remote diagnosis, data logging, and visual analysis of system operation.

[0132] In summary, this module establishes a highly reliable operation control path between the PS and PL through a unified register control strategy, a precise state monitoring mechanism, a comprehensive interrupt handling path, and a structured shared memory design. It is a key support module for ensuring the system achieves multi-level anti-interference, path control, and stable navigation output.

[0133] (A2) GNSS / IMU data acquisition and observation preprocessing module

[0134] This module is deployed on the ARM Cortex-A9 core CPU1 of the ZYNQ SoC platform. As the data input front end of the integrated navigation system, it is responsible for receiving, formatting, timing synchronization, reconstructing cache and sharing updates of observation data provided by external GNSS receivers and inertial measurement units (IMUs), providing the navigation filter with highly timely observation information with a unified structure.

[0135] The GNSS receiver module in the system outputs raw pseudorange observation data in RTCM3 format, with an update frequency of 10 Hz and a communication baud rate of 921600. It connects to the ZYNQ PS terminal via a TTL serial port. The IMU module outputs triaxial acceleration and triaxial angular velocity observations with an update frequency of 2000 Hz and a communication baud rate of 921600. It connects to the system via an asynchronous serial port. The module internally uses an asynchronous serial port controller to receive data frames, unpack their structures, and extract fields. It also establishes its own independent time synchronization mechanism and cache structure.

[0136] To ensure a consistent sampling baseline for navigation system input data, the module uses a 10 ms (100 Hz) observation cycle as the system's unified observation cycle. IMU raw data is averaged (i.e., linearly averaged within a sliding window) every 20 consecutive samples to generate equally spaced six-axis inertial observation vectors. GNSS observation data is received every 100 ms, and the satellite number, frequency tags (B1, L1, G1, B3), pseudorange, pseudorange rate, and receiver local time stamp are extracted and aligned. Data from both observation sources is reassembled in a structured buffer, and data pages are exchanged during each navigation cycle using a double-buffering mechanism to ensure consistent data delivery and parallel availability.

[0137] The IMU observation buffer caches the most recent 50 frames (corresponding to 500 ms) of 100 Hz downsampled data, which serves as the integral sliding window for the extended Kalman filter prediction phase. The GNSS buffer retains the most recently parsed frame of data, along with the interference detection flag intf_detect_flag_ch and the GNSS mask flag gnss_mask_bitmap, which are written to shared memory by CPU0. This is used to determine the credibility of multi-source observations during the solution phase.

[0138] The module implements a data integrity check mechanism that covers exceptions such as IMU serial port reception interruption, frame structure corruption, and GNSS timeout and frame loss. IMU reception failure, frame header errors, or invalid data trigger the imu_rx_err_flag status bit. Failure to receive GNSS data for two consecutive cycles (200 ms) triggers the gnss_timeout_flag. Missing or out-of-bounds GNSS or IMU fields sets the obs_parse_err_flag. All exception flags are written to a shared memory structure configured by the A1 module for path control and status determination.

[0139] This module periodically writes and updates the data integrity fields in the shared structure, along with the navigation input observations. This includes the update cycle timestamp (timestamp_ms) and the current data frame status flag, ensuring that the main navigation process has a consistent, complete, and deterministic observation context when reading each cycle. Shared write operations are paced using the frame synchronization bit to avoid access conflicts between CPU0 and CPU1.

[0140] This module builds a complete input observation chain through unified time base reconstruction of high-frequency observation sources, downsampling sliding window design, structured cache organization and shared state synchronization mechanism. It is the basic input support module to ensure the stable operation of integrated navigation filtering and reliable execution of interference identification.

[0141] (A3) Integrated navigation filtering module

[0142] This module is deployed on the ARM Cortex-A9 core CPU1 of the ZYNQ SoC platform. As the core functional unit of the integrated navigation solution, it adopts the extended Kalman filter (EKF) algorithm structure to realize the fusion and state estimation of multi-source navigation information, continuously output high-precision position, velocity and attitude information, and provide new information judgment basis and state residual support for subsequent interference identification and path control modules.

[0143] The filter state variables are uniformly modeled using 15-dimensional state variables, including 3D position error, 3D velocity error, 3D attitude error (in the form of Euler angles or error quaternions), 3D accelerometer bias, and 3D gyroscope bias. The state prediction component runs at 100Hz, using IMU acceleration and angular velocity data provided by the A2 module as input for state propagation and covariance matrix prediction. Each cycle updates the system dynamics equations and propagates the error state, maintaining a continuous estimate of the current motion state.

[0144] The observation update process is executed at a 10Hz frequency, triggered by the arrival of a GNSS observation frame. The observation equation is constructed from the GNSS pseudorange and pseudorange rate information. During this update step, the system calculates the Kalman gain, performs state corrections, and performs covariance contraction. Simultaneously, the innovation residuals and observation information matrix for the current epoch are calculated in real time for subsequent interference detection and credibility assessment.

[0145] The module leverages the GNSS mask control word gnss_mask_bitmap shared with the A1 module during filtering, dynamically adjusting the pseudorange channels currently participating in fusion by frequency. If a frequency is marked as masked, the system automatically removes the corresponding satellite observation from the observation equation, ensuring the reliability and robustness of status updates. Furthermore, the navigation status output includes information about the currently used channel and a mask flag for external systems to facilitate quality management and mode determination.

[0146] Innovation sequences are generated internally by this module and automatically exported to shared memory fields for multi-epoch statistical analysis by the A4 module. The module is designed to support a single-satellite observation rejection strategy, softly rejecting any abnormally amplified innovations detected on a single channel and retaining the impact assessment of the observation in the state variables.

[0147] During the filtering process, the fusion results of each cycle are written into key fields such as the state vector snapshot, velocity vector, attitude angle, and system timestamp through a shared structure. Filter quality parameters such as the innovation mean, mean square error, and covariance main diagonal value are also written into specific quality monitoring fields for subsequent judgment modules to provide interference indication or path switching management.

[0148] In summary, this module implements the extended Kalman filter algorithm based on IMU high-frequency state propagation and GNSS periodic observation updates. It has complete functions such as dynamic path fusion, frequency point selection shielding, and state credibility estimation. It is the core computing module of this system to realize the linkage mechanism of stable navigation and interference detection.

[0149] (A4) Interference detection and navigation status management module

[0150] This module, deployed on the Zynq SoC platform's ARM Cortex-A9 core CPU1, serves as the upper-level control logic unit for the integrated navigation system. It comprehensively analyzes interference information and navigation status quality indicators, performing pseudorange channel shielding, path mode switching, navigation credibility output, and system status management. It operates in conjunction with the navigation filter module, maintaining a 10Hz update cycle, enabling the system's intelligent anti-interference scheduling and steady-state path switching capabilities.

[0151] The interference determination mechanism utilizes multi-source information fusion. The module periodically reads the interference detection flag (intf_detect_flag_ch) and interference parameter (intf_param_ch) written to a shared buffer by CPU0 to determine whether strong interference exists on the PL side and identifies the affected GNSS frequencies using a frequency mapping relationship. Furthermore, the module analyzes the mean, variance, and epoch trend of the innovation residual sequence output by the navigation filter module in real time, identifying typical interference indicators such as sudden changes and slope drift. Innovation statistical indicators are then constructed to supplement the interference determination criteria.

[0152] During each navigation cycle, the module generates a GNSS frequency mask bitmap (gnss_mask_bitmap) based on the above information. This bitmap indicates the pseudorange observation channels that are currently excluded from fusion. This bitmap is written to a shared state structure in real time, allowing the filtering module to dynamically mask observations. If a frequency is marked as a high-confidence interference hit in the current frame, the module immediately masks it. If the interference status remains invalid for three consecutive frames, the mask is removed.

[0153] When the number of available GNSS channels drops below the tolerance threshold (the system defaults to three valid satellite channels from at least two frequencies), or the root mean square error (RMSE) of the innovation residuals output by the integrated navigation filter module exceeds 15 meters for three consecutive epochs, the module automatically executes the navigation path switching strategy. At this point, the module immediately updates the navigation operation mode status word nav_mode_flag to "INS Inertial Hold" mode (control code 0x01) and sets all bits in the gnss_mask_bitmap to 1, indicating that GNSS observations are unavailable. A mask control flag is then sent to the A3 module, causing the filter to stop using GNSS observations for updates and the system to enter a 100Hz pure IMU dead reckoning state to maintain short-term continuous positioning capability. In subsequent operation, if the system detects that more than 5 available channels have been restored and the interference flag is in the interference-free state for 3 consecutive frames (intf_detect_flag_ch is all 0), the module automatically switches the nav_mode_flag state to the combined navigation mode (control code 0x00) and releases the GNSS frequency shielding to achieve navigation recovery closed loop.

[0154] The module also calculates the overall trustworthiness of the current navigation system every cycle and writes it to the shared field nav_trust_level. Trustworthiness is categorized as high, medium, and low, based on four evaluation factors: first, whether all interference strength factors are less than 6dB above the background noise level; second, whether there are more than five available satellites distributed across at least two frequency bands; third, whether the innovation mean is less than 10 meters and the standard deviation is less than 5 meters; and fourth, whether the maximum value of the main diagonal element of the state estimate covariance is less than 50 square meters. If all four conditions are met in the current cycle, the system is marked as high trust (0x00); if two or more conditions are met, the system is marked as medium trust (0x01); otherwise, the system is marked as low trust (0x02). This level information can be used by higher-level management modules for link optimization, positioning authorization, and alarm notification.

[0155] In summary, this module realizes multi-source fusion judgment of interference and observation, dynamic shielding of pseudorange, and intelligent switching control of navigation path in the navigation status management process. It has complete system operation status labeling and credibility output capabilities, and is the core control link of this system with anti-deception interference, path fault-tolerant management, and continuous navigation guarantee.

[0156] (A5) System status output and remote interface module

[0157] This module is deployed on the ARM Cortex-A9 core CPU0 of the ZYNQ SoC platform. It serves as the output channel for external delivery of system operation results and remote information synchronization. It is responsible for uniformly encapsulating key operation information such as the system's current navigation status, interference detection results, path control flags, and credibility assessments, and sending them to external platforms through serial ports or Ethernet interfaces. It supports remote logging, link access control, or system operation loopback verification.

[0158] To improve the compatibility and standardization of the system's external interfaces, this module references the structure and format of the NMEA 0183 communication protocol and designs and implements a custom structured string statement output mechanism. This mechanism uses ASCII encoding and boasts excellent cross-platform parsing capabilities. All statements begin with a $ sign, are separated by commas, and terminate with a * followed by a two-digit XOR checksum. The string ends with \r\n to ensure stable format control and data verification.

[0159] The system defines the following five types of standard output statements. Their specific structures and functions are shown in the following table:

[0160] Table 2: Specific structure and function table of standard output statements

[0161]

[0162] Each statement type has a fixed structure, with fields derived from structured variables written by modules A1-A4 to the shared state buffer. These include key parameters such as timestamp_ms, nav_mode_flag, gnss_mask_bitmap, intf_detect_flag_ch, intf_param_ch, notch_param_ch, nav_trust_level, and navigation status output. The module is scheduled by a system timer during each navigation cycle (default 10 Hz) to execute statement construction, XOR checksum generation, and transmission, generating a stable output data stream.

[0163] The output mechanism supports two operating modes: a fixed-frequency output mode, in which the system outputs $SYSNAV and $SYSMODE statements every second; and an event-driven mode, in which $SYSINTF, $SYSFILT, and $SYSLOG are automatically appended to the output when key status changes such as interference events, path switching, status anomalies, or filter indicator exceeding limits are detected, enabling real-time reporting of key node information.

[0164] The communication interface supports dual serial and Ethernet channels. The default serial output baud rate is 921600, suitable for direct connection to embedded host computers or flight control systems. The Ethernet interface uses the UDP protocol, enabling periodic broadcasting of system status to a specified host address. This makes it suitable for remote control terminals, centralized management platforms, or large-scale distributed systems. The output data syntax strictly adheres to a structured format, making it easy to parse and process.

[0165] In summary, this module achieves stable output and remote synchronization of the system's operating status, anti-interference parameters, and path control flags through standard definitions of structured statements, a unified data encapsulation mechanism, and flexible communication interface configuration. It is a key output component for building the system's open operating architecture and improving maintainability and integration capabilities.

[0166] This embodiment also provides inter-module collaboration and task scheduling mechanisms, as follows:

[0167] The system's overall architectural design leverages the heterogeneous platform advantages of the Zynq SoC, employing a dual-core ARM Cortex-A9 processor and hierarchical decoupling of programmable logic (PL) elements. This enables real-time reception and processing of high-bandwidth data streams, closed-loop control of interference mitigation links, and rapid response for navigation path and policy decisions. Modules collaborate efficiently through AXI-Lite register mapping, interrupt signals, a shared status buffer, and timer synchronization, forming a complete closed-loop "acquisition-processing-judgment-control-output" chain.

[0168] Each processing module on the PL side utilizes a strict signal flow design, starting with the analog-to-digital acquisition and reception module in Module 1, which sequentially completes digital downconversion, interference detection, adaptive notch filtering, digital upconversion, and channel synthesis. Each module communicates in cascade via a structured complex signal path (65MSPS, 14-bit I / Q) and synchronous control signals. Key signal nodes feature control registers and status feedback interfaces. The interference detection module and the notch filter configuration module interact via an internal parameter bus, enabling automatic filter parameter updates. All key PL registers are mapped to the AXI-Lite bus and integrated into the PS address space, enabling real-time configuration and access by CPU0.

[0169] The PS utilizes a dual-core architecture. ARM CPU0 is responsible for system control and management tasks, including PL register access, shared memory construction, interference flag forwarding, status encapsulation and output, and remote communication control. ARM CPU1 is dedicated to high-frequency integrated navigation filtering and innovation residual calculation and judgment logic, ensuring navigation accuracy and minimizing path control response latency. Both CPUs establish a unified system status area via DDR shared memory. All interference parameters, navigation solution results, and control flags are encapsulated and shared in a structured format. Synchronous updates are driven by a scheduling timer, and a mutually exclusive access mechanism prevents data contention.

[0170] The system interrupt mechanism is uniformly triggered by the PL-side event-driven module, including key status signals such as sampling interrupts, data anomalies, and interference events. The interrupt signal is transmitted to CPU0 via the GIC controller. The interrupt service routine quickly identifies the register status bits and executes corresponding processing logic (such as notch refresh and channel masking), and updates the shared memory structure. The synchronization mechanism uses a two-stage timer management. The main timer drives the GNSS / IMU data update rhythm (10Hz / 100Hz), and the secondary timer is responsible for PL status polling and output scheduling (10ms tick).

[0171] The coordinated operation of each module maintains consistency through the control bus and status buffer mapping, and supports module-level independent debugging and system-level soft reset mechanism under hot start, realizing the scalable capabilities of subsystem cascade debugging, fault module location and online update.

[0172] In summary, this system has achieved orderly structure, efficient communication and closed-loop control in terms of module architecture, data channels and collaborative mechanisms, and has constructed an embedded multi-module collaborative anti-interference platform suitable for high-interference environments, multi-channel fusion processing and real-time response of navigation tasks.

[0173] Embodiment 2: This embodiment provides a narrowband single-tone interference verification test, including the following contents:

[0174] To verify the system's detection and identification, notch suppression, and navigation path control capabilities in a typical suppressive narrowband jamming scenario, a single-tone jammer injection experiment was conducted on a laboratory static test platform. The system was connected to an external multi-frequency GNSS measurement antenna and received signals from four frequencies: B1, L1, G1, and B3. The GNSS module output frequency was set to 10 Hz. The IMU module was connected via a serial port, with an original update frequency of 2000 Hz, which was smoothly downsampled to 100 Hz by the PS end. The integrated navigation solution frequency was also 100 Hz.

[0175] The jamming signal was generated by a high-stability RF signal source, with the injection frequency set to the center frequency of the main lobe at frequency B1. It was an unmodulated, fixed-frequency continuous wave single-tone signal with an extremely narrow bandwidth (approximately 0 Hz) and a prominent peak in the spectrum. The jamming power was set to three suppression levels of +60 dB, +75 dB, and +90 dB relative to the GNSS signal (–130 dBm). A single test lasted 300 seconds.

[0176] Within 30-50 ms after interference injection, the system's PL-side spectrum disturbance analysis module detects abnormal frequency domain spikes and accurately extracts the interference frequency index and power parameters, with a center frequency estimation error of less than ±0.1 MHz and a strength estimation error of less than ±1 dB. The interference parameters are synchronously written to the AXI bus shared buffer and passed to the adaptive notch filter module. The filter completes coefficient loading and operation within the next cycle. The overall system response latency is less than 100 ms, and the measured notch depth exceeds 35 dB. The interference signal energy at the target frequency is significantly reduced, and the spectrum is restored to a stable state.

[0177] Upon identifying interference, the system immediately blocks the affected frequency and automatically switches navigation mode to a combination of "IMU-dominated + other frequency-assisted," maintaining a stable and uninterrupted navigation and positioning link. Multiple tests and statistics show that under interference gain conditions of +60 dB and +75 dB, the system's three-dimensional positioning error remains within 3 meters. Under extremely strong interference gain of +90 dB, the C / N0 ratio of some channels drops below 20 dB, and the system's maximum positioning error does not exceed 9 meters. The navigation solution remains continuous and free of jumps.

[0178] Key performance indicators of the system during interference response were obtained through structured data recording and post-processing analysis. Response time was measured based on the timestamp of when the interference flag in the $SYSINTF statement transitioned from zero to valid. The delay between detection and notch response was calculated by subtracting the timestamp from the system's recorded interference injection start time. Test results showed an average response time of less than 100 ms, with a maximum value of no more than 120 ms.

[0179] Positioning error analysis relies on a second-by-second comparison of the 3D position data output by $SYSNAV with the known coordinates of the test platform. The error logs are automatically analyzed by the host computer and an error trend graph is plotted. As shown in Figure 9, positioning error gradually increases with increasing interference intensity but remains within the acceptable engineering range.

[0180] The system's false positive rate was evaluated by running for 6000 seconds under static conditions without interference. The number of false triggers of the interference flag in the $SYSINTF output was analyzed. The results showed zero false positives, resulting in a 0% false positive rate. All performance analyses can be automated using system statements and host computer tools, enabling operational verifiability and engineering evaluation under real-world deployment conditions.

[0181] The test results are shown in Figures 6, 7, 8, 9, and 14, which respectively correspond to the spectrum comparison before and after interference injection, the spectrum comparison before and after notch filtering, the schematic diagram of the navigation path switching process, the relationship curve between positioning error and interference intensity, and the preview of some navigation information sentences output by the system.

[0182] Example 3:

[0183] This embodiment provides a GNSS spoofing interference detection verification test, including the following:

[0184] To verify the system's recognition capabilities and path control mechanisms in GNSS spoofing jamming scenarios, a static experimental platform with controllable pseudo-signal injection was constructed to conduct ground station GNSS spoofing testing. The test system was connected to an external high-gain multi-frequency GNSS measurement antenna to receive signals from the four frequencies B1, L1, G1, and B3. The GNSS module output frequency was set to 10 Hz, and the IMU module's raw data update frequency was set to 2000 Hz. This data was downsampled to 100 Hz after PS-side mean filtering. The integrated navigation solution frequency was synchronized to 100 Hz.

[0185] During the test, a dedicated RF signal source was used to simulate a GNSS spoofing jamming signal, using a ramped power injection method to construct a gradually replacing pseudo-signal. The pseudo-signal's modulation structure, PRN encoding, and navigation data were identical to the real signal. Initially, its power was approximately 15 dB lower than the real signal, and within 30 seconds, it linearly increased to surpass the real signal, achieving full coverage of the B1 frequency band. To simulate target guidance drift, the pseudo-signal dynamically introduced a gradually varying pseudo-range offset, with a maximum drift rate set to 0.1 m / s. The total position offset was kept within 9 meters.

[0186] Initially, the system operated in a normal integrated navigation state. As the prevalence of spurious signals increased, the innovation residuals output by the integrated navigation filter on the PS side exhibited a trend of mean shift and increasing variance. The A4 module employed a sliding window strategy with a length of 100 epochs to dynamically monitor innovation statistics. Upon detecting continuous out-of-bounds behavior, the system simultaneously compared the PL side's spectrum energy anomaly flags to form a basis for joint decision making.

[0187] According to recorded data, the system completes deception identification within an average of 64 seconds after the start of interference injection. The PS-side path control module then updates the navigation mode flag nav_mode_flag to the "IMU hold" state, shielding all GNSS pseudorange observation paths and relying solely on IMU calculations to maintain short-term navigation continuity.

[0188] During the test, the system continuously output structured statements, including $SYSFILT (filter residual information), $SYSINTF (interference identification flag), and $SYSMODE (path control status), at a 1 Hz output period. Recorded data showed that recognition response latency was less than 300 ms, path switching was smooth and without fluctuation, the maximum GNSS positioning error did not exceed 8 meters, and the positioning trajectory showed no jumps or unreasonable drift.

[0189] After the interference source is removed, the system automatically restores the GNSS observation path. After detecting that the innovation statistics have returned to normal, it completes the path switching within an average of 6 seconds, re-enters the integrated navigation operation state, and completes the path recovery loop.

[0190] The performance indicators in this test are as follows: deception interference detection delay (average): 64 seconds; path switching response time: <300 milliseconds; path switching time: 6.1 seconds; maximum positioning error: 8.0 meters; average error: 4.2 meters; misjudgment rate: 0%, and the path control process is stable.

[0191] Various performance parameters are obtained by parsing system log statements. The detection delay is obtained by comparing the first setting time of $SYSINTF with the start time of interference injection. The path switching response time is measured by the setting time of the $SYSMODE switching flag. The positioning error is calculated by comparing the position data in the $SYSNAV statement with the reference trajectory.

[0192] The relevant test results are shown in Figures 10 to 13. Figure 10 shows the dynamic trend of GNSS filter innovations, Figure 11 illustrates the timeline annotation process of the path switching state, Figure 12 compares the deviation trend of the navigation trajectory under spoofing interference and the reference trajectory, and Figure 13 shows the trend of positioning error before and after the path switch. The image data is collected from the test system logs and output statements, and then parsed and visualized by Python scripts.

[0193] Test results demonstrate that in GNSS spoofing jamming scenarios characterized by high fidelity, low initial power, and gradual evolution, the system achieves stable identification using a multi-epoch innovation statistics and front-end power spectrum linkage mechanism. Detection latency is kept below one minute, navigation path switching is timely, and system continuity and stability are excellent, demonstrating strong adaptability to engineering deployments.

[0194] Example 4:

[0195] This embodiment provides a multi-frequency composite interference verification test, including the following:

[0196] To further verify the system's comprehensive interference suppression and path management capabilities in complex interference environments, a multi-frequency composite interference injection test was conducted. The experimental platform was based on a static ground station setup, connected to a multi-band GNSS measurement antenna, and receiving signals from four frequencies: B1, L1, G1, and B3. The GNSS module output frequency was set to 10 Hz, and the IMU module data update frequency was 2000 Hz. After PS-side mean downsampling, the data was reduced to 100 Hz for subsequent integrated navigation solution. The system's navigation solution frequency was also 100 Hz.

[0197] This experiment constructed a combined jamming scenario combining B1 frequency spoofing and L1 frequency suppression. The spoofing signal employed a ramped jamming model, gradually increasing in power over 30 seconds to achieve full coverage of the B1 frequency. The signal structure was consistent with real GNSS signals, with a pseudorange offset of 0.1 m / s introduced to simulate continuous spatial drift. The suppression signal consisted of a fixed-frequency, continuous-wave, single-tone jammer injected directly into the center of the L1 mainlobe. The signal power was set to +85 dB relative to the GNSS signal (–130 dBm), resulting in strong suppression interference, manifested as a strong peak in the spectrum.

[0198] Approximately 60 ms after the interference injection, the system's PL-side spectrum detection module identified an abnormal energy peak at the L1 frequency. The center frequency was estimated with an error of ±0.2 MHz and an error of approximately ±2 dB in intensity. Due to the extremely high interference intensity of the L1 suppression signal, although the notch filter was loaded and operational, its interference rejection at this frequency was relatively weakened. The measured notch depth was approximately 28 dB, and the residual energy in the spectrum remained high. Based on feedback from the PL-side NF_STATUS register and the determination that the C / N ratio was below 20 dB, the PS-side path control module blocked the L1 frequency data path within the first three seconds of system operation, retaining only the B1, G1, and B3 channels for combined navigation to ensure navigation continuity.

[0199] As the power proportion of the B1 spoofing signal gradually increased, the innovation residual output by the PS-side integrated navigation filter showed mean shift and variance expansion characteristics. The system used a 100-epoch sliding window to count the innovation sequence and jointly judged the abnormal energy signs of the PL-side power spectrum. 68.2 seconds after the interference injection, it was determined that a spoofing signal appeared at the B1 frequency point. The nav_mode_flag was then updated to the "IMU hold" state, blocking all GNSS pseudorange observation data and entering a pure IMU calculation path to maintain short-term continuous navigation.

[0200] The experimental results are as follows Figure 13-16 As shown, during the experiment, system statements output a stable 1 Hz frequency. The $SYSFILT statement was used to record residual information, the $SYSINTF statement recorded interference determination results, and the $SYSMODE statement reflected the path control status. Log analysis and performance evaluation were performed using a Python script. The notch response delay was measured by comparing the interference injection timestamp with the filter NF_PARAM register update timestamp, with an average value of approximately 112 ms. The spoofing detection delay was calculated by comparing the first set time of the $SYSINTF flag with the start point of B1 interference injection, and was measured to be 68.2 seconds. The path switch response delay was less than 300 ms. After path blocking and updating, the navigation solution remained continuous, with no trajectory jumps. Positioning error was obtained by comparing the position output by the $SYSNAV statement with the ground station reference coordinates. The maximum error before B1 spoofing was detected was 10.1 meters, and after entering IMU hold, the error remained within 7.3 meters. After the spoofing interference ceased, the system reintroduced GNSS observations, completed path reversion within 5.6 seconds, and the system returned to integrated navigation mode.

[0201] Test results show that in a combined "spoofing + suppression" interference environment, the system is limited by both signal quality and filter suppression capabilities. The notch depth is slightly lower than in a single suppression scenario, and deception detection latency is also increased. However, the system still achieves stable interference identification and path switching control. Test data shows a maximum positioning error of 10.1 meters, an average error of approximately 5.8 meters during the IMU hold period, a false detection rate of 0%, and stable system output path control actions, demonstrating adaptability to engineering deployments under combined interference conditions.

[0202] The basic principles, main features and advantages of the present invention are shown and described above. It is obvious to those skilled in the art that the present invention is not limited to the details of the above exemplary embodiments, and that the present invention can be implemented in other specific forms without departing from the spirit or basic features of the present invention.

[0203] In addition, it should be understood that although this specification is described in terms of implementation methods, not every implementation method contains only one independent technical solution. This narrative method of the specification is only for the sake of clarity. Those skilled in the art should regard the specification as a whole. The technical solutions in each embodiment can also be appropriately combined to form other implementation methods that can be understood by those skilled in the art.

Claims

1. GNSS anti-interference receiver system based on RF front-end-INS joint assistance, characterized by: The system's hardware architecture includes a signal downconversion board and a signal processing board. The downconversion board downconverts the multi-frequency RF signals received by the GNSS antenna and outputs two pairs of analog IQ intermediate frequency (IF) signals, providing the raw input for subsequent anti-interference processing. The signal processing board integrates a ZYNQ programmable SoC chip, an analog-to-digital / digital-to-analog converter, an inertial navigation module communication interface, and a signal output unit, completing IF signal sampling, anti-interference digital processing, navigation fusion solution, and path management. The system uses an external GNSS measurement antenna to receive navigation satellite signals from multiple frequency bands. The signal first passes through a front-end low-noise amplifier and a T-type attenuator for gain control and power conditioning. The conditioned RF signal is then divided into four channels by a four-power splitter, each entering the RF anti-interference path at the corresponding frequency. The system's software architecture is built on the ZYNQ XC7Z020 SoC platform and utilizes a hardware-software collaborative processing mechanism to effectively decouple the highly parallel GNSS signal anti-interference processing and navigation fusion reasoning, which are respectively implemented by the programmable logic unit and the embedded processing system unit.

2. The GNSS anti-interference receiver system based on RF front-end-INS joint assistance according to claim 1 is characterized in that: The baseband signal after interference suppression processing is resynthesized into an intermediate frequency signal through digital up-conversion and sent to the DAC from the PL end through the LVCMOS interface to complete the digital-to-analog conversion. The signal is then up-converted through the local oscillator-mixer structure to restore it to the original frequency band. Finally, it is output to the signal input port of the GNSS receiver through the power amplifier, completing the closed-loop transmission of RF-level anti-interference processing.

3. The GNSS anti-interference receiver system based on RF front-end-INS joint assistance according to claim 2 is characterized in that: It also includes an inertial navigation module, which communicates with the ZYNQ PS terminal through a TTL serial port to provide three-axis angular velocity and acceleration information; The GNSS receiver module is connected to the ZYNQ PS terminal via a TTL serial port and outputs data in RTCM3 format. The ZYNQ PS terminal runs a GNSS / INS tightly integrated navigation filter, extracts filter innovation residuals based on IMU data and pseudorange solution results, identifies pseudorange drift anomalies, and assists in determining potential deceptive interference.

4. The GNSS anti-interference receiver system based on RF front-end-INS joint assistance according to claim 1 is characterized in that: It also includes a PL-side processing flow, in which the programmable logic unit is responsible for sampling, processing, and interference suppression of GNSS signals at the physical layer. An adaptive notch filter processing path driven by spectrum analysis is constructed. The processing flow is composed of several functional modules in sequence. Signal data is transmitted between modules through an on-chip interconnection bus, forming a highly parallel and pipelined anti-interference signal processing chain. The functional modules include an analog-to-digital conversion input module, a digital down-conversion module, a time-frequency analysis and interference detection module, an adaptive notch filter module, and a signal synthesis and loopback link module.

5. The GNSS anti-interference receiver system based on RF front-end-INS joint assistance according to claim 4 is characterized in that: The analog-to-digital conversion input module is the starting module of the system's PL-side signal processing link and is deployed in the programmable logic unit of the ZYNQ SoC platform. It is used to receive external analog signal sampling results and complete initial digital format processing. The system supports receiving GNSS intermediate frequency signals of four frequency channels: B1, L1, G1, and B3. The front-end RF link uses a superheterodyne architecture to perform IQ demodulation and frequency conversion on each frequency signal, and outputs an I / Q dual-channel analog signal with a center frequency of 4.096 MHz. A total of eight analog intermediate frequency signals serve as input sources. Each channel signal is connected to four dual-channel analog-to-digital converters, with a sampling rate of 65 MHz per channel, a quantization accuracy of 14 bits, and an output interface in the LVCMOS standard parallel digital format. During module operation, a complete input anomaly detection mechanism is included, and all abnormal states are mapped to the AXI-Lite address space through the status register group for real-time access and monitoring by the PS side. The digital down-conversion module is deployed in the programmable logic unit of the ZYNQ SoC platform, located after the analog-to-digital conversion input module. It is used to perform digital frequency shifting and bandwidth compression on the four complex IQ intermediate frequency signals output by the module, and output standardized complex baseband signals for use by the subsequent interference detection and suppression module. The input signal is complex intermediate frequency data with a sampling rate of 65 MSPS and 14-bit accuracy, and the center frequency is 4.096 MHz. The module output signal is a complex baseband IQ data stream with a sampling rate of 4.0625 MSPS and 16-bit accuracy. The bandwidth is controlled within 4 MHz to meet the spectrum fidelity and dynamic range requirements of GNSS baseband signal processing; the module is equipped with frequency lock status detection logic to monitor the operating stability of the NCO local oscillator frequency. The lock status is determined by the phase observer and written into the status register for use by the PS end scheduling or fault identification.

6. The GNSS anti-interference receiver system based on RF front-end-INS joint assistance according to claim 4 is characterized in that: The time-frequency analysis and interference detection module is deployed in the programmable logic unit of the ZYNQ SoC platform, located after the digital down-conversion module. It is mainly used for interference detection and parameter extraction based on power spectrum perturbations, and provides dynamic control information for the subsequent adaptive notch filtering module. The module's input signal is four complex baseband IQ data streams from the digital down-conversion module, with a sampling rate of 4.0625 MSPS and a data format of 16-bit fixed-point complex numbers. The system configures an independent spectrum analysis path for each channel, building a four-channel parallel processing structure to support multi-frequency signal input. The module uses a 256-point fast Fourier transform to implement sliding window spectrum analysis with a window step size of 128 points, forming a 50% overlapping sliding window structure to improve the time resolution of spectral perturbations. The input data is uniformly multiplied by a Hamming window function for shaping before being sent to the FFT. The window function coefficients are loaded from the ROM during system initialization. The adaptive notch filter module is deployed in the programmable logic unit of the ZYNQ SoC platform, located between the time-frequency analysis module and the system signal loopback link. It is mainly used to construct a notch filter based on dynamic interference parameters to achieve real-time suppression of strong interference at the target frequency point. The module receives the interference parameters output by the analysis module, including the center frequency index, bandwidth control word, and intensity factor information, filters the original baseband IQ signal by reconstructing the notch filter coefficients, and outputs the suppressed complex signal for use in the subsequent loopback link. The module supports independent operation of four channels: B1, L1, G1, and B3. The input of each channel is a complex IQ data stream with a sampling rate of 4.0625 MSPS and a data format of 16-bit fixed-point complex numbers. Each channel is internally configured with two sets of series-connected reconfigurable notch filter paths to support parallel suppression of multiple clusters of interference. Each set of notches adopts a second-order IIR structure and has the ability to construct frequency domain notches, which is suitable for suppressive interference suppression scenarios. The center frequency of the notch filter is converted by the frequency index in the interference parameter to calculate the normalized frequency ω. The formula is: The normalized frequency is used to calculate the cos(ω) term in the notch filter transfer function. The system obtains the required value through a lookup table and linear interpolation mechanism. The LUT uses the Q1.15 fixed-point format with a resolution of 1 / 1024, which can achieve an interpolation error better than ±0.001, ensuring that the notch frequency control accuracy is higher than 1 / 512 of the sampling frequency. The transfer function of each notch filter group is as follows: H(z)= Where r is the pole radius, which is used to control the bandwidth and depth of the filter. The system converts its value based on the bandwidth control word. The bandwidth calculation formula is: - Where EBW is the estimated bandwidth, Fs is the sampling rate, and r typically ranges from 0.95 to 0.

99. The filter coefficients are quantized using the Q2.14 format and mapped to the DSP48E1 arithmetic unit inside the PL through a pipeline structure.

7. The GNSS anti-interference receiver system based on RF front-end-INS joint assistance according to claim 4 is characterized in that: The signal synthesis and loopback link module is deployed in the programmable logic unit of the ZYNQ SoC platform, located after the adaptive notch filter module. It is mainly used to complete frequency up-conversion, weighted synthesis and digital-to-analog conversion operations on the complex baseband signal after four-channel interference suppression, and output a standardized analog intermediate frequency signal, which is sent back to the system's RF front-end to build a closed-loop output path for the anti-interference processing link; the module input is the four complex IQ data streams output by the previous notch filter module, corresponding to the four frequency points B1, L1, G1, and B3 of the GNSS signal respectively. The system configures an independent digital up-conversion path for each channel, including a digitally controlled oscillator, a complex rotation unit and a modulator, for up-converting the baseband signal to a preset intermediate frequency point.

8. The GNSS anti-interference receiver system based on RF front-end-INS joint assistance according to claim 1, characterized in that: It also includes a processing system in the ZYNQ SoC platform, which is used to manage the register read and write of each module of the programmable logic unit, the fusion processing of inertial and GNSS observation data, the execution of deception interference identification logic, and the unified scheduling and output control of the system status. To improve the parallelism and modular management efficiency of system operation, the PS side is constructed with a dual-core heterogeneous structure, with two ARM Cortex-A9 cores independently undertaking different functional tasks. The processing system in the ZYNQ SoC platform includes multiple PS-side functional modules, including a PL register configuration and task scheduling module, a GNSS / IMU data acquisition and observation preprocessing module, an integrated navigation filtering module, an interference detection and navigation status management module, and a system status output and remote interface module.

9. The GNSS anti-interference receiver system based on RF front-end-INS joint assistance according to claim 8, characterized in that: The PL register configuration and task scheduling module is deployed on the ARM Cortex-A9 core CPU0 of the Zynq SoC platform. As the main scheduling unit for system operation control, it is fully responsible for register configuration writing, operation status polling, interrupt event response, and sharing and outputting system status information for each functional module of the programmable logic unit (PL). This realizes unified control and stable scheduling of the anti-interference functional link. The GNSS / IMU data acquisition and observation preprocessing module is deployed on the ARM Cortex-A9 core CPU1 of the Zynq SoC platform. As the data input front end of the integrated navigation system, it is responsible for receiving, formatting, timing synchronization, reconstructing cache, and sharing and updating observation data provided by external GNSS receivers and inertial measurement units, providing the navigation filter with highly timely observation information with a unified structure. The integrated navigation filtering module is deployed on the ARM Cortex-A9 core CPU1 of the ZYNQ SoC platform. As the core functional unit of the integrated navigation solution, it adopts the extended Kalman filter algorithm structure to achieve the fusion and state estimation of multi-source navigation information, continuously output high-precision position, velocity and attitude information, and provide new information judgment basis and state residual support for the subsequent interference identification and path control modules. The interference detection and navigation status management module is deployed on the ARM Cortex-A9 core CPU1 of the ZYNQ SoC platform. As the upper-level control logic unit of the integrated navigation system, it is responsible for comprehensively analyzing interference information and navigation status quality indicators, completing pseudo-range channel shielding, path mode switching, navigation credibility output and system status management functions. The module operates in coordination with the navigation filter module, maintaining a 10Hz update cycle, and realizing the system's anti-interference intelligent scheduling and path steady-state switching capabilities. The system status output and remote interface module is deployed on the ARM Cortex-A9 core CPU0 of the ZYNQ SoC platform. It serves as the output channel for external delivery of system operation results and synchronization of remote information. It is responsible for uniformly encapsulating the system's current navigation status, interference detection results, path control flags and key operation information of credibility assessment, and sending them to the external platform through the serial port or Ethernet interface, supporting remote logging, link access control or system operation loopback verification.

10. The GNSS anti-interference receiver system based on RF front-end-INS joint assistance according to claim 1, characterized in that: Each processing module on the PL side adopts a strict signal flow design. Starting with the analog-to-digital acquisition and reception module in module 1, it sequentially completes digital down-conversion, interference detection, adaptive notch filtering, digital up-conversion, and channel synthesis. Each module achieves cascade communication through structured complex signal channels and synchronous control signals. Key signal nodes are equipped with control registers and status feedback interfaces. The interference detection module and the notch filter configuration module interact via an internal parameter bus to achieve automatic filter parameter updates. All key PL registers are mapped to the AXI-Lite bus and integrated into the PS address space. They are configured and accessed in real time by CPU0. The PS adopts a dual-core architecture. ARM CPU0 is responsible for system control and management tasks, including PL register access, shared memory construction, interference flag forwarding, status encapsulation output, and remote communication control. ARM CPU1 is dedicated to high-frequency integrated navigation filtering tasks and innovation residual calculation and judgment logic, ensuring navigation accuracy and minimizing path control response latency. The system interrupt mechanism is uniformly triggered by the PL-side event-driven module, including sampling interrupts, data anomalies, and interference event key states. The interrupt signal is sent to CPU0 through the GIC controller. The interrupt service routine quickly identifies the register status bit and executes the corresponding processing logic, and updates the shared memory structure. The synchronization mechanism uses a two-level timer management. The main timer drives the GNSS / IMU data update rhythm, and the sub-timer is responsible for PL status polling and output scheduling.

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