SSD multi-layer pre-reading method and device, computer equipment and storage medium

Abstract

The invention discloses an SSD multi-layer pre-reading method and device, computer equipment and a storage medium, and relates to the technical field of SSD pre-reading. The method comprises the steps that whether a preset pre-reading condition is triggered or not is judged; if the preset pre-reading condition is triggered, loading the data into a multi-layer pre-reading buffer area of the solid state disk; if a read command is received, judging whether the read command hits the multi-layer pre-read buffer area or not; and if the read command hits the multi-layer pre-read buffer area, reading target data corresponding to the read command from the multi-layer pre-read buffer area. According to the method, the NAND inherent cache resources are reused, so that the pre-read data capacity is expanded by multiple times, and hardware cost does not need to be newly increased; when the hit occurs, the physical reading delay of the NAND array is thoroughly avoided, and the traditional serial operation is converted into buffer area direct reading. For a sequential read scene, most read commands skip an NAND access link through multi-stage buffering, and the average delay is compressed from a hundred microsecond level to a microsecond level transmission time, so that the performance step-type improvement is realized.

Description

Technical Field

[0001] The present invention relates to the field of SSD pre-reading technology, and in particular to an SSD multi-layer pre-reading method, device, computer equipment, and storage medium. Background Art

[0002] Solid-state drives (SSDs) typically face a high volume of sequential read operations. In these scenarios, there is a time gap between read commands issued by the host. If the server must wait for each command to arrive before accessing the NAND flash memory to retrieve data, response latency will increase significantly.

[0003] To optimize performance, existing solutions identify sequential read patterns and proactively preload predicted data into the cache when the host doesn't issue subsequent commands. However, this solution relies on sufficient cache space to store the pre-read data, and consumer-grade SSDs have extremely limited on-chip memory capacity due to cost constraints.

[0004] Under the strict cost constraints of consumer-grade SSDs, there is a fundamental conflict between minimal memory resources and the demand for read-ahead performance. Overcoming memory capacity limitations and building an efficient read-ahead mechanism to improve sequential read performance has become a pressing technical challenge. Summary of the Invention

[0005] Embodiments of the present invention provide an SSD multi-layer pre-reading method, apparatus, computer device, and storage medium, aiming to solve the technical problem of how to break through memory capacity limitations and build an efficient pre-reading mechanism to improve sequential read performance.

[0006] In a first aspect, an embodiment of the present invention provides an SSD multi-layer pre-reading method, which includes:

[0007] Determine whether the preset pre-reading condition is triggered;

[0008] If a preset pre-read condition is triggered, the data is loaded into the multi-layer pre-read buffer of the solid-state drive, which includes the SSD on-chip memory, NAND Cache Buffer, and NAND Page Buffer;

[0009] If a read command is received, determining whether the read command hits the multi-layer pre-read buffer;

[0010] If the read command hits the multi-layer pre-read buffer, target data corresponding to the read command is read from the multi-layer pre-read buffer.

[0011] A further technical solution is that the determination of whether a preset pre-reading condition is triggered includes:

[0012] Determine whether the logical addresses of the read commands sent by the host are continuous;

[0013] If the logical addresses of the read commands issued by the host are continuous, determine whether the cumulative amount of data sequentially read by the host is greater than a preset data amount threshold;

[0014] If the cumulative value of the amount of data sequentially read by the host is greater than a preset threshold, it is determined that a preset pre-read condition is triggered.

[0015] A further technical solution is that the step of loading data into the multi-layer pre-read buffer of the solid state drive includes:

[0016] Based on the preset pre-read depth, the data is loaded and stored in the SSD on-chip memory, the NAND Cache Buffer and the NAND Page Buffer in sequence according to the logical address order read sequentially by the host.

[0017] A further technical solution is that the determining whether the read command hits the multi-layer pre-read buffer includes:

[0018] The multi-layer pre-read buffers are sequentially checked in the order of the SSD on-chip memory → the NAND Cache Buffer → the NAND Page Buffer to see whether the target data requested by the read command exists.

[0019] A further technical solution is that after reading the target data corresponding to the read command from the multi-layer pre-read buffer, the method further includes

[0020] The target data is deleted from the multi-layer pre-read buffer.

[0021] A further technical solution is that after deleting the target data from the multi-layer pre-read buffer, the method further includes:

[0022] The loaded data is stored in the multi-layer read-ahead buffer.

[0023] A further technical solution is that the method further comprises:

[0024] If a write command is received, determining whether the write command hits the multi-layer pre-read buffer;

[0025] If the write command hits the multi-layer read-ahead buffer, the data hit by the write command is marked as invalid in the multi-layer read-ahead buffer.

[0026] In a second aspect, an embodiment of the present invention further provides an SSD multi-layer pre-reading device, which includes a unit for executing the above method.

[0027] In a third aspect, an embodiment of the present invention further provides a computer device, which includes a memory and a processor, wherein a computer program is stored in the memory, and the processor implements the above method when executing the computer program.

[0028] In a fourth aspect, an embodiment of the present invention further provides a computer-readable storage medium, wherein the storage medium stores a computer program, and the computer program can implement the above method when executed by a processor.

[0029] Embodiments of the present invention provide a multi-layer pre-read method, apparatus, computer device, and storage medium for SSDs. The method includes: determining whether a preset pre-read condition is triggered; if the preset pre-read condition is triggered, loading data into a multi-layer pre-read buffer of a solid-state drive, the multi-layer pre-read buffer comprising SSD on-chip memory, NAND cache buffer, and NAND page buffer; upon receiving a read command, determining whether the read command hits the multi-layer pre-read buffer; and if the read command hits the multi-layer pre-read buffer, reading the target data corresponding to the read command from the multi-layer pre-read buffer. By constructing a multi-layer pre-read buffer comprising SSD on-chip memory, NAND cache buffer, and NAND page buffer, data is loaded in layers when the pre-read condition is triggered, allowing the target data to be directly retrieved from the buffer when a read command hits. This solution overcomes the memory capacity limitations of consumer-grade SSDs by reusing NAND's inherent cache resources to expand pre-read data capacity several times without increasing hardware costs. When a hit occurs, the physical read delay of the NAND array (especially the time-consuming cell data transfer phase) is completely avoided, converting traditional serial operations into direct buffer reads. For sequential read scenarios, multi-level buffering allows most read commands to skip the NAND access link, compressing the average latency from hundreds of microseconds to microsecond transmission time, achieving a step-by-step performance improvement. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0031] Figure 1 A schematic diagram of a flow chart of an SSD multi-layer pre-reading method provided by an embodiment of the present invention;

[0032] Figure 2 A schematic block diagram of a computer device provided in an embodiment of the present invention. DETAILED DESCRIPTION

[0033] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of them. All other embodiments obtained by ordinary technicians in this field based on the embodiments of the present invention without making any creative efforts shall fall within the scope of protection of the present invention.

[0034] It will be understood that when used in this specification and the appended claims, the terms “comprises” and “comprising” indicate the presence of described features, integers, steps, operations, elements and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or groups thereof.

[0035] It should also be understood that the terminology used in this specification is for the purpose of describing particular embodiments only and is not intended to limit the present invention. As used in the specification and appended claims, the singular forms "a," "an," and "the" are intended to include the plural forms unless the context clearly indicates otherwise.

[0036] It should be further understood that the term "and / or" used in the present description and the appended claims refers to and includes any and all possible combinations of one or more of the associated listed items.

[0037] As used in this specification and the appended claims, the term "if" can be interpreted as "when" or "upon" or "in response to determining" or "in response to detecting," depending on the context. Similarly, the phrase "if it is determined" or "if [described condition or event] is detected" can be interpreted as meaning "upon determination" or "in response to determining" or "upon detection of [described condition or event]" or "in response to detecting [described condition or event]," depending on the context.

[0038] See also Figure 1 An embodiment of the present invention provides an SSD multi-layer pre-reading method, the method comprising the following steps:

[0039] S1, determining whether a preset pre-reading condition is triggered.

[0040] In a specific implementation, it is first determined whether a preset pre-reading condition is triggered. The pre-reading condition may specifically be a continuous reading condition, that is, it is determined whether a continuous reading situation currently exists.

[0041] For example, in some preferred embodiments, the above step of "determining whether the preset pre-read condition is triggered" includes: determining whether the logical addresses of the read commands issued by the host are continuous; if the logical addresses of the read commands issued by the host are continuous, determining whether the cumulative amount of data read sequentially by the host is greater than the preset data amount threshold; if the cumulative value of the amount of data read sequentially by the host is greater than the preset threshold, determining that the preset pre-read condition is triggered.

[0042] In specific implementations, a dual judgment mechanism based on logical address continuity and cumulative data volume thresholds accurately identifies true sequential read scenarios. First, logical address continuity screening eliminates interference from pseudo-random accesses, ensuring that pre-reading only affects sequential reads. Second, the cumulative data volume threshold is set to filter out fragmented, small-scale sequential reads (such as requests shorter than the NAND page length), avoiding resource waste caused by ineffective pre-reading. This hierarchical triggering strategy allocates pre-reading resources to high-value scenarios—long continuous data streams—optimally matching limited buffer depth with host access patterns.

[0043] For example, when a host processes large video files, a cumulative threshold mechanism ensures that pre-read depth covers fragments of the entire file, preventing resources from being interrupted by short, sequential requests. Furthermore, the configurable threshold parameters adapt to different application scenarios (such as the differing pre-read requirements for database logging and media playback), improving resource utilization efficiency and acceleration-to-revenue ratio at the system level.

[0044] S2: If a preset pre-read condition is triggered, data is loaded into the multi-layer pre-read buffer of the solid-state drive, which includes the SSD on-chip memory, NAND Cache Buffer, and NAND Page Buffer.

[0045] In specific implementations, NAND Array is an internal storage device of the SSD, which includes the following parts:

[0046] NAND CellArray: The physical storage unit (Cell) structure for storing data, which represents data through the 0 / 1 state of each cell, thereby realizing power-off data storage

[0047] NAND Page Buffer: NAND internal page buffer, used to store data loaded from NAND CellArray, which is lost when power is off

[0048] NAND Cache Buffer: The cache buffer inside the NAND is used to interact with the controller and is lost when power is off.

[0049] In a typical read scenario, data is read from the NAND Cell Array, loaded into the Page Buffer, then loaded into the Cache Buffer, and then sent back to the host.

[0050] In the embodiment of the present invention, a multi-layer buffer is set, and the specific configuration is as follows:

[0051] First layer: SSD on-chip memory (high speed, smallest capacity).

[0052] Second layer: NAND Cache Buffer (medium speed, medium capacity).

[0053] The third layer: NAND Page Buffer (low speed, largest capacity).

[0054] When the preset read-ahead condition is triggered, the data is loaded into the multi-layer read-ahead buffer of the solid-state drive.

[0055] In some preferred embodiments, the above step of "loading data into the multi-layer pre-read buffer of the solid-state drive" specifically includes the following steps: based on a preset pre-read depth, the data is loaded and stored in the SSD on-chip memory, the NAND Cache Buffer and the NAND Page Buffer in sequence according to the logical address order read sequentially by the host.

[0056] In a specific implementation, the pre-reading depth can be pre-set by those skilled in the art according to actual needs, and the present invention does not specifically limit this. The pre-reading depth is used to indicate the amount of pre-read data.

[0057] The hierarchical loading strategy of filling data into the SSD on-chip memory → NAND Cache Buffer → NAND Page Buffer in the order of host access is essentially an optimization of the matching between access probability and storage speed.

[0058] Data that is accessed sooner is stored in a higher-speed buffer (such as SSD on-chip memory), achieving three core benefits: First, ensuring that the most frequently accessed data is at the lowest latency level, maximizing performance gains when a hit occurs; second, leveraging the large capacity of the NAND Page Buffer to store long-term data (such as data at the end of a sequential stream), even if the host suddenly jumps to access a remote location, the third-level buffer can still be used to avoid real-time NAND reads; third, layered loading naturally forms a data elimination sequence - when new pre-read data is loaded into memory, older data is sequentially transferred to the lower-level buffer, avoiding the risk of hot data being accidentally overwritten in traditional circular buffers. This timeline-based data arrangement enables multiple layers of buffers to form a collaborative cache chain rather than an isolated storage pool, greatly improving the overall hit rate.

[0059] S3: If a read command is received, determine whether the read command hits the multi-layer pre-read buffer.

[0060] In a specific implementation, if a read command is received, it is determined whether the read command hits the multi-layer pre-read buffer.

[0061] For example, in some preferred embodiments, the above step of "determining whether the read command hits the multi-layer pre-read buffer" specifically includes the following steps: checking in sequence whether the target data requested by the read command exists in the multi-layer pre-read buffer in the order of the SSD on-chip memory → the NAND Cache Buffer → the NANDPage Buffer.

[0062] In practice, a progressive hit determination mechanism checks the SSD's on-chip memory, NAND cache buffer, and NAND page buffer in this order. This is essentially a balancing act between access cost and hit probability. Priority is given to searching the high-speed but scarce memory tier, as a hit results in extremely fast responses (microseconds), while a miss only adds a few nanoseconds of detection overhead. Next, the medium-capacity but high-cost cache buffer is searched. Although a hit in this tier requires additional data transfer (such as from the cache buffer to the host), it still saves hundreds of microseconds of latency compared to NAND reads. Finally, the large-capacity but high-latency page buffer is searched as the final layer of pre-read data.

[0063] This hierarchical query strategy achieves three optimizations: 1) minimizing average query overhead—90% of hits occur in the first two high-speed layers; 2) avoiding bus congestion caused by frequent access to the low-speed layers (if reverse querying the Page Buffer is prioritized, it will increase invalid bus occupancy); and 3) synergizing with the data loading order—the most recently loaded data is placed in the priority detection layer, in line with the principle of temporal locality.

[0064] S4: If the read command hits the multi-layer pre-read buffer, read the target data corresponding to the read command from the multi-layer pre-read buffer.

[0065] In a specific implementation, if the read command hits the multi-layer pre-read buffer, the target data corresponding to the read command is read from the multi-layer pre-read buffer.

[0066] The embodiment of the present invention constructs a multi-layer pre-read buffer architecture including SSD on-chip memory, NAND Cache Buffer and NAND Page Buffer. When the pre-read condition is triggered, the data is loaded into different levels of buffers in layers, and the data is directly extracted from the corresponding buffer when the read command hits. This solution breaks through the fundamental limitation of the on-chip memory capacity of consumer-grade SSDs: on the one hand, the inherent Cache Buffer and Page Buffer of NAND are used as the second and third level caches to expand the pre-read data capacity several times without increasing the hardware cost; on the other hand, the data access path is diversified through a hierarchical storage mechanism. When the host command hits the buffer, the physical read delay of the NAND array (especially the longest-time transmission stage from Cell data to Page Buffer) can be completely avoided, and operations such as mapping queries and NAND access that must be executed serially in traditional solutions are converted into direct buffer access. For typical sequential read scenarios, this multi-level hit mechanism can cover longer data sequences, allowing more than 90% of read commands to skip the NAND access link, compressing the average latency from hundreds of microseconds to the memory / cache data transmission time level (about a few microseconds), achieving a step-by-step improvement in performance.

[0067] An embodiment of the present invention proposes a multi-layer pre-reading method for SSDs, comprising: determining whether a preset pre-reading condition is triggered; if the preset pre-reading condition is triggered, loading data into a multi-layer pre-reading buffer of a solid-state drive, wherein the multi-layer pre-reading buffer includes an SSD on-chip memory, a NAND Cache Buffer, and a NAND Page Buffer; if a read command is received, determining whether the read command hits the multi-layer pre-reading buffer; if the read command hits the multi-layer pre-reading buffer, reading the target data corresponding to the read command from the multi-layer pre-reading buffer. By constructing a multi-layer pre-reading buffer comprising an SSD on-chip memory, a NAND Cache Buffer, and a NAND Page Buffer, data is loaded in layers when the pre-reading condition is triggered, so that the target data is directly obtained from the buffer when the read command hits. This solution breaks through the memory capacity limitations of consumer-grade SSDs: it reuses NAND's inherent cache resources, expands the pre-reading data capacity several times without adding additional hardware costs; when a hit occurs, it completely avoids the physical read delay of the NAND array (especially the time-consuming Cell data transmission stage), and converts traditional serial operations into direct buffer reads. For sequential read scenarios, multi-level buffering allows most read commands to skip the NAND access link, compressing the average latency from hundreds of microseconds to microseconds of transmission time, achieving a step-by-step performance improvement.

[0068] In some preferred embodiments, after reading the target data corresponding to the read command from the multi-layer pre-read buffer, the method further includes: deleting the target data from the multi-layer pre-read buffer; and loading data into the multi-layer pre-read buffer for storage.

[0069] In practice, a dynamic refresh mechanism immediately deletes target data after reading it and adds new data, creating a self-sustaining pre-read pipeline. The delete operation frees up buffer space for consumed data (especially critical in SSDs with only a few MB of on-chip memory), while subsequent data loading keeps the buffer full.

[0070] This instant update strategy offers two key advantages: First, it eliminates the "hole" problem of traditional read-ahead—where consumed data occupies buffer space, preventing new data from being loaded. This solution effectively utilizes the buffer through a delete-and-replenish closed loop. Second, it enables adaptive expansion of the read-ahead depth. As the host continues to read sequentially, new data is continuously loaded at the end of the buffer, forming a sliding window that follows the host's access position. For example, as the host reads from LBA 1000 to LBA 2000, the read-ahead window is synchronously updated from [1000-1500] to [1500-2500], expanding the acceleration coverage to twice the original design depth. This dynamic fluidity is key to overcoming the limitations of fixed read-ahead depth.

[0071] In some preferred embodiments, the method further includes: if a write command is received, determining whether the write command hits the multi-layer pre-read buffer; if the write command hits the multi-layer pre-read buffer, marking the data hit by the write command as invalid in the multi-layer pre-read buffer.

[0072] In practice, the mechanism of immediately invalidating data when a write command hits the read-ahead buffer is the most cost-effective solution for maintaining data consistency. When the host writes new data overwriting the old version in the read-ahead buffer, the invalidation operation marks the data as unavailable through software, ensuring that subsequent read commands will not return the invalidated old (dirty) data. Furthermore, the data can be deleted.

[0073] Corresponding to the above-mentioned SSD multi-layer pre-reading method, the present invention further provides an SSD multi-layer pre-reading device. The SSD multi-layer pre-reading device includes a unit for executing the above-mentioned SSD multi-layer pre-reading method. The SSD multi-layer pre-reading device can be configured in a terminal device such as a desktop computer, tablet computer, or laptop computer. Specifically, the SSD multi-layer pre-reading device includes:

[0074] A first judging unit, configured to judge whether a preset pre-reading condition is triggered;

[0075] A loading unit, configured to load data into a multi-layer pre-read buffer of the solid-state drive when a preset pre-read condition is triggered, wherein the multi-layer pre-read buffer includes an SSD on-chip memory, a NAND cache buffer, and a NAND page buffer;

[0076] a second determining unit, configured to determine, upon receiving a read command, whether the read command hits the multi-layer pre-read buffer;

[0077] The reading unit is configured to read target data corresponding to the read command from the multi-layer pre-read buffer if the read command hits the multi-layer pre-read buffer.

[0078] In some preferred embodiments, the determining whether a preset pre-reading condition is triggered includes:

[0079] Determine whether the logical addresses of the read commands sent by the host are continuous;

[0080] If the logical addresses of the read commands issued by the host are continuous, determine whether the cumulative amount of data sequentially read by the host is greater than a preset data amount threshold;

[0081] If the cumulative value of the amount of data sequentially read by the host is greater than a preset threshold, it is determined that a preset pre-read condition is triggered.

[0082] In some preferred embodiments, loading data into a multi-layer pre-read buffer of a solid-state drive includes:

[0083] Based on the preset pre-read depth, the data is loaded and stored in the SSD on-chip memory, the NAND Cache Buffer and the NAND Page Buffer in sequence according to the logical address order read sequentially by the host.

[0084] In some preferred embodiments, determining whether the read command hits the multi-layer pre-read buffer includes:

[0085] The multi-layer pre-read buffers are sequentially checked in the order of the SSD on-chip memory → the NAND Cache Buffer → the NAND Page Buffer to see whether the target data requested by the read command exists.

[0086] In some preferred embodiments, the SSD multi-layer pre-reading device further includes:

[0087] a deleting unit, configured to delete the target data from the multi-layer pre-read buffer;

[0088] The storage unit is used to load data and store it in the multi-layer pre-read buffer.

[0089] In some preferred embodiments, the SSD multi-layer pre-reading device further includes:

[0090] a third determining unit, configured to determine, upon receiving a write command, whether the write command hits the multi-layer pre-read buffer;

[0091] The invalidation unit is configured to mark the data hit by the write command as invalid in the multi-layer pre-read buffer if the write command hits the multi-layer pre-read buffer.

[0092] The above-mentioned SSD multi-layer pre-reading device can be implemented in the form of a computer program. The computer program can be used in Figure 2 Runs on the computer device shown.

[0093] See also Figure 2 , Figure 2 This is a schematic block diagram of a computer device provided in an embodiment of the present application. The computer device 500 can be a terminal device or a server. The terminal can be a smart phone, tablet computer, laptop computer, desktop computer, personal digital assistant, wearable device, or other electronic device with communication capabilities. The server can be a standalone server or a server cluster consisting of multiple servers.

[0094] The computer device 500 includes a processor 502 , a memory, and a network interface 505 connected via a system bus 501 , wherein the memory may include a non-volatile storage medium 503 and an internal memory 504 .

[0095] The non-volatile storage medium 503 can store an operating system 5031 and a computer program 5032. When the computer program 5032 is executed, the processor 502 can execute an SSD multi-layer pre-reading method.

[0096] The processor 502 is used to provide computing and control capabilities to support the operation of the entire computer device 500.

[0097] The internal memory 504 is used to provide an environment for the operation of the computer program 5032 in the non-volatile storage medium 503. When the computer program 5032 is executed by the processor 502, the processor 502 can execute an SSD multi-layer pre-reading method.

[0098] The network interface 505 is used to communicate with other devices over the network. Those skilled in the art will appreciate that the above structure is merely a block diagram of a portion of the structure related to the present invention and does not limit the computer device 500 to which the present invention is applied. A specific computer device 500 may include more or fewer components than those shown in the figure, or combine certain components, or have a different component arrangement.

[0099] The processor 502 is configured to run a computer program 5032 stored in a memory to implement the steps of an SSD multi-layer pre-reading method provided by any embodiment of the present invention.

[0100] It should be understood that in the embodiment of the present application, the processor 502 may be a central processing unit (CPU), and the processor 502 may also be other general-purpose processors, digital signal processors (DSP), application-specific integrated circuits (ASIC), field-programmable gate arrays (FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. Among them, the general-purpose processor may be a microprocessor or the processor may also be any conventional processor, etc.

[0101] Those skilled in the art will appreciate that all or part of the steps in the method of the above-described embodiment can be implemented by instructing the relevant hardware through a computer program. The computer program can be stored in a computer-readable storage medium. The computer program is executed by at least one processor in the computer system to implement the steps in the method of the above-described embodiment.

[0102] Therefore, the present invention further provides a storage medium. The storage medium may be a computer-readable storage medium. The storage medium stores a computer program. When executed by a processor, the computer program causes the processor to perform the steps of an SSD multi-layer pre-reading method provided in any embodiment of the present invention.

[0103] The storage medium is a physical, non-transient storage medium, such as a USB flash drive, a mobile hard drive, a read-only memory (ROM), a magnetic disk, or an optical disk, etc. Any physical storage medium capable of storing program code can be non-volatile or volatile.

[0104] Those skilled in the art will appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of the two. In order to clearly illustrate the interchangeability of hardware and software, the above description has generally described the composition and steps of each example according to function. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of the present invention.

[0105] In the several embodiments provided herein, it should be understood that the disclosed devices and methods can be implemented in other ways. For example, the device embodiments described above are merely illustrative. For example, the division of the various units is merely a logical functional division, and actual implementation may employ other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be omitted or not implemented.

[0106] The steps in the methods of the embodiments of the present invention may be adjusted in order, combined, or deleted as needed. The units in the devices of the embodiments of the present invention may be combined, divided, or deleted as needed. Furthermore, the functional units in the various embodiments of the present invention may be integrated into a single processing unit, each unit may exist physically separately, or two or more units may be integrated into a single unit.

[0107] If this integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a storage medium. Based on this understanding, the technical solution of the present invention, or the part that contributes to the existing technology, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes a number of instructions for causing a computer device (which can be a personal computer, terminal, or network device, etc.) to execute all or part of the steps of the method described in various embodiments of the present invention.

[0108] In the above embodiments, the description of each embodiment has its own focus. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0109] Obviously, those skilled in the art may make various changes and modifications to the present invention without departing from the spirit and scope of the present invention. Thus, to the extent such changes and modifications fall within the scope of the claims and their equivalents, the present invention is intended to encompass such changes and modifications.

[0110] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any person skilled in the art can easily conceive of various equivalent modifications or substitutions within the technical scope disclosed in the present invention, and such modifications or substitutions are intended to be within the scope of protection of the present invention. Therefore, the scope of protection of the present invention shall be subject to the scope of protection of the claims.

Claims

1. A multi-layer pre-reading method for SSD, characterized in that: include: Determine whether the preset pre-reading condition is triggered; If a preset pre-read condition is triggered, the data is loaded into the multi-layer pre-read buffer of the solid-state drive, which includes the SSD on-chip memory, NAND Cache Buffer, and NAND Page Buffer; If a read command is received, determining whether the read command hits the multi-layer pre-read buffer; If the read command hits the multi-layer pre-read buffer, target data corresponding to the read command is read from the multi-layer pre-read buffer.

2. The SSD multi-layer pre-reading method according to claim 1, characterized in that: The determining whether a preset pre-reading condition is triggered includes: Determine whether the logical addresses of the read commands sent by the host are continuous; If the logical addresses of the read commands issued by the host are continuous, determine whether the cumulative amount of data sequentially read by the host is greater than a preset data amount threshold; If the cumulative value of the amount of data sequentially read by the host is greater than a preset threshold, it is determined that a preset pre-read condition is triggered.

3. The SSD multi-layer pre-reading method according to claim 2, characterized in that: The step of loading data into the multi-layer pre-read buffer of the solid state drive includes: Based on the preset pre-read depth, the data is loaded and stored in the SSD on-chip memory, the NAND Cache Buffer and the NAND Page Buffer in sequence according to the logical address order read sequentially by the host.

4. The SSD multi-layer pre-reading method according to claim 3, characterized in that: The determining whether the read command hits the multi-layer pre-read buffer includes: The multi-layer pre-read buffers are sequentially checked in the order of the SSD on-chip memory → the NAND Cache Buffer → the NAND Page Buffer to see whether the target data requested by the read command exists.

5. The SSD multi-layer pre-reading method according to claim 1, characterized in that: After reading the target data corresponding to the read command from the multi-layer pre-read buffer, the method further includes: The target data is deleted from the multi-layer pre-read buffer.

6. The SSD multi-layer pre-reading method according to claim 5, characterized in that: After deleting the target data from the multi-layer pre-read buffer, the method further includes: The loaded data is stored in the multi-layer read-ahead buffer.

7. The SSD multi-layer pre-reading method according to claim 1, characterized in that: The method further comprises: If a write command is received, determining whether the write command hits the multi-layer pre-read buffer; If the write command hits the multi-layer read-ahead buffer, the data hit by the write command is marked as invalid in the multi-layer read-ahead buffer.

8. An SSD multi-layer pre-reading device, characterized in that: The method comprises means for performing the method according to any one of claims 1 to 7.

9. A computer device, characterized in that: The computer device includes a memory and a processor, the memory stores a computer program, and the processor implements the method according to any one of claims 1 to 7 when executing the computer program.

10. A computer-readable storage medium, characterized in that The storage medium stores a computer program, and when the computer program is executed by a processor, the computer program can implement the method according to any one of claims 1 to 7.

Images