P-type GaN field effect transistor based on multichannel two-dimensional hole gas and preparation method thereof

Abstract

The invention discloses a p-type GaN field effect transistor based on multichannel two-dimensional hole gas and a preparation method of the p-type GaN field effect transistor. The field effect transistor comprises a substrate, a buffer layer and a channel layer, wherein the buffer layer and the channel layer are sequentially arranged on one side of the substrate in a stacked mode. The plurality of channel sub-layers comprise a p-GaN layer, a p-Inx1Ga (1-x1N) layer, a p-Inx2Ga (1-x2N) layer,..., a p-InxnGa (1-xnN) layer which are sequentially stacked on one side, far away from the substrate, of the buffer layer, and the thickness of the channel sub-layers is 10-500 nm; wherein x1, x2,..., xn are component proportions of the indium element in each channel sub-layer, and n is a positive integer greater than or equal to 2; and x < 1lt > is greater than or equal to 0.05. X2lt; x2lt; ... xn < = 1. According to the field effect transistor, through controlling the indium component gradient of each channel sub-layer, remarkable spontaneous polarization charges and piezoelectric polarization charges are generated at the heterojunction interface, so that high-density two-dimensional hole gas is induced to be generated, and the current density of the field effect transistor is improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a p-type GaN field effect transistor based on multi-channel two-dimensional hole gas and a preparation method thereof. Background Art

[0002] Gallium nitride (GaN)-based high electron mobility transistors (HEMTs) have become core devices in the field of power electronics due to their wide bandgap and high breakdown field strength. However, the development of p-type GaN devices lags far behind that of n-type HEMTs, mainly due to the low doping efficiency of magnesium (Mg) acceptor impurities, low hole mobility, and low hole carrier concentration. Currently, enhancement-mode (E-mode) GaN p-type GaN field-effect transistors (p-FETs) face core challenges in complementary logic circuits: low hole carrier mobility, low current density (usually less than 10mA / mm), and low on-resistance R on higher, and the threshold voltage V th It is difficult to precisely control. These problems severely limit the application of p-type GaN field-effect transistors in high-voltage, high-frequency, and high-power integrated circuits. In the prior art, although p-FETs based on p-GaN / AlGaN / GaN heterostructures can form 2DHG (two-dimensional hole gas), the 2DHG density depends on the diffused Mg doping concentration. Due to the high activation energy of the acceptor, the hole concentration is low and unevenly distributed, and the hole mobility and density cannot be effectively improved. In addition, the existing E-mode p-FET achieves threshold control through gate etching or surface dielectric layer design, but is limited by the channel quality, and the maximum current density I DSMax The on-resistance is generally low and the current density is still not ideal.

[0003] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present invention, and therefore may include information that does not constitute prior art known to ordinary technicians in this field. Summary of the Invention

[0004] In order to solve the above problems existing in the prior art, the present invention provides a p-type GaN field-effect transistor based on a multi-channel two-dimensional hole gas and a method for preparing the same. The technical problem to be solved by the present invention is achieved through the following technical solutions:

[0005] In a first aspect, the present invention provides a p-type GaN field-effect transistor based on a multi-channel two-dimensional hole gas, comprising a substrate, and a buffer layer and a channel layer stacked in sequence on one side of the substrate; the channel layer comprises a plurality of channel sublayers, each of the channel sublayers having a thickness of 10-500 nm;

[0006] The plurality of channel sublayers include a p-GaN layer, a p-In layer, and a buffer layer located on a side away from the substrate. x1 Ga 1-x1 N-layer, p-In x2 Ga 1-x2 N layers, ..., p-In xn Ga 1-xn N layers; where x1, x2, ..., xn are the composition ratios of indium elements in each channel sublayer, and n is a positive integer greater than or equal to 2; and 0.05≤x1 <x2<…xn≤1。

[0007] In one embodiment of the present invention, the channel layer includes a p-GaN layer, a p-In x1 Ga 1-x1 N-layer and p-In x2 Ga 1-x2 N layers.

[0008] In one embodiment of the present invention, the channel layer has a groove gate on a side away from the substrate, and the groove gate includes a gate dielectric and a gate metal stacked in sequence;

[0009] The groove depth of the groove gate is smaller than the thickness of the channel layer.

[0010] In one embodiment of the present invention, a source electrode and a drain electrode are provided on a side of the channel layer away from the substrate, and the source electrode and the drain electrode are in ohmic contact with any channel sub-layer.

[0011] In a second aspect, the present invention provides a method for preparing the above-mentioned p-type GaN field-effect transistor based on multi-channel two-dimensional hole gas, comprising the following steps:

[0012] S10, obtaining a substrate;

[0013] growing a buffer layer on one side of the substrate by using a molecular beam epitaxy method or a metal organic chemical vapor deposition method;

[0014] S20, forming a channel layer on a side of the buffer layer away from the substrate by molecular beam epitaxy or metal organic chemical vapor deposition, wherein the channel layer includes a plurality of channel sublayers, and the thickness of each channel sublayer is 10-500 nm;

[0015] The channel layer is formed by sequentially forming a stacked p-GaN layer, a p-In layer, and a x1 Ga 1-x1 N-layer, p-In x2 Ga 1- x2 N layers, ..., p-In xn Ga 1-xnN layers; where x1, x2, ..., xn are the composition ratios of indium elements in each channel sublayer, and n is a positive integer greater than or equal to 2; and 0.05≤x1 <x2<…xn≤1;

[0016] S30, using an inductively coupled plasma etching technique to respectively etch a gate groove, a source groove, and a drain groove on a side of the channel layer away from the substrate, wherein the depths of the gate groove, the source groove, and the drain groove are all less than the thickness of the channel layer;

[0017] A gate dielectric is formed in the gate groove by using a plasma enhanced chemical vapor deposition process;

[0018] S40. Using an electron beam evaporation process, a gate metal is formed on the surface of the gate dielectric; using an electron beam evaporation process, a source and a drain are formed in the source groove and the drain groove, so that the source and the drain achieve ohmic contact with any channel sub-layer to obtain a p-type GaN field effect transistor.

[0019] In a third aspect, the present invention provides a p-type GaN field-effect transistor based on a multi-channel two-dimensional hole gas, comprising a substrate, and a buffer layer and a channel layer sequentially stacked on one side of the substrate;

[0020] The channel layer includes a plurality of channel sublayers, and the thickness of each of the channel sublayers is 10-500 nm;

[0021] The plurality of channel sublayers include a p-GaN layer, a p-Al layer, and a buffer layer located on a side away from the substrate. y1 In z1 Ga 1-y1-z1 N layer, p-Al y2 In z2 Ga 1-y2-z2 N layer,…,p-Al ym In zm Ga 1-ym-zm N layer; where y1, y2, ..., ym are the composition ratios of aluminum elements in each channel sublayer, and z1, z2, ..., zm are the composition ratios of indium elements in each channel sublayer, satisfying 0.05≤z1 <z2<…zm≤1,1≥y1>y2>…ym≥0.05。

[0022] In one embodiment of the present invention, the channel layer includes a p-GaN layer, a p-Al y1 In z1 Ga 1-y1-z1 N layer and p-Al y2 In z2 Ga 1-y2-z2 N layers.

[0023] In one embodiment of the present invention, the channel layer has a groove gate on a side away from the substrate, and the groove gate includes a gate dielectric and a gate metal stacked in sequence;

[0024] The groove depth of the groove gate is smaller than the thickness of the channel layer.

[0025] In one embodiment of the present invention, a source electrode and a drain electrode are provided on a side of the channel layer away from the substrate, and the source electrode and the drain electrode are in ohmic contact with any channel sub-layer.

[0026] In a fourth aspect, the present invention provides a method for preparing the above-mentioned p-type GaN field-effect transistor based on multi-channel two-dimensional hole gas, comprising the following steps:

[0027] S10, obtaining a substrate;

[0028] growing a buffer layer on one side of the substrate by using a molecular beam epitaxy method or a metal organic chemical vapor deposition method;

[0029] S20, forming a channel layer on a side of the buffer layer away from the substrate by molecular beam epitaxy or metal organic chemical vapor deposition, wherein the channel layer includes a plurality of channel sublayers, and the thickness of each channel sublayer is 10-500 nm;

[0030] The channel layer is formed by sequentially forming a stacked p-GaN layer, a p-Al y1 In z1 Ga 1-y1-z1 N layer, p-Al y2 In z2 Ga 1-y2-z2 N layer,…,p-Al ym In zm Ga 1-ym-zm N layer; where y1, y2, ..., ym are the composition ratios of aluminum elements in each channel sublayer, and z1, z2, ..., zm are the composition ratios of indium elements in each channel sublayer, satisfying 0.05≤z1 <z2<…zm≤1,1≥y1>y2>…ym≥0.05;

[0031] S30, using inductively coupled plasma etching technology to etch a gate groove, a source groove, and a drain groove on a side of the channel layer away from the substrate;

[0032] A gate dielectric is formed in the gate groove by a plasma enhanced chemical vapor deposition process, wherein the depths of the gate groove, the source groove and the drain groove are all less than the thickness of the channel layer;

[0033] S40. Using an electron beam evaporation process, a gate metal is formed on the surface of the gate dielectric; using an electron beam evaporation process, a source and a drain are formed in the source groove and the drain groove, so that the source and the drain achieve ohmic contact with any channel sub-layer to obtain a p-type GaN field effect transistor.

[0034] Compared with the prior art, the present invention has the following beneficial effects:

[0035] 1. The p-type GaN field-effect transistor provided by the present invention is provided with at least three channel sublayers, and the indium content of each channel sublayer increases and / or the aluminum content decreases from the side close to the buffer layer to the side away from the buffer layer. By utilizing the difference in indium content and / or aluminum content between two adjacent channel sublayers, significant spontaneous polarization charge and piezoelectric polarization charge are generated at the heterojunction interface between any two adjacent channel sublayers due to the polarization effect, thereby inducing the generation of high-density two-dimensional hole gas (2DHG) at multiple interfaces, generating multiple 2DHG channels, thereby effectively reducing the on-resistance of the p-type GaN field-effect transistor and breaking through the carrier limitation of the traditional single heterojunction.

[0036] 2. The p-type GaN field-effect transistor provided by the present invention utilizes the interlayer polarization difference of different In components to form a superimposed polarization electric field, thereby improving the spatial distribution uniformity of the two-dimensional hole gas.

[0037] 3. The gradient design of the indium content and / or aluminum content in each channel sublayer alleviates the stress problem caused by lattice mismatch, thereby improving the material epitaxial quality and the reliability of p-type GaN field-effect transistor devices.

[0038] 4. By adjusting the etch depth of the gate groove in the channel layer, thereby affecting the degree of band bending at the gate dielectric / semiconductor interface, the concentration of the two-dimensional hole gas between adjacent channel sublayers will also vary, allowing the threshold voltage of the p-type GaN field-effect transistor to be adjusted. Therefore, the field-effect transistor provided by the present invention can achieve a high current density while achieving threshold voltage adjustability, without affecting the application of p-type GaN field-effect transistors in different scenarios.

[0039] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention.

[0040] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] The accompanying drawings are incorporated into and constitute a part of this specification, illustrate embodiments consistent with the present invention, and together with the description, serve to explain the principles of the present invention. Obviously, the drawings described below are only some embodiments of the present invention, and it is clear that those skilled in the art can derive other drawings based on these drawings without inventive effort.

[0042] Figure 1 A schematic cross-sectional view of a p-type GaN field-effect transistor based on a multi-channel two-dimensional hole gas in one embodiment of the present invention;

[0043] Figure 2 A schematic cross-sectional view of a p-type GaN field-effect transistor based on a multi-channel two-dimensional hole gas in one embodiment of the present invention;

[0044] Figure 3 A schematic cross-sectional view of a p-type GaN field-effect transistor based on a multi-channel two-dimensional hole gas in one embodiment of the present invention;

[0045] Figure 4 This is a cross-sectional schematic diagram corresponding to the preparation process S10 of a p-type GaN field effect transistor based on a multi-channel two-dimensional hole gas in one embodiment of the present invention;

[0046] Figure 5 A cross-sectional schematic diagram corresponding to the preparation process S20 of a p-type GaN field effect transistor based on a multi-channel two-dimensional hole gas in one embodiment of the present invention;

[0047] Figure 6 A cross-sectional schematic diagram corresponding to step S30 of fabricating a p-type GaN field-effect transistor based on a multi-channel two-dimensional hole gas in one embodiment of the present invention;

[0048] Figure 7 A schematic cross-sectional view of a p-type GaN field-effect transistor based on a multi-channel two-dimensional hole gas in one embodiment of the present invention;

[0049] Figure 8 A schematic cross-sectional view of a p-type GaN field-effect transistor based on a multi-channel two-dimensional hole gas in one embodiment of the present invention;

[0050] Figure 9 Schematic cross-sectional view of a p-type GaN field-effect transistor based on multi-channel two-dimensional hole gas in one embodiment of the present invention.

[0051] The reference numerals are as follows:

[0052] SBT-substrate, BF-buffer layer, CL-channel layer, SE-source, DE-drain, GI-gate dielectric, GE-gate metal. DETAILED DESCRIPTION

[0053] Example embodiments will now be described more fully with reference to the accompanying drawings. However, the example embodiments can be implemented in many forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete and will fully convey the concepts of the example embodiments to those skilled in the art. Like reference numerals in the figures represent identical or similar structures, and thus their detailed description will be omitted. Furthermore, the figures are merely schematic illustrations of the present invention and are not necessarily drawn to scale.

[0054] The terms "a", "an", "the" and "said" are used to indicate the presence of one or more elements / components / etc.; the terms "including" and "having" are used to express open-ended inclusion and mean that additional elements / components / etc. may exist in addition to the listed elements / components / etc.; the terms "first", "second", etc. are used only as labels and do not limit the quantity of their objects.

[0055] In the prior art, the polarization effect of the p-GaN / AlGaN heterojunction is underutilized, resulting in limited interface polarization charge, making it difficult to form a high-density 2DHG and achieving sufficient carrier concentration and current density. To address this issue, embodiments of the present invention provide a p-type GaN field-effect transistor based on a multi-channel two-dimensional hole gas.

[0056] In the first aspect, an embodiment of the present invention provides a p-type GaN field effect transistor based on a multi-channel two-dimensional hole gas, the field effect transistor comprising a substrate SBT, and a buffer layer BF and a channel layer CL stacked in sequence on one side of the substrate SBT; the channel layer CL comprises a plurality of channel sublayers, each of which has a thickness of 10-500nm; the plurality of channel sublayers comprises a p-GaN layer, a p-In layer, and a p-GaN layer stacked in sequence on the side of the buffer layer BF away from the substrate SBT. x1 Ga 1-x1 N-layer, p-In x2 Ga 1-x2 N layers, ..., p-In xn Ga 1-xn N layers; where x1, x2, ..., xn are the composition ratios of indium elements in each channel sublayer, and n is a positive integer greater than or equal to 2; and 0.05≤x1 <x2<…xn≤1。

[0057] The p-type GaN field effect transistor provided in this embodiment is provided with at least three channel sublayers, and, in any two adjacent channel sublayers, the mass content of indium in the channel sublayer away from the side of the substrate substrate SBT is greater than the mass content of indium in the channel sublayer close to the side of the substrate substrate SBT. In this way, by utilizing the difference in indium content between the two adjacent channel sublayers, the heterojunction interface between any two adjacent channel sublayers generates significant spontaneous polarization charge and piezoelectric polarization charge due to the polarization effect, thereby inducing the generation of high-density two-dimensional hole gas (2DHG) at the interface, generating multiple 2DHG channels, thereby effectively reducing the on-resistance of the p-type GaN field effect transistor. In addition, the gradient design of the indium content in each channel sublayer alleviates the stress problem caused by lattice mismatch, and further improves the material epitaxial quality and the reliability of the p-type GaN field effect transistor device.

[0058] In one embodiment of the present invention, n=2. That is, the channel layer CL of the p-type GaN field effect transistor includes a p-GaN layer, a p-In x1 Ga 1-x1 N-layer and p-In x2 Ga 1-x2 N layers.

[0059] In one example, the channel layer includes a p-GaN layer, a p-In 0.1 Ga 0.9 N-layer and p-In 0.8 Ga 0.2 N layers.

[0060] In one embodiment of the present invention, the channel layer has a groove gate on the side away from the substrate SBT, and the groove gate includes a gate dielectric GI and a gate metal GE stacked in sequence; the groove depth of the groove gate is less than the thickness of the channel layer. For the convenience of description, the groove of the groove gate is defined as a gate groove. That is, the gate groove can be formed between the p-GaN layer and the p-In layer. xn Ga 1-xn Any thickness position between the N layers. In this way, the threshold voltage can be adjusted by adjusting the depth of the groove.

[0061] For example, Figure 1 As shown, the gate groove is set in the p-In xn Ga 1-xn N layer, can be adjusted by adjusting the gate groove in the p-In xn Ga 1-xn The etching depth of the N layer makes the gate correspond to the p-In layer in the stacked area. xn Ga 1-xn The thickness of the N layer changes, which in turn affects the band bending degree of the gate dielectric / semiconductor interface. xn Ga1-xn N layer and p-In x(n-1) Ga 1-x(n-1) The concentration of the two-dimensional hole gas between the N layers also varies, making the threshold voltage of the p-type GaN field-effect transistor adjustable. This allows the field-effect transistor to achieve high current density and adjustable threshold voltage, without affecting the application of the p-type GaN field-effect transistor in different scenarios.

[0062] In another example, the bottom of the gate groove is set at the p-GaN layer to the p-In layer. x(n-1) Ga 1-x(n-1) N layers. For example, Figure 2 As shown, the bottom of the gate groove is set at p-In x1 Ga 1-x1 N layer. That is, the gate groove makes the p-In x1 Ga 1-x1 N layer to p-In xn Ga 1-xn In the N layer, the 2DHG channel between the two adjacent channel sublayers is cut off, which can only control the p-GaN layer and the p-In x1 Ga 1-x1 The 2DHG channel is generated between the N layers, but due to the p-In x1 Ga 1-x1 N layer to p-In xn Ga 1-xn The gradient change of indium content in the two adjacent layers in the N layer makes the p-GaN layer and the p-In layer x1 Ga 1-x1 The polarization effect of the N layer increases, and the p-GaN layer and p-In x1 Ga 1-x1 The 2DHG concentration at the N-layer interface increases, thereby increasing the current density. At the same time, the gate groove can be adjusted to x1 Ga 1-x1 The depth of the N layer adjusts the threshold voltage of the p-type GaN field-effect transistor.

[0063] In one embodiment of the present invention, a source and a drain are provided on the side of the channel layer away from the substrate SBT, and the source and the drain are in ohmic contact with any channel sub-layer. Figure 1 and Figure 3 As shown, the depths of the source groove and the drain groove etched during the preparation process can be adjusted according to the actual application scenario to obtain a good low-ohmic contact.

[0064] The embodiment of the present invention further provides a method for preparing the above-mentioned p-type GaN field effect transistor based on multi-channel two-dimensional hole gas, which comprises the following steps:

[0065] S10, such as Figure 4 As shown, a substrate SBT is obtained; a buffer layer BF is grown on one side of the substrate SBT by using a molecular beam epitaxy method or a metal organic chemical vapor deposition method.

[0066] Exemplarily, the buffer layer BF has a thickness of 200 nm to 5000 nm and is not intentionally doped with GaN.

[0067] S20, such as Figure 5 As shown, a molecular beam epitaxy method or a metal organic chemical vapor deposition method is used to form a channel layer on the side of the buffer layer BF away from the substrate SBT, and the channel layer includes a plurality of channel sublayers, and the thickness of each channel sublayer is 10-500nm; the formation of the channel layer includes: sequentially forming a stacked p-GaN layer, a p-In x1 Ga 1-x1 N-layer, p-In x1 Ga 1-x1 N layers, ..., p-In xn Ga 1-xn N layers; where x1, x2, ..., xn are the composition ratios of indium elements in each channel sublayer, and n is a positive integer greater than or equal to 2; and 0.05≤x1 <x2<…xn≤1。

[0068] For example, taking the formation of three channel sublayers as an example, the channel layers respectively include a p-GaN layer with a thickness of 10nm to 500nm; a p-In layer with a thickness of 10nm to 500nm; x1 Ga 1-x1 N layer; p-In with a thickness of 10nm to 500nm x1 Ga 1-x1 N layers.

[0069] S30, such as Figure 6 As shown, an inductively coupled plasma (ICP) etching technology is used to etch a gate groove, a source groove, and a drain groove on the side of the channel layer away from the substrate SBT, respectively. The depths of the gate groove, the source groove, and the drain groove are all less than the thickness of the channel layer. A plasma enhanced chemical vapor deposition process is used to form a gate dielectric GI in the gate groove. In step S30, the inductively coupled plasma etching technology uses low power, which can reduce etching damage, obtain a low-damage etching interface, and reduce the interface defect density.

[0070] Exemplarily, the gate dielectric GI may be Si3N4, SiO2, Al2O3 or HfO dielectric, with a thickness of 10-200 nm.

[0071] S40. Using an electron beam evaporation process, a gate metal GE is formed on the surface of the gate dielectric GI of the gate; using an electron beam evaporation process, a source and a drain are formed in the source groove and the drain groove, so that the source and the drain achieve ohmic contact with any channel sub-layer to obtain a p-type GaN field effect transistor.

[0072] Exemplarily, forming the gate metal GE includes sequentially depositing a Ti / Al / Ti or TiN metal stack as the gate metal. Forming the source and drain includes sequentially depositing a Ti / Al / Ni / Au metal stack or a Ti / Al / Ti / TiN metal stack as the ohmic source and drain metal.

[0073] Second, as Figure 7 As shown, the embodiment of the present invention also provides another p-type GaN field effect transistor based on multi-channel two-dimensional hole gas, the field effect transistor includes a substrate SBT, and a buffer layer BF and a channel layer stacked in sequence on one side of the substrate SBT; the channel layer includes a plurality of channel sublayers, each of which has a thickness of 10-500nm; the plurality of channel sublayers include a p-GaN layer, a p-Al layer, and a buffer layer BF. The buffer layer BF is located on a side away from the substrate SBT and is stacked in sequence. y1 In z1 Ga 1-y1-z1 N layer, p-Al y2 In z2 Ga 1-y2-z2 N layer,…,p-Al ym In zm Ga 1-ym-zm N layer; where y1, y2, ..., ym are the composition ratios of aluminum elements in each channel sublayer, and z1, z2, ..., zm are the composition ratios of indium elements in each channel sublayer, satisfying 0.05≤z1 <z2<…zm≤1,1≥y1>y2>…ym≥0.05。

[0074] The p-type GaN field effect transistor provided in this embodiment is provided with at least three channel sublayers, and, in any two adjacent channel sublayers, the mass content of indium in the channel sublayer away from the substrate substrate SBT side is greater than the mass content of indium in the channel sublayer close to the substrate substrate SBT side; in any two adjacent channel sublayers, the mass content of aluminum in the channel sublayer away from the substrate substrate SBT side is less than the mass content of aluminum in the channel sublayer close to the substrate substrate SBT side. In this way, on the one hand, by utilizing the difference in indium content between the two adjacent channel sublayers, significant spontaneous polarization charge and piezoelectric polarization charge are generated at the heterojunction interface between any two adjacent channel sublayers due to the polarization effect, thereby inducing the generation of high-density two-dimensional hole gas (2DHG) at the interface, generating multiple 2DHG channels, thereby effectively reducing the on-resistance of the p-type GaN field effect transistor. The gradient design of the indium content in each channel sublayer alleviates the stress problem caused by lattice mismatch, and further improves the material epitaxial quality and the reliability of the p-type GaN field effect transistor device. On the other hand, by utilizing the difference in aluminum content between two adjacent channel sublayers and reducing the aluminum content in the channel layer, the scattering probability and the effective mass of holes can be reduced, thereby improving the mobility. At the same time, the ratio of aluminum and indium is adjusted so that the lattice constant of AlInGaN can match that of GaN, reducing the dislocations and defects that may occur during epitaxial growth, and improving the epitaxial quality and device reliability.

[0075] In one embodiment of the present invention, m=2. That is, the channel layer of the p-type GaN field effect transistor includes a p-GaN layer, a p-Al y1 In z1 Ga 1-y1-z1 N layer and p-Al y2 In z2 Ga 1-y2-z2 N layers.

[0076] In one embodiment of the present invention, the channel layer has a groove gate on the side away from the substrate SBT, and the groove gate includes a gate dielectric GI and a gate metal GE stacked in sequence; the groove depth of the groove gate is less than the thickness of the channel layer.

[0077] For example, Figure 7 As shown, the gate groove is set in the p-Al ym In zm Ga 1-ym-zm N layer, can be adjusted by adjusting the gate groove in the p-Al ym In zm Ga 1-ym-zm The etching depth of the N layer makes the gate correspond to the p-Al stacking area ym In zm Ga 1-ym-zmThe thickness of the N layer changes, which in turn affects the band bending degree of the gate dielectric / semiconductor interface. ym In zm Ga 1-ym-zm N layer and p-Al y(m-1) In z(m-1) Ga 1-y(m-1)-z(m-1) The concentration of the two-dimensional hole gas between the N layers also varies, making the threshold voltage of the p-type GaN field-effect transistor adjustable. This allows the field-effect transistor to have a higher current density and an adjustable threshold voltage, without affecting the application of the p-type GaN field-effect transistor in different scenarios.

[0078] In another example, the bottom of the gate groove is set at the p-GaN layer to the p-Al layer. y(m-1) In z(m-1) Ga 1-y(m-1)-z(m-1) Any layer in the N layers. For example, Figure 8 As shown, the bottom of the gate groove is set on the p-Al y1 In z1 Ga 1-y1-z1 N layer. That is, the gate groove makes the p-Al y1 In z1 Ga 1-y1-z1 N layer to p-Al yn In zn Ga 1-yn-zn In the N layer, the 2DHG channel between the two adjacent channel sublayers is cut off, which can only control the p-GaN layer and the p-Al y1 In z1 Ga 1-y1-z1 The 2DHG channel generated between the N layers, however, due to the p-Al y1 In z1 Ga 1-y1-z1 N layer to p-Al ym In zm Ga 1-ym-zm The gradient change of indium content and aluminum content in the adjacent two layers in the N layer makes the p-GaN layer and the p-Al layer y1 In z1 Ga 1-y1-z1 The polarization effect of the N layer increases, and the p-GaN layer and the p-Al y1 In z1 Ga 1-y1-z1 The 2DHG concentration at the N layer interface increases, thereby increasing the current density. At the same time, the gate groove can be adjusted in the p-Al y1 In z1 Ga 1-y1-z1 The depth of the N layer adjusts the threshold voltage of the p-type GaN field-effect transistor.

[0079] In one embodiment of the present invention, the channel layer is provided with a source and a drain on the side away from the substrate SBT, and the source and the drain are in ohmic contact with any channel sub-layer. In other words, the source and the drain can be in contact with the p-Al ym In zm Ga 1-ym-zm N layer ohmic contact, or can be connected to p-Al y(m-1) In z(m-1) Ga 1-y(m-1)-z(m-1) N layer ohmic contact, or can be connected to p-Al y2 In z2 Ga 1-y2-z2 N layer p-Al y1 In z1 Ga 1-y1-z1 N layer ohmic contact, or can be connected to p-Al y1 In z1 Ga 1-y1- z1 N-layer ohmic contact, etc. Figure 7 As shown, the source SE and drain DE are both connected to the p-Al y(m-1) In z(m-1) Ga 1-y(m-1)-z(m-1) N layer ohmic contact, making p-Al y(m-1) In z(m-1) Ga 1-y(m-1)-z(m-1) N layer and p-Al ym In zm Ga 1-ym-zm The transmission path between the 2DHG channel between the N layer and the source SE and drain DE becomes shorter. Figure 9 As shown, the source electrode SE and the drain electrode DE are both in ohmic contact with the p-GaN layer, so that the p-GaN layer is in contact with the p-Al layer. y1 In z1 Ga 1-y1-z1 2DHG channel between N layers, p-Al y1 In z1 Ga 1-y1-z1 N layer and p-Al y2 In z2 Ga 1-y2-z2 2DHG channel between N layers, ..., p-Al y(m-1) In z(m-1) Ga 1-y(m-1)-z(m-1) N layer and p-Al ym In zm Ga 1-ym-zm The transmission paths between the 2DHG channel between the N layers and the source SE and drain DE are shortened.

[0080] The embodiment of the present invention further provides a method for preparing the above-mentioned p-type GaN field effect transistor based on multi-channel two-dimensional hole gas, comprising the following steps:

[0081] S10, obtaining a substrate SBT; and growing a buffer layer BF on one side of the substrate SBT by using a molecular beam epitaxy method or a metal organic chemical vapor deposition method.

[0082] Exemplarily, the buffer layer BF has a thickness of 200 nm to 5000 nm and is not intentionally doped with GaN.

[0083] S20, using molecular beam epitaxy or metal organic chemical vapor deposition to form a channel layer on the side of the buffer layer BF away from the substrate SBT, wherein the channel layer includes a plurality of channel sublayers, and the thickness of each channel sublayer is 10-500nm; the forming of the channel layer includes: sequentially forming a stacked p-GaN layer, a p-Al y1 In z1 Ga 1-y1-z1 N layer, p-Al y2 In z2 Ga 1-y2-z2 N layer,…,p-Al ym In zm Ga 1-ym-zm N layer; where y1, y2, ..., ym are the composition ratios of aluminum elements in each channel sublayer, and z1, z2, ..., zm are the composition ratios of indium elements in each channel sublayer, satisfying 0.05≤z1 <z2<…zm≤1,1≥y1>y2>…ym≥0.05。

[0084] For example, taking the formation of three channel sublayers as an example, the channel layers respectively include a p-GaN layer with a thickness of 10nm to 500nm; a p-Al layer with a thickness of 10nm to 500nm; y1 In z1 Ga 1-y1-z1 N layer; thickness is 10nm~500nm p-Al y1 In z1 Ga 1-y1-z1 N layers.

[0085] S30. Using inductively coupled plasma (ICP) etching technology, a gate groove, a source groove, and a drain groove are respectively etched on the side of the channel layer away from the substrate SBT; a plasma enhanced chemical vapor deposition (PECVD) deposition process is used to form a gate dielectric GI in the gate groove, and the depths of the gate groove, source groove, and drain groove are all less than the thickness of the channel layer.

[0086] For example, the gate dielectric GI may be Si3N4 or SiO 2,Al2O3, HfO and other dielectrics, with a thickness of 10-200nm.

[0087] S40. Using an electron beam evaporation process, a gate metal GE is formed on the surface of the gate dielectric GI; using an electron beam evaporation process, a source and a drain are formed in the source groove and the drain groove, so that the source and the drain achieve ohmic contact with any channel sub-layer to obtain a p-type GaN field effect transistor.

[0088] Exemplarily, the forming of the gate metal GE includes sequentially depositing a Ti / Al / Ti metal stack or depositing TiN. The forming of the source and drain includes sequentially depositing a Ti / Al / Ni / Au or Ti / Al / Ti / TiN metal stack as ohmic source and drain metals.

[0089] The above is a further detailed description of the present invention in conjunction with specific preferred embodiments, and the specific implementation of the present invention should not be considered to be limited to these descriptions. For those skilled in the art of the present invention, without departing from the concept of the present invention, several simple deductions or substitutions can be made, which should be considered to fall within the scope of protection of the present invention.

Claims

1. A p-type GaN field-effect transistor based on multi-channel two-dimensional hole gas, characterized in that: It includes a base substrate, and a buffer layer and a channel layer stacked in sequence on one side of the base substrate; The channel layer includes a plurality of channel sublayers, and the thickness of each of the channel sublayers is 10-500 nm; The plurality of channel sublayers include a p-GaN layer, a p-In layer, and a buffer layer located on a side away from the substrate. x1 Ga 1-x1 N-layer, p-In x2 Ga 1-x2 N layers, ..., p-In xn Ga 1-xn N layers; where x1, x2, ..., xn are the composition ratios of indium elements in each channel sublayer, and n is a positive integer greater than or equal to 2; and 0.05≤x1 <x2<…xn≤1。 2. The p-type GaN field effect transistor based on multi-channel two-dimensional hole gas according to claim 1, characterized in that: The channel layer includes a p-GaN layer, a p-In x1 Ga 1-x1 N-layer and p-In x2 Ga 1-x2 N layers.

3. The p-type GaN field effect transistor based on multi-channel two-dimensional hole gas according to claim 1 or 2, characterized in that: The channel layer has a groove gate on a side away from the substrate, and the groove gate includes a gate dielectric and a gate metal stacked in sequence; The groove depth of the groove gate is smaller than the thickness of the channel layer.

4. The p-type GaN field effect transistor based on multi-channel two-dimensional hole gas according to claim 3, characterized in that: A source electrode and a drain electrode are provided on the side of the channel layer away from the substrate, and the source electrode and the drain electrode realize ohmic contact with any channel sub-layer.

5. A method for preparing a p-type GaN field effect transistor based on multi-channel two-dimensional hole gas according to claim 4, characterized in that: The following steps are involved: S10, obtaining a substrate; growing a buffer layer on one side of the substrate by using a molecular beam epitaxy method or a metal organic chemical vapor deposition method; S20, forming a channel layer on a side of the buffer layer away from the substrate by molecular beam epitaxy or metal organic chemical vapor deposition, wherein the channel layer includes a plurality of channel sublayers, and the thickness of each channel sublayer is 10-500 nm; The channel layer is formed by sequentially forming a stacked p-GaN layer, a p-In layer, and a x1 Ga 1-x1 N-layer, p-In x2 Ga 1-x2 N layers, ..., p-In xn Ga 1-xn N layers; where x1, x2, ..., xn are the composition ratios of indium elements in each channel sublayer, and n is a positive integer greater than or equal to 2; and 0.05≤x1 <x2<…x n ≤1; S30, using an inductively coupled plasma etching technique to respectively etch a gate groove, a source groove, and a drain groove on a side of the channel layer away from the substrate, wherein the depths of the gate groove, the source groove, and the drain groove are all less than the thickness of the channel layer; A gate dielectric is formed in the gate groove by using a plasma enhanced chemical vapor deposition process; S40. Using an electron beam evaporation process, a gate metal is formed on the surface of the gate dielectric; using an electron beam evaporation process, a source and a drain are formed in the source groove and the drain groove, so that the source and the drain achieve ohmic contact with any channel sub-layer to obtain a p-type GaN field effect transistor.

6. A p-type GaN field-effect transistor based on multi-channel two-dimensional hole gas, characterized in that: It includes a base substrate, and a buffer layer and a channel layer stacked in sequence on one side of the base substrate; The channel layer includes a plurality of channel sublayers, and the thickness of each of the channel sublayers is 10-500 nm; The plurality of channel sublayers include a p-GaN layer, a p-Al layer, and a buffer layer located on a side away from the substrate. y1 In z1 Ga 1-y1-z1 N layer, p-Al y2 In z2 Ga 1-y2-z2 N layer,…,p-Al ym In zm Ga 1-ym-zm N layer; where y1, y2, ..., ym are the composition ratios of aluminum elements in each channel sublayer, and z1, z2, ..., zm are the composition ratios of indium elements in each channel sublayer, satisfying 0.05≤z1 <z2<…zm≤1,1≥y1>y2>…ym≥0.05。 7. The p-type GaN field effect transistor based on multi-channel two-dimensional hole gas according to claim 6, characterized in that: The channel layer includes a p-GaN layer, a p-Al y1 In z1 Ga 1-y1-z1 N layer and p-Al y2 In z2 Ga 1-y2-z2 N layers.

8. The p-type GaN field effect transistor based on multi-channel two-dimensional hole gas according to claim 6 or 7, characterized in that: The channel layer has a groove gate on a side away from the substrate, and the groove gate includes a gate dielectric and a gate metal stacked in sequence; The groove depth of the groove gate is smaller than the thickness of the channel layer.

9. The p-type GaN field effect transistor based on multi-channel two-dimensional hole gas according to claim 8, characterized in that: A source electrode and a drain electrode are provided on the side of the channel layer away from the substrate, and the source electrode and the drain electrode are in ohmic contact with any channel sub-layer.

10. A method for preparing a p-type GaN field effect transistor based on multi-channel two-dimensional hole gas according to claim 9, characterized in that: The following steps are involved: S10, obtaining a substrate; growing a buffer layer on one side of the substrate by using a molecular beam epitaxy method or a metal organic chemical vapor deposition method; S20, forming a channel layer on a side of the buffer layer away from the substrate by molecular beam epitaxy or metal organic chemical vapor deposition, wherein the channel layer includes a plurality of channel sublayers, and the thickness of each channel sublayer is 10-500 nm; The channel layer is formed by sequentially forming a stacked p-GaN layer, a p-Al y1 In z1 Ga 1-y1-z1 N layer, p-Al y2 In z2 Ga 1-y2-z2 N layer,…,p-Al ym In zm Ga 1-ym-zm N layer; where y1, y2, ..., ym are the composition ratios of aluminum elements in each channel sublayer, and z1, z2, ..., zm are the composition ratios of indium elements in each channel sublayer, satisfying 0.05≤z1 <z2<…zm≤1,1≥y1>y2>…ym≥0.05; S30, using inductively coupled plasma etching technology to etch a gate groove, a source groove, and a drain groove on a side of the channel layer away from the substrate; A gate dielectric is formed in the gate groove by a plasma enhanced chemical vapor deposition process, wherein the depths of the gate groove, the source groove and the drain groove are all less than the thickness of the channel layer; S40. Using an electron beam evaporation process, a gate metal is formed on the surface of the gate dielectric; using an electron beam evaporation process, a source and a drain are formed in the source groove and the drain groove, so that the source and the drain achieve ohmic contact with any channel sub-layer to obtain a p-type GaN field effect transistor.

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