Phase interpolator circuit

Abstract

The invention discloses a phase interpolator circuit, and belongs to the field of phase interpolator circuits. The phase interpolator circuit comprises a current source module, a control word decoding module, a phase interpolation module and a buffer output module, the current source module provides different currents for different units of the phase interpolation module, the control word decoding module converts an input control word into a corresponding control signal, the phase interpolation module allocates weight to an input four-phase clock according to the input control word to carry out phase interpolation and output, and the buffer output module recovers a voltage signal to a full swing. The digital resource overhead and the circuit area are remarkably reduced, and high linearity can be achieved through the designed control word decoding scheme and the current source proportion. The method is applied to a multi-channel high-speed sampling application scene with harsh area and resource overhead requirements.

Description

Technical Field

[0001] The present invention belongs to the field of circuit design, and more particularly, relates to a phase interpolator circuit. Background Art

[0002] In multi-channel high-speed sampling circuits, the relative position of the sampling clock and the data eye diagram significantly impacts the bit error rate (BER). Therefore, algorithms are required to adjust the sampling clock to achieve an optimal sampling clock, inevitably requiring adjustments to the clock-related circuitry. Furthermore, multi-channel circuit structures often impose certain requirements on the area and shape of the circuit layout, significantly limiting resource expenditure and area. A phase interpolator (PI) is a circuit structure commonly used to implement sampling clock adjustment. It can rotate the phase of the output clock relative to the input clock using an input control word, thus enabling integration with external digital modules to achieve an optimal sampling clock.

[0003] Conventional phase interpolation circuits achieve this by linearly modulating the weights of different clocks. While this approach simplifies layout, it introduces significant nonlinearity, and linearity deteriorates as the number of interpolated phases increases. Furthermore, additional digital storage circuits are often added to store the corresponding control signals to compensate for the inherent nonlinearity of the original circuit structure, but this approach significantly increases circuit resources and power consumption.

[0004] Therefore, the existing phase interpolation circuit has the problems of low linearity, high circuit resources and power consumption. Summary of the Invention

[0005] In view of the defects of the related art, the purpose of the present invention is to provide a phase interpolator circuit, aiming to solve the problems of low linearity, high circuit resources and power consumption in the existing phase interpolation circuit.

[0006] To achieve the above objectives, in a first aspect, the present invention provides a phase interpolator circuit, comprising: a current source module, a control word decoding module, a phase interpolation module, and a buffer output module;

[0007] The current source module is used to output 16 I currents and 16 Q currents to the phase interpolation module according to pre-configured weights;

[0008] The control word decoding module is used to decode the externally input 6-bit binary control word into a corresponding 64-bit control signal and output it to the phase interpolation module;

[0009] The phase interpolation module includes 16 units, each of which is divided into an I branch and a Q branch, and each unit includes four pairs of differential transistors. The phase interpolation module is used to turn on or off the differential transistors of the corresponding path according to the 64-bit control signal, redistribute the weights of the externally input four-phase clock signal, and adjust the current of each branch so that the total transconductance of the Q branch and the I branch respectively changes sinusoidally and cosinely with the increase of the externally input control word, thereby achieving phase interpolation and generating an output voltage.

[0010] The buffer output module is used to restore the output voltage to full swing and output it.

[0011] Optionally, the sine component and cosine component of the output voltage change in a sine manner and a cosine manner respectively corresponding to the 64-bit control signal, so that the phase of the output voltage is in a linear relationship with the 64-bit control signal.

[0012] Optionally, the IP phase, IN phase, QP phase, and QN phase corresponding to the four-phase clock in the four-phase clock signal differ by 90 degrees respectively.

[0013] Optionally, the 64-bit control signal generated by the control word decoding module is represented as {IP<0:15>, IN<0:15>, QP<0:15>, QN<0:15>}, which is respectively input into the phase interpolation module to control the opening or closing of the differential pair tubes of the corresponding path.

[0014] Optionally, the control word decoding module is further used to adjust the decoding logic according to the sinusoidal modulation relationship;

[0015] The decoding logic expression corresponding to the generated 64-bit control signal is:

[0016]

[0017] Among them, CTRL new is the i-th bit of the 64-bit control signal; when the control word changes from 16 to 32 and 48 to 64, the order in which the control signals are turned on in the I path and the Q path is reversed.

[0018] Optionally, the phase interpolation module further includes a common load resistor;

[0019] The common load resistor is used to add the currents of the branches in the units and convert them into output voltage.

[0020] Optionally, the buffer output module includes a DC blocking capacitor, a self-biased inverter, an inverter, and two latch-type inverters; the self-biased inverter is connected to the first latch-type inverter through the inverter, and the first latch-type inverter is connected to the second latch-type inverter through two consecutive inverters;

[0021] The DC blocking capacitor and the self-biased inverter are used to readjust the common mode voltage of the output voltage so that the phase interpolator circuit is in a normal working state;

[0022] The inverter inverts the input signal;

[0023] The latch-type inverter jumps at the zero-crossing position of the two inverted signals input, propagates the voltage signal of the output voltage backward, drives the corresponding circuit of the subsequent stage, and thus restores the output voltage to the full swing and outputs it.

[0024] Optionally, the current source module is further used to redistribute the tail current of each unit in the phase interpolation module to compensate for the nonlinear error of the phase interpolation module.

[0025] In a second aspect, the present invention further provides an integrated circuit comprising a phase interpolator circuit as described in any one of the first aspects.

[0026] Compared with the prior art, the above technical solutions conceived by the present invention can achieve the following beneficial effects:

[0027] The present invention provides a phase interpolator circuit that uses a control signal corresponding to an externally input 6-bit binary control word to adjust the weights of the four-phase clock signals of each unit in the phase interpolation module, thereby adjusting the proportion of each phase current. This achieves multi-segment linear approximate sinusoidal modulation of the current, compensating for the weighted sine and cosine variations that cannot be achieved with traditional schemes, effectively reducing nonlinear errors and improving the linearity of phase interpolation. This circuit only requires a small amount of digital logic, avoiding the use of memory circuits, effectively controlling digital resource and area expenditures, and is suitable for applications with stringent area and resource constraints.

[0028] 2. The phase interpolator circuit provided by the present invention achieves appropriate error compensation by adjusting the tail current ratio without increasing additional power consumption and resource expenditure, thereby effectively improving circuit linearity.

[0029] 3. The phase interpolator circuit provided by the present invention introduces a DC blocking capacitor at the input end of the buffer output module, thereby avoiding the adverse effects of the output common-mode voltage and effectively enhancing the robustness of the circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figure 1 This is the circuit diagram of the existing traditional phase interpolator;

[0031] Figure 2 Schematic diagram of interpolation error of existing traditional phase interpolator;

[0032] Figure 3 It is a nonlinear schematic diagram of the existing traditional phase interpolator;

[0033] Figure 4 An improved phase interpolator circuit diagram is provided;

[0034] Figure 5 A structural diagram of a phase interpolator circuit provided in an embodiment of the present invention;

[0035] Figure 6 A schematic diagram of a transconductance compensation solution provided by an embodiment of the present invention;

[0036] Figure 7 A schematic diagram of an improved control word according to an embodiment of the present invention;

[0037] Figure 8 An improved control word solution provided by an embodiment of the present invention;

[0038] Figure 9 A circuit diagram of a phase interpolation module provided in an embodiment of the present invention;

[0039] Figure 10 A circuit diagram of a buffer output module provided in an embodiment of the present invention;

[0040] Figure 11 Provides a schematic diagram of the common-mode voltage impact of PI according to an embodiment of the present invention;

[0041] Figure 12 Provides a linearity waveform measured by PI transient simulation for an embodiment of the present invention;

[0042] Figure 13 Provides linearity data measured by PI transient simulation for the embodiment of the present invention. DETAILED DESCRIPTION

[0043] In order to make the objectives, technical solutions and advantages of the present invention more clearly understood, the present invention is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely for the purpose of explaining the present invention and are not intended to limit the present invention. In addition, the technical features involved in the various embodiments of the present invention described below may be combined with each other as long as they do not conflict with each other.

[0044] The contents involved in the above embodiment are described below in conjunction with a preferred embodiment.

[0045] Figure 1 This is a traditional phase interpolator circuit diagram, which mainly consists of 16 PI units and a common load resistor. Each PI unit contains four differential pairs and a set of current sources. Each differential pair is turned on and off by the corresponding input signal, that is, 16 identical PI units weight the input four-phase clock, and the 64-bit control signal selects the open path, controls the signal weight of each branch, and converts the current of each path into an output voltage signal on the common load resistor. Briefly describe the working principle of the circuit: Assuming that the input signal is a sine wave, the differential output voltage of the circuit is V out :

[0046] V out =W I sinωt+W Q cosωt (1)

[0047] Among them, W I is the sinusoidal component of the output voltage signal, W Q is the cosine component of the output voltage signal. Therefore, the expression of the output phase can be further derived from formula (1):

[0048]

[0049] Therefore, if the weights of the sine and cosine signals, namely W I and W Q As the input control word CODE changes in sinusoidal and cosine modes respectively, a linear relationship between the output phase and the input control word CODE can be achieved.

[0050] W I The value of can be expressed as:

[0051] W I =R L G m A in ·K I =R L G m A in (Ctrl i -Ctrl in ) (3)

[0052] Assume that the input signal V in is an ideal sine, where K I G is the number of open I branches minus the number of open IN branches. m is the transconductance of a differential pair in each PI unit, R L is the load resistance, A in is the input signal amplitude.

[0053] To achieve phase interpolation, a relatively simple control word solution can be used, and the initial value of the input control signal is set to:

[0054] CTRL<0:63>={CTRL_I<0:15>CTRL_IN<0:15>CTRL_Q<0:15>CTRL_Q N<0:15>}=64'hffff000000000000.

[0055] According to the input control word from 0 to 63, the above control signal is cyclically shifted right.

[0056] But this scheme will be subject to the condition |K I |+|K Q |=16, that is, the total current remains unchanged. Taking the control word from 0 to 16 as an example, according to the above control word scheme, when the control word increases, the open branch current gradually transfers from I path to Q path, and the phase change will appear as follows Figure 2 As shown in the figure, the trend of dense on both sides and sparse in the middle will cause a significant decrease in PI linearity, such as Figure 3 The nonlinear situation shown.

[0057] Figure 4 To improve the phase interpolator circuit diagram. This structure uses current-mode DAC (CDAC) to adjust the current of each branch according to the corresponding binary control word. Its purpose is to use more accurate W in formula (2) Q / W I To achieve smaller error. Assume that the target output phase is Right now Under the original control word scheme, the closest case is CODE=10, that is, K Q =10,K I =6, there is But the improved control word scheme is not affected by |K I |+|K Q |=16 conditions, so the current ratio can be set to K Q =12,K I =7, then we have The smaller the error value, the significantly improved linearity can be achieved. Theoretically, arbitrary phase interpolation can be achieved within the accuracy supported by the CDAC. However, this solution requires storage of the control word input at the corresponding phase, which requires additional digital storage circuitry. Furthermore, as the phase interpolation accuracy increases (increases the number of CDAC bits), the digital resource expenditure increases significantly.

[0058] Therefore, it can be seen that improving the linearity of the phase interpolator in a simple and effective way while effectively controlling the circuit area has become an urgent problem to be solved.

[0059] The phase interpolation circuit in the prior art has the problems of low linearity, high circuit resources and power consumption. Figure 5 As shown, an embodiment of the present invention proposes a phase interpolator circuit, comprising: a current source module 1, a control word decoding module 2, a phase interpolation module 3 and a buffer output module 4;

[0060] The current source module 1 is used to output 16 I currents and 16 Q currents to the phase interpolation module 3 according to pre-configured weights;

[0061] The control word decoding module 2 is used to decode the external input 6-bit binary CODE into a corresponding 64-bit control signal and output it to the phase interpolation module 3;

[0062] The phase interpolation module 3 includes 16 units, each of which is divided into an I branch and a Q branch, and each unit includes four pairs of differential transistors. The phase interpolation module 3 is used to turn on or off the differential transistors of the corresponding path according to the 64-bit control signal, redistribute the weights of the externally input four-phase clock signal, and adjust the current of each branch so that the total transconductance of the Q branch and the I branch respectively changes sinusoidally and cosinely with the increase of the externally input control word, thereby achieving phase interpolation and generating an output voltage.

[0063] The buffer output module 4 is used to restore the output voltage to full swing and output it.

[0064] The embodiment of the present invention addresses the nonlinearity of linear modulation in traditional phase interpolation circuits and the theoretical expression of the output phase of phase interpolation circuits, and designs a multi-segment linear approximate sine modulation scheme. By adjusting the weights of the four-phase clock signals and the current ratios of each branch, appropriate error compensation is achieved. As a result, the final circuit only needs to adjust the currents of each unit to the appropriate ratio to achieve good phase interpolation linearity. This effectively improves circuit linearity without increasing additional power consumption and resource expenditure.

[0065] In this embodiment of the present invention, current source module 1 configures weights for different CODE inputs and outputs a near-sinusoidal modulated current via a phase interpolation module. This module receives an external bias voltage, Vb, and outputs 16 I currents and 16 Q currents. Current mirrors replicate the corresponding currents to the phase interpolation module, which then controls the transistor aspect ratio to adjust the output current.

[0066] In response to the sinusoidal modulation requirements of formula (2), Figure 6 Taking the change of CODE from 0 to 16 as an example, the curve of the total transconductance of Q path in the traditional PI structure changes with CODE. Since the tail current of each unit in the traditional PI architecture is the same, the total transconductance of Q path increases linearly. In order to achieve the sinusoidal modulation required by formula (2), that is, The target transconductance change trend should be as shown in the corresponding curve in the figure. The area shown in the figure is the transconductance error between the traditional PI architecture modulation and the ideal modulation. However, it is difficult to directly and accurately implement sinusoidal modulation. When CODE switches from 15 to 16, the transconductance of the Q path will have a very small step. Therefore, the compensation curve in the figure is used to complete the multi-segment linear approximation of the Q path transconductance, and the transconductance increase ratio corresponding to each CODE is set to For the total I-path transconductance, the top and bottom are reversed. For example, the I-path current ratio is {2, 2, 3, 3, 3, 4, 4, 4, 7, 7, 7, 7, 7, 7, 7}. In this case, the total Q-path and I-path transconductances vary approximately sinusoidally and cosine-like, respectively, as CODE increases. Because the compensation effect depends on the ratio of the corresponding currents of each unit, the effects of process, power supply voltage, and temperature are effectively controlled under normal operating conditions of each transistor in the circuit. The outputs of the current source module are 16 I-path currents and 16 Q-path currents.

[0067] The control word decoding module 2 decodes the input binary control word into the corresponding control signal. The input CODE is a 6-bit binary control word, corresponding to inputs 0 to 63. The 64-bit control signal generated by the control word decoding module is represented as {IP<0:15>, IN<0:15>, QP<0:15>, QN<0:15>}, which are respectively input to the phase interpolation module to control the opening or closing of the differential pair tubes of the corresponding paths. When CODE increases from 0 to 63, the corresponding opened path is from I of the IP path, to IN of the I path, to QP of the Q path, and finally to QN of the Q path. Since the current compensation is redistributed for the tail current to achieve sinusoidal modulation, a simple cyclic right shift cannot be used for the control signal.

[0068] A gate circuit is added to re-modulate the generation of each control signal. When CODE changes from 0 to 16, that is, the I current gradually transfers to the Q path, the control word solution of CTRL cyclically shifting right can achieve the function, but when CODE changes from 16 to 32, 48 to 64, the following will occur Figure 7 The error of the traditional planning curve is shown in the figure. The new planning curve in the figure is the transconductance modulation that should be achieved in theory. Therefore, the decoding of the control signal needs to be readjusted as follows Figure 8 The scheme shown is to reverse the order in which the control words are turned on in the I and Q paths when CODE changes from 16 to 32 and 48 to 64.

[0069] The control word decoding module is further used to adjust the decoding logic according to the sinusoidal modulation relationship;

[0070] The decoding logic expression corresponding to the generated 64-bit control signal is:

[0071]

[0072] Among them, CTRL new is the i-th bit of the 64-bit control signal; when CODE changes from 16 to 32 and 48 to 64, the order in which the control signals are turned on in the I path and the Q path is reversed.

[0073] The phase interpolation module 3 performs phase interpolation on the input four-phase clock signal based on the input control signal. Specifically, the control signal turns on or off the differential pairs of transistors in the corresponding branch paths, controlling the corresponding components of each input clock to achieve weighted adjustment of the output clock phase. The four-phase output currents corresponding to the four-phase input clocks are summed, and then converted into voltage signals through a load circuit to achieve digitally controllable phase interpolation of the four-phase clock. The IP phase, IN phase, QP phase, and QN phase corresponding to the four phases in the four-phase clock signal are 90 degrees apart, respectively; therefore, the four-phase clock signal is a four-phase quadrature clock signal. The phase interpolation module also includes a common load resistor; the common load resistor is used to sum the currents of each branch in each unit and convert it into an output voltage. The load circuit described above is the common load resistor. Using a common load to achieve current summation of each branch, by selecting a load of appropriate size, can not only ensure the normal operating state of the transistors under each code, but also provide the phase interpolation module with a certain gain to avoid the problem that the output buffer module requires additional delay to recover the full swing for smaller swings.

[0074] Furthermore, the current source module 1 is also used to redistribute the tail current of each unit in the phase interpolation module 3 to compensate for the nonlinear error of the phase interpolation module 3 .

[0075] The circuit diagram of the phase interpolation module 3 is as follows: Figure 9 As shown in the figure. By receiving a 64-bit control signal, the corresponding differential pair is enabled. The tail current is provided by the current source module, achieving phase interpolation of the corresponding clock signal. Through a common load resistor, the currents of each unit and branch are summed, ultimately converting them into an output voltage. Generating the Q-phase signal requires only adjusting the position of the input control signal. For example, the CTRL_I of the control word decoding module is fed into the CTRL_Q of the phase interpolation module, and so on.

[0076] The sine component and cosine component of the output voltage generated by the phase interpolation module 3 change in a sine manner and a cosine manner respectively according to the 64-bit control signal, so that the phase of the output voltage is in a linear relationship with the 64-bit control signal.

[0077] The buffer output module 4 restores the output voltage of the phase interpolation module to a square wave signal with full amplitude, and then outputs it. Figure 10 As shown, it includes a DC blocking capacitor, a self-biased inverter, an inverter and two latch-type inverters; the self-biased inverter is connected to the first latch-type inverter through the inverter, and the first latch-type inverter is connected to the second latch-type inverter through two consecutive inverters.

[0078] Since the total current flowing through the load resistor of the phase interpolation module is different under different CODEs, the following will occur: Figure 11 The common-mode input voltage changes with CODE as shown. Therefore, when an input signal arrives, the DC-blocking capacitors at the input terminals prevent the influence of the input common-mode voltage. The subsequent self-biased inverter provides input bias, ensuring the circuit operates normally under different operating conditions. The latched inverter jumps at the zero-crossing point of the two inverted signals output by the self-biased inverter, propagating the voltage signal backward to drive the corresponding subsequent circuits. The latched structure of the latched inverter ensures the differential nature of the output signal.

[0079] In a specific embodiment, the circuit is implemented using SMIC's 28nm process technology. The simulation conditions are that the power supply voltage VCC is 0.9V and the ground voltage GND is 0V. The four-phase clock input signal is a sine wave with a common-mode voltage Vcm=0.8V, a peak-to-peak value Vpp=0.16V, and a frequency f=3.125GHz, and the four-phase clocks IP, IN, QP, and QN are 90 degrees out of phase. Set the input control word CODE from 0 to 32. After a period of transient simulation, the output signal is stable. At this time, measure the delay of the output signal relative to the input signal IP, and use CODE as the horizontal axis and the measured delay as the vertical axis. The waveform obtained at this time should be approximately a straight line. Further measure the linearity of the straight line. Here, the integral nonlinearity INL is used as the measurement indicator, and it is obtained. Figure 12 The waveform of the simulation result based on this embodiment is shown. Figure 13 The simulation data based on this embodiment is shown in Figure 1. At a power supply voltage of 0.9V, the integral nonlinearity at each process corner temperature is less than 1LSB, demonstrating the stability and good linearity of the circuit under different operating environments.

[0080] This embodiment of the present invention adjusts the weights of the four-phase clock signals of each unit in the phase interpolation module using a control signal corresponding to an externally input 6-bit binary control word, thereby adjusting the proportion of each phase current and achieving multi-segment linear approximate sinusoidal modulation of the current. This compensates for the weighted sine and cosine variations that cannot be achieved with traditional schemes, effectively reducing nonlinear errors. This solves the technical problems of low linearity, high circuit resources, and high power consumption in existing phase interpolation circuits, improving the linearity of phase interpolation while adding only a small amount of digital logic, avoiding the use of storage circuits, and effectively controlling digital resources and area expenditures. This approach is suitable for applications with stringent area and resource expenditure constraints.

[0081] On the basis of the above embodiments, the present invention further provides an integrated circuit, comprising the phase interpolator circuit as described in any one of the above embodiments.

[0082] With the rapid development of high-speed serial communication technology, key integrated circuits such as SerDes (serializer / deserializer) interfaces, DDR memory systems, and high-speed data converters are placing higher demands on the phase control accuracy of clock signals. The present invention proposes a phase interpolator circuit with high linearity. It can perform phase shifting on the input signal using a given input control word, enabling digital control of the output phase, thereby improving the linearity of the integrated circuit incorporating the phase interpolator circuit.

[0083] It will be easily understood by those skilled in the art that the above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

Claims

1. A phase interpolator circuit, characterized in that: include: Current source module, control word decoding module, phase interpolation module and buffer output module; The current source module is used to output 16 I currents and 16 Q currents to the phase interpolation module according to pre-configured weights; The control word decoding module is used to decode the externally input 6-bit binary control word into a corresponding 64-bit control signal and output it to the phase interpolation module; The phase interpolation module includes 16 units, each of which is divided into an I branch and a Q branch, and each unit includes four pairs of differential transistors. The phase interpolation module is used to turn on or off the differential transistors of the corresponding path according to the 64-bit control signal, redistribute the weights of the externally input four-phase clock signal, and adjust the current of each branch so that the total transconductance of the Q branch and the I branch respectively changes sinusoidally and cosinely with the increase of the externally input control word, thereby achieving phase interpolation and generating an output voltage. The buffer output module is used to restore the output voltage to full swing and output it.

2. The phase interpolator circuit according to claim 1, wherein The sine component and cosine component of the output voltage change in a sine manner and a cosine manner respectively corresponding to the 64-bit control signal, so that the phase of the output voltage is in a linear relationship with the 64-bit control signal.

3. The phase interpolator circuit according to claim 1, wherein The IP phase, IN phase, QP phase, and QN phase corresponding to the four-phase clock in the four-phase clock signal are 90 degrees apart in sequence.

4. The phase interpolator circuit according to claim 1, wherein The 64-bit control signal generated by the control word decoding module is represented as {IP<0:15>, IN<0:15>, QP<0:15>, QN<0:15>}, which is respectively input into the phase interpolation module to control the opening or closing of the differential pair transistors of the corresponding path.

5. The phase interpolator circuit according to claim 4, wherein: The control word decoding module is further used to adjust the decoding logic according to the sinusoidal modulation relationship; The decoding logic expression corresponding to the generated 64-bit control signal is: Among them, CTRL new is the i-th bit of the 64-bit control signal; when the control word changes from 16 to 32 and 48 to 64, the order in which the control signals are turned on in the I path and the Q path is reversed.

6. The phase interpolator circuit according to claim 4, wherein: The phase interpolation module further includes a common load resistor; The common load resistor is used to add the currents of the branches in the units and convert them into an output voltage.

7. The phase interpolator circuit according to claim 1, wherein The buffer output module includes a DC blocking capacitor, a self-biased inverter, an inverter, and two latch-type inverters; the self-biased inverter is connected to the first latch-type inverter through the inverter, and the first latch-type inverter is connected to the second latch-type inverter through two consecutive inverters; The DC blocking capacitor and the self-biased inverter are used to readjust the common mode voltage of the output voltage so that the phase interpolator circuit is in a normal working state; The inverter inverts the input signal; The latch-type inverter jumps at the zero-crossing position of the two inverted signals input, propagates the voltage signal of the output voltage backward, drives the corresponding circuit of the subsequent stage, and thus restores the output voltage to the full swing and outputs it.

8. The phase interpolator circuit according to claim 1, wherein The current source module is further used to redistribute the tail current of each unit in the phase interpolation module to compensate for the nonlinear error of the phase interpolation module.

9. An integrated circuit, characterized in that: Comprising a phase interpolator circuit as claimed in any one of claims 1 to 8.

Images