Semiconductor structure and forming method thereof

Abstract

The invention discloses a semiconductor structure and a forming method thereof, and the structure comprises a substrate which comprises a storage unit region, and the storage unit region extends along a first direction; the split-gate structure is located on the substrate of the storage unit area, the split-gate structure comprises a control gate structure and floating gate structures located on the two sides of the control gate structure in the first direction respectively, and the contact faces of the floating gate structures and the control gate structure are in a multi-stage step shape; and the erasing gate structure covers the top of the split gate structure. The working efficiency of the semiconductor structure can be guaranteed.

Description

Technical Field

[0001] Embodiments of the present invention relate to the field of semiconductor manufacturing, and in particular to a semiconductor structure and a method for forming the same. Background Art

[0002] Flash memory devices, as non-volatile storage devices, feature high storage density and ease of programming and erasing, making them widely used in consumer electronics, servers, industrial electronics, and other fields. Flash memory device structures can be categorized as stacked-gate and split-gate flash memory. Split-gate flash memory offers advantages such as high programming speed and no over-erase effects, making it widely used in standalone NOR flash memory and embedded flash memory. Floating-gate flash memory, meanwhile, is widely used in high-reliability applications such as automotive electronics and process control due to its excellent data retention and good erase and write capabilities. Summary of the Invention

[0003] The problem solved by the embodiments of the present invention is to provide a semiconductor structure and a method for forming the same, which are beneficial to ensuring the working efficiency of the semiconductor structure.

[0004] To solve the above problems, an embodiment of the present invention provides a semiconductor structure, including: a substrate, including a storage cell area, the storage cell area extending along a first direction; a split gate structure, located on the substrate of the storage cell area, the split gate structure including a control gate structure, and floating gate structures located on both sides of the control gate structure along the first direction, the contact surface between the floating gate structure and the control gate structure is a multi-step morphology; an erase gate structure, covering the top of the split gate structure.

[0005] Correspondingly, an embodiment of the present invention also provides a method for forming a semiconductor structure, including: providing a substrate, including a storage cell area; forming a split gate structure on the substrate of the storage cell area, the split gate structure including a control gate structure, and floating gate structures respectively located on both sides of the control gate structure along a first direction, the contact surface between the floating gate structure and the control gate structure having a multi-step morphology; forming an erase gate structure covering the top of the split gate structure.

[0006] Compared with the prior art, the technical solution of the embodiment of the present invention has the following advantages:

[0007] In the semiconductor structure provided by an embodiment of the present invention, the split gate structure is located on the substrate of the storage cell area, and the split gate structure includes a control gate structure and a floating gate structure located on both sides of the control gate structure along a first direction, and the contact surface between the floating gate structure and the control gate structure is a multi-step-like morphology; in the embodiment of the present invention, the contact surface between the floating gate structure and the control gate structure is a multi-step-like morphology, and each step-like morphology has a corner, that is, the contact surface between the floating gate structure and the control gate structure has multiple corners, and the tip of the corner is prone to produce a tip discharge effect, so the electric field at the tip of the corner is larger, and electrons are more easily coupled from the control gate structure into the floating gate structure, which is beneficial to improving the coupling ratio (coupling ratio) between the control gate structure and the floating gate structure, thereby improving the writing efficiency of the semiconductor structure, and further beneficial to ensuring the working efficiency of the semiconductor structure.

[0008] In the formation method provided in an embodiment of the present invention, a split-gate structure is formed on the substrate of the storage cell area, and the split-gate structure includes a control gate structure and a floating gate structure respectively located on both sides of the control gate structure along a first direction, and the contact surface between the floating gate structure and the control gate structure is a multi-step-like morphology; in an embodiment of the present invention, the contact surface between the floating gate structure and the control gate structure is a multi-step-like morphology, and each step-like morphology has a corner, that is, the contact surface between the floating gate structure and the control gate structure has multiple corners, and the tip of the corner is prone to produce a tip discharge effect, so the electric field at the tip of the corner is larger, and electrons are more easily coupled from the control gate structure into the floating gate structure, which is beneficial to improving the coupling ratio (coupling ratio) between the control gate structure and the floating gate structure, thereby improving the writing efficiency of the semiconductor structure, and further beneficial to ensuring the working efficiency of the semiconductor structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figures 1 to 3 is a schematic structural diagram of an embodiment of a semiconductor structure of the present invention;

[0010] Figures 4 to 24 1 is a schematic structural diagram corresponding to each step in an embodiment of a method for forming a semiconductor structure of the present invention. DETAILED DESCRIPTION

[0011] As can be seen from the background technology, the coupling ratio between the control gate (CG) and the floating gate (FG) of the memory cell of the flash memory directly affects the write efficiency of the floating gate type flash memory. Improving the coupling ratio of the control gate to the floating gate is crucial for the working efficiency of the floating gate type flash memory. At present, after the floating gate is completed, an oxide-nitride-oxide (ONO) is deposited, and then the control gate is deposited on the ONO. The ONO is used as a dielectric to form a capacitor, and the control gate uses this capacitor to control the floating gate. Based on the current process flow, in order to increase the coupling ratio of the control gate to the floating gate, the thickness of the ONO must be reduced. While thinning the thickness of the ONO, the storage time of the charge will be reduced, making it difficult to ensure the working efficiency of the semiconductor structure.

[0012] In order to solve the technical problem, an embodiment of the present invention provides a semiconductor structure, including: a substrate, including a storage cell area, the storage cell area extending along a first direction; a split gate structure, located on the substrate of the storage cell area, the split gate structure including a control gate structure, and a floating gate structure located on both sides of the control gate structure along the first direction, the contact surface between the floating gate structure and the control gate structure has a multi-step morphology; an erase gate structure, covering the top of the split gate structure.

[0013] In an embodiment of the present invention, the contact surface between the floating gate structure and the control gate structure has a multi-step-like morphology, and each step-like morphology has a corner, that is, the contact surface between the floating gate structure and the control gate structure has multiple corners, and the tips of the corners are prone to produce a tip discharge effect. The electric field at the tips of the corners is larger, and electrons are more easily coupled from the control gate structure into the floating gate structure, which is beneficial to improving the coupling ratio (coupling ratio) between the control gate structure and the floating gate structure, thereby improving the writing efficiency of the semiconductor structure, and further beneficial to ensuring the working efficiency of the semiconductor structure.

[0014] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0015] Figures 1 to 3 FIG. 1 is a schematic structural diagram of a semiconductor structure according to an embodiment of the present invention.

[0016] Combined with reference Figures 1 to 3 , Figure 2 yes Figure 1 Cross-sectional view along AA direction, Figure 3 yes Figure 1 The cross-sectional view along the BB direction shows a semiconductor structure comprising: a substrate 100, comprising a memory cell region 100a, the memory cell region 100a being arranged along a first direction (eg Figure 1The split gate structure 700 is located on the substrate 100 in the memory cell area 100a. The split gate structure 700 includes a control gate structure 500 and floating gate structures 320 located on both sides of the control gate structure 500 along a first direction. The contact surface between the floating gate structure 320 and the control gate structure 500 has a multi-step morphology. The erase gate structure 800 covers the top of the split gate structure 700.

[0017] As an example, in this embodiment, the semiconductor structure is a flash memory device (Flash Memory), specifically, a Nor flash memory, which is a non-volatile storage device.

[0018] Specifically, in this embodiment, the semiconductor structure is a split-gate memory.

[0019] The substrate 100 provides a process operation basis for the formation process of the semiconductor structure.

[0020] In this embodiment, the material of the substrate 100 is silicon. In other embodiments, the substrate material may be one or more of germanium, silicon germanium, silicon carbide, gallium arsenide, and indium gallium. The substrate may also be other types of substrates, such as a silicon-on-insulator substrate or a germanium-on-insulator substrate. The substrate material may be a material suitable for process requirements or easy to integrate.

[0021] The memory cell region 100 a is used to form a split-gate memory structure composed of a floating gate (Floating Gate) structure 320 , a coupling gate (CG) structure 500 , and an erase gate (EG) structure 800 .

[0022] In this embodiment, the memory cell region 100a extends along the first direction and along the second direction (eg Figure 1 The second direction is perpendicular to the first direction.

[0023] The memory cell region 100 a is used to form split-gate memory cells extending along a first direction, and to isolate the split-gate memory cells in adjacent memory cell regions 100 a from each other.

[0024] In this embodiment, the memory cell region 100 a is used as a first active region, and the substrate 100 further includes a second active region 100 b extending along a second direction and spanning across the plurality of memory cell regions 100 a.

[0025] Specifically, a substrate is formed in the substrate 100 of the first active area and the second active area 100b, and isolation structures are formed in the substrate 100 on both sides of the first active area along the second direction and in the substrate 100 on both sides of the second active area 100b along the first direction.

[0026] The split gate structure 700 is used to implement signal writing of the memory. Specifically, the floating gate structure 320 is used as a unit structure for storing data in the memory, and the control gate structure 500 is used to electrically connect to the word line (WL) to control the longitudinal electric field of the floating gate structure 320.

[0027] Specifically, a high voltage is applied to the control gate structure 500 through the word line to create a strong electric field between the floating gate structure 320 and the control gate structure 500. The strong electric field injects a portion of electrons into the floating gate structure 320, thereby achieving electron injection and signal writing.

[0028] In this embodiment, the contact surface between the floating gate structure 320 and the control gate structure 500 has a multi-step-like morphology, and each step-like morphology has a corner, that is, the contact surface between the floating gate structure 320 and the control gate structure 500 has multiple corners, and the tips of the corners are prone to produce a tip discharge effect. The electric field at the tips of the corners is larger, and electrons are more easily coupled from the control gate structure 500 into the floating gate structure 320, which is beneficial to improving the coupling ratio (coupling ratio) between the control gate structure 500 and the floating gate structure 320, thereby improving the writing efficiency of the semiconductor structure, and further beneficial to ensuring the working efficiency of the semiconductor structure.

[0029] In this embodiment, the contact surface between the floating gate structure 320 and the control gate structure 500 is a multi-step morphology with the lateral dimension gradually increasing from top to bottom along the longitudinal direction.

[0030] The contact surface between the floating gate structure 320 and the control gate structure 500 is a multi-step-like morphology with gradually increasing lateral dimensions from top to bottom along the longitudinal direction, that is, the space between the floating gate structures 320 adjacent to each other along the first direction in the storage cell area 100a is a space with gradually decreasing dimensions from top to bottom along the longitudinal direction. The semiconductor process is usually carried out from top to bottom, which is conducive to the formation of the multi-step-like morphology of the floating gate structure 320 and the formation of the control gate structure 500 between adjacent floating gate structures 320.

[0031] In this embodiment, the floating gate structures 320 located on both sides of the control gate structure 500 are symmetrical with respect to the control gate structure 500 .

[0032] The floating gate structures 320 located on both sides of the control gate structure 500 are arranged symmetrically with respect to the control gate structure 500, which is beneficial to ensuring that the electric field is more evenly distributed on both sides of the control gate structure 500, improving the capacitive coupling efficiency between the floating gate structure 320 and the control gate structure 500, and improving the programming efficiency of the memory. The uniform electric field distribution is also beneficial to reducing charge traps and insulation layer damage caused by excessive local electric fields, thereby improving the reliability and life of the semiconductor structure.

[0033] In this embodiment, in the contact surface between the floating gate structure 320 and the control gate structure 500 having a multi-stepped morphology, the angle of the step corner is less than or equal to 90°.

[0034] The angle of the step corner is less than or equal to 90°, which is beneficial to enhancing the tip discharge effect, further making the electric field at the corner tip larger, and further beneficial to improving the coupling rate between the control gate structure 500 and the floating gate structure 320, thereby improving the writing efficiency of the semiconductor structure.

[0035] In this embodiment, the contact surface between the floating gate structure 320 and the control gate structure 500 has a multi-stepped morphology, and the lateral dimension of each step is to The longitudinal dimension of each step is to This is beneficial to ensuring sufficient contact area between the floating gate structure 320 and the control gate structure 500, improving device writing efficiency, and at the same time keeping the height of the split gate structure 700 formed by the floating gate structure 320 and the control gate structure 500 not too large, thereby ensuring the integration of the semiconductor structure.

[0036] In this embodiment, the control gate structure 500 extends along the second direction across the plurality of memory cell regions 100 a .

[0037] Specifically, the control gate structure 500 is located on the second active region 100 b along the second direction.

[0038] In this embodiment, the floating gate structure 320 is made of polysilicon; and the control gate structure 500 is made of polysilicon.

[0039] In this embodiment, the semiconductor structure further includes a first dielectric layer 600 located between the floating gate structure 320 and the control gate structure 500 .

[0040] The first dielectric layer 600 is used to isolate the floating gate structure 320 from the control gate structure 500 .

[0041] In this embodiment, the first dielectric layer 600 further extends between the control gate structure 500 and the substrate 100 to isolate the control gate structure 500 from the substrate 100 .

[0042] In this embodiment, the first dielectric layer 600 is an Oxide-Nitride-Oxide (ONO) structure including a silicon oxide layer, a silicon nitride layer on the silicon oxide layer, and a silicon oxide layer on the silicon nitride layer.

[0043] In this embodiment, a second dielectric layer is further formed between the floating gate structure 320 and the substrate 100 .

[0044] The second dielectric layer is used to isolate the floating gate structure 320 from the substrate 100 .

[0045] In this embodiment, the material of the second dielectric layer includes silicon oxide, which has a better isolation effect.

[0046] The erase gate structure 800 is used to implement signal erasure of the memory.

[0047] Specifically, by applying a high voltage to the erase gate structure 800, a potential difference is formed in the dielectric between the erase gate structure 800 and the floating gate structure 320 due to the coupling capacitance, which can pull electrons in the floating gate structure 320 to the erase gate structure 800 through tunneling. As the electrons in the floating gate structure 320 are pulled out, the potential of the floating gate structure 320 increases, and the difference between its potential and that of the erase gate structure 800 decreases, weakening the potential difference between the dielectrics. Finally, the electrons in the floating gate structure 320 are completely pulled out, achieving signal erasure of the memory.

[0048] In this embodiment, the erase gate structure 800 further extends along the second direction to cover the top of the control gate structure 500 .

[0049] That is, the erase gate structure 800 extends along the second direction across multiple memory cell areas 100a and is located above the second active area 100b. In the memory cell area 100a, the erase gate structure 800 covers the top of the split gate structure 700. Between adjacent memory cell areas 100a, the erase gate structure 800 covers the top of the control gate structure 500.

[0050] In this embodiment, the erase gate structure 800 is made of polysilicon.

[0051] In this embodiment, a third dielectric layer is further formed between the split gate structure 700 and the erase gate structure 800 .

[0052] The third dielectric layer is used to isolate the split gate structure 700 from the erase gate structure 800 .

[0053] In this embodiment, the material of the third dielectric layer includes silicon oxide, which has a better isolation effect.

[0054] In this embodiment, the semiconductor structure further includes: a selection gate structure 200 located on both sides of the split gate structure 700 along the first direction.

[0055] The select gate structure 200 controls the conduction and shutdown of memory cells. In a memory array, the select gate structure 200 is used to select specific memory cells for read or write operations. By applying an appropriate voltage to the select gate structure 200, the channel of the memory cell can be opened or closed, thereby achieving precise control of the memory cell.

[0056] In this embodiment, the top surface of the control gate structure 500 is flush with the top surface of the select gate structure 200 .

[0057] The top surface of the control gate structure 500 is flush with the top surface of the select gate structure 200 , which helps to make the electric field distribution between the control gate structure 500 and the select gate structure 200 more uniform.

[0058] Accordingly, in this embodiment, the erase gate structure 800 further extends along the first direction to cover a portion of the top of the select gate structure 200 .

[0059] In this embodiment, the select gate structure 200 extends along the second direction across the plurality of memory cell regions 100 a .

[0060] Specifically, the selection gate structure 200 extends along the second direction and is located on the substrate 100 at both sides of the second active region 100 b.

[0061] Accordingly, in this embodiment, on the substrate 100 between adjacent memory cell regions 100 a , the select gate structures 200 are respectively located on both sides of the control gate structure 500 along the first direction.

[0062] In this embodiment, the material of the select gate structure 200 includes polysilicon.

[0063] In this embodiment, a fourth dielectric layer is formed on the sidewalls of the select gate structure 200 .

[0064] The fourth dielectric layer is used to isolate the select gate structure 200 from the floating gate structure 320 , and to isolate the select gate structure 200 from the control gate structure 500 .

[0065] In this embodiment, the fourth dielectric layer is an Oxide-Nitride-Oxide (ONO) structure including a silicon oxide layer, a silicon nitride layer on the silicon oxide layer, and a silicon oxide layer on the silicon nitride layer.

[0066] It should be noted that in the process of forming the erase gate structure 800, the oxide layer on the top of the select gate structure 200 is also patterned. In the process of patterning the oxide layer on the top of the select gate structure 200, a certain degree of over-etching is also caused to the top of the select gate structure 200, so that the top of the select gate structure 200 that is protruding from the erase gate structure 800 along the first direction presents a concave morphology.

[0067] Correspondingly, an embodiment of the present invention further provides a method for forming a semiconductor structure.

[0068] Figures 4 to 24 1 is a schematic structural diagram corresponding to each step in an embodiment of a method for forming a semiconductor structure of the present invention.

[0069] Combined with reference Figures 4 to 6 , Figure 5 yes Figure 4 Cross-sectional view along AA direction, Figure 6 yes Figure 4 A cross-sectional view along the BB direction is provided, wherein a substrate 100 is provided, including a memory cell region 100a, and the memory cell region 100a is arranged along a first direction (eg Figure 4 The X direction is shown in FIG.

[0070] As an example, in this embodiment, the semiconductor structure is a flash memory device (Flash Memory), specifically, a Nor flash memory, which is a non-volatile storage device.

[0071] Specifically, in this embodiment, the semiconductor structure is a split-gate memory.

[0072] The substrate 100 provides a process operation basis for the formation process of the semiconductor structure.

[0073] In this embodiment, the material of the substrate 100 is silicon. In other embodiments, the substrate material may be one or more of germanium, silicon germanium, silicon carbide, gallium arsenide, and indium gallium. The substrate may also be other types of substrates, such as a silicon-on-insulator substrate or a germanium-on-insulator substrate. The substrate material may be a material suitable for process requirements or easy to integrate.

[0074] The memory cell region 100 a is used to form a split-gate memory structure composed of a floating gate (Floating Gate) structure 320 , a coupling gate (CG) structure 500 , and an erase gate (EG) structure 800 .

[0075] In the step of providing the substrate 100 in this embodiment, the memory cell region 100a extends along the first direction and along the second direction (eg Figure 4 The second direction is perpendicular to the first direction.

[0076] The memory cell region 100 a is used to form split-gate memory cells extending along a first direction, and to isolate the split-gate memory cells in adjacent memory cell regions 100 a from each other.

[0077] In this embodiment, in the step of providing the substrate 100 , the memory cell region 100 a is used as the first active region, and the substrate 100 further includes a second active region 100 b extending along the second direction and spanning across the plurality of memory cell regions 100 a .

[0078] Specifically, a substrate is formed in the substrate 100 of the first active area and the second active area 100b, and isolation structures are formed in the substrate 100 on both sides of the first active area along the second direction and in the substrate 100 on both sides of the second active area 100b along the first direction.

[0079] In this embodiment, in the step of providing the substrate 100 , a selection gate structure 200 is further formed on the substrate 100 along the first direction and located on both sides of a region where a split gate structure to be formed subsequently is located.

[0080] Specifically, the selection gate structure 200 extends along the second direction and is located on the substrate 100 at both sides of the second active region 100 b.

[0081] The select gate structure 200 controls the conduction and shutdown of memory cells. In a memory array, the select gate structure 200 is used to select specific memory cells for read or write operations. By applying an appropriate voltage to the select gate structure 200, the channel of the memory cell can be opened or closed, thereby achieving precise control of the memory cell.

[0082] In this embodiment, in the step of providing the substrate 100 , the select gate structure 200 extends along the second direction across the plurality of memory cell regions 100 a .

[0083] In this embodiment, in the step of providing the substrate 100 , the select gate structures 200 and the substrate 100 adjacent to each other along the first direction form a groove 210 .

[0084] The groove 210 is used to provide a space for the subsequent formation of a split gate structure.

[0085] In this embodiment, the material of the select gate structure 200 includes polysilicon.

[0086] In this embodiment, in the step of providing the substrate 100 , a fourth dielectric layer is formed on the sidewalls of the select gate structure 200 .

[0087] The fourth dielectric layer is used to isolate the select gate structure 200 from a subsequently formed floating gate structure, and to isolate the select gate structure 200 from a subsequently formed control gate structure.

[0088] In this embodiment, in the step of providing the substrate 100 , the fourth dielectric layer is an Oxide-Nitride-Oxide (ONO) structure of a silicon oxide layer, a silicon nitride layer on the silicon oxide layer, and a silicon oxide layer on the silicon nitride layer.

[0089] Combined with reference Figure 4 middle Figure 24 A split gate structure 700 is formed on the substrate 100 of the memory cell area 100a. The split gate structure 700 includes a control gate structure 500 and floating gate structures 320 located on both sides of the control gate structure 500 along a first direction. The contact surface between the floating gate structure 320 and the control gate structure 500 has a multi-step morphology.

[0090] The split gate structure 700 is used to implement signal writing of the memory. Specifically, the floating gate structure 320 is used as a unit structure for storing data in the memory, and the control gate structure 500 is used to electrically connect to the word line (WL) to control the longitudinal electric field of the floating gate structure 320.

[0091] Specifically, a high voltage is applied to the control gate structure 500 through the word line to create a strong electric field between the floating gate structure 320 and the control gate structure 500. The strong electric field injects a portion of electrons into the floating gate structure 320, thereby achieving electron injection and signal writing.

[0092] In this embodiment, the contact surface between the floating gate structure 320 and the control gate structure 500 has a multi-step-like morphology, and each step-like morphology has a corner, that is, the contact surface between the floating gate structure 320 and the control gate structure 500 has multiple corners, and the tips of the corners are prone to produce a tip discharge effect. The electric field at the tips of the corners is larger, and electrons are more easily coupled from the control gate structure 500 into the floating gate structure 320, which is beneficial to improving the coupling ratio (coupling ratio) between the control gate structure 500 and the floating gate structure 320, thereby improving the writing efficiency of the semiconductor structure, and further beneficial to ensuring the working efficiency of the semiconductor structure.

[0093] In this embodiment, in the step of forming the split gate structure 700 on the substrate 100 in the memory cell region 100a, the contact surface between the floating gate structure 320 and the control gate structure 500 has a multi-step morphology with gradually increasing lateral dimensions from top to bottom along the longitudinal direction.

[0094] The contact surface between the floating gate structure 320 and the control gate structure 500 is a multi-step-like morphology with gradually increasing lateral dimensions from top to bottom along the longitudinal direction, that is, the space between the floating gate structures 320 adjacent to each other along the first direction in the storage cell area 100a is a space with gradually decreasing dimensions from top to bottom along the longitudinal direction. The semiconductor process is usually carried out from top to bottom, which is conducive to the formation of the multi-step-like morphology of the floating gate structure 320 and the formation of the control gate structure 500 between adjacent floating gate structures 320.

[0095] In this embodiment, in the step of forming the split gate structure 700 on the substrate 100 in the memory cell region 100 a , the floating gate structures 320 located on both sides of the control gate structure 500 are symmetrical with respect to the control gate structure 500 .

[0096] The floating gate structures 320 located on both sides of the control gate structure 500 are arranged symmetrically with respect to the control gate structure 500, which is beneficial to ensuring that the electric field is more evenly distributed on both sides of the control gate structure 500, improving the capacitive coupling efficiency between the floating gate structure 320 and the control gate structure 500, and improving the programming efficiency of the memory. The uniform electric field distribution is also beneficial to reducing charge traps and insulation layer damage caused by excessive local electric fields, thereby improving the reliability and life of the semiconductor structure.

[0097] In this embodiment, in the step of forming the split gate structure 700 on the substrate 100 in the memory cell region 100a, the angle of the step corners in the contact surface between the floating gate structure 320 and the control gate structure 500 is less than or equal to 90°.

[0098] The angle of the step corner is less than or equal to 90°, which is beneficial to enhancing the tip discharge effect, further making the electric field at the corner tip larger, and further beneficial to improving the coupling rate between the control gate structure 500 and the floating gate structure 320, thereby improving the writing efficiency of the semiconductor structure.

[0099] In this embodiment, the contact surface between the floating gate structure 320 and the control gate structure 500 has a multi-stepped morphology, and the lateral dimension of each step is to The longitudinal dimension of each step is to This is beneficial to ensuring sufficient contact area between the floating gate structure 320 and the control gate structure 500, improving device writing efficiency, and at the same time keeping the height of the split gate structure 700 formed by the floating gate structure 320 and the control gate structure 500 not too large, thereby ensuring the integration of the semiconductor structure.

[0100] In this embodiment, in the step of forming the split gate structure 700 on the substrate 100 in the memory cell region 100 a , the split gate structure 700 is formed on the substrate 100 in the memory cell region 100 a between the select gate structures 200 .

[0101] That is, the split gate structure 700 is formed in the groove 210 .

[0102] In this embodiment, in the step of forming the split gate structure 700 on the substrate 100 in the memory cell region 100 a , the top surface of the control gate structure 500 is flush with the top surface of the select gate structure 200 .

[0103] The top surface of the control gate structure 500 is flush with the top surface of the select gate structure 200 , which helps to make the electric field distribution between the control gate structure 500 and the select gate structure 200 more uniform.

[0104] In this embodiment, in the step of forming the split gate structure 700 on the substrate 100 in the memory cell region 100 a , the control gate structure 500 extends along the second direction across the plurality of memory cell regions 100 a .

[0105] Specifically, the control gate structure 500 is located on the second active region 100 b along the second direction.

[0106] In this embodiment, the floating gate structure 320 is made of polysilicon; and the control gate structure 500 is made of polysilicon.

[0107] Combined with reference Figures 4 to 9 The step of forming the split gate structure 700 on the substrate 100 of the memory cell area 100a includes: forming a floating gate material layer 310 in the memory cell area 100a, which extends along the first direction and covers the sidewalls and bottom of the groove 210 and the top of the selection gate structure 200.

[0108] The floating gate material layer 310 is used to form a floating gate structure 320 .

[0109] Accordingly, in this embodiment, the floating gate material layer 310 is made of polysilicon.

[0110] In this embodiment, in the step of forming the floating gate material layer 310 extending along the first direction to cover the sidewalls and bottom of the groove 210 and the top of the select gate structure 200 in the memory cell region 100a, the thickness of the floating gate material layer 310 is to

[0111] The longitudinal cross section of the floating gate material layer 310 (ie, the cross section along the thickness direction) is used to subsequently form a multi-stepped morphology. The thickness of the floating gate material layer 310 is to This is beneficial for providing a larger process window for the subsequent formation of a multi-step-like morphology, making the multi-step-like morphology easy to form.

[0112] Specifically, with reference to Figures 4 to 6 In the memory cell area 100a, the step of forming a floating gate material layer 310 extending along the first direction to cover the sidewalls and bottom of the groove 210 and the top of the selection gate structure 200 includes: forming an initial floating gate material layer 300 covering the substrate 100, the sidewalls and bottom of the groove 210, and the top of the selection gate structure 200.

[0113] The initial floating gate material layer 300 is used to form a floating gate material layer 310 .

[0114] In this embodiment, a second dielectric layer is further formed between the initial floating gate material layer 300 and the substrate 100 .

[0115] The second dielectric layer is used to isolate the floating gate structure 320 from the substrate 100 .

[0116] In this embodiment, the material of the second dielectric layer includes silicon oxide, which has a better isolation effect.

[0117] Combined with reference Figures 7 to 9 , Figure 8 yes Figure 7 Cross-sectional view along AA direction, Figure 9 yes Figure 7 In the cross-sectional view along the BB direction, the initial floating gate material layer 300 between the adjacent memory cell regions 100 a along the second direction is removed, and the initial floating gate material layer 300 located in the memory cell region 100 a is retained as the floating gate material layer 310 .

[0118] It should be noted that, in this embodiment, in the step of removing the initial floating gate material layer 300 between adjacent memory cell regions 100a along the second direction, the second dielectric layer at the bottom of the initial floating gate material layer 300 between adjacent memory cell regions 100a along the second direction is retained.

[0119] Combined with reference Figures 10 to 21 The floating gate material layer 310 at the bottom of the groove 210 is patterned, and the remaining floating gate material layer 310 covering the sidewall of the groove 210 and disconnected along the first direction is retained as a floating gate structure 320. The disconnected surface of the floating gate structure 320 has a multi-step morphology.

[0120] In this embodiment, during the step of patterning the floating gate material layer 310 at the bottom of the groove 210 , the floating gate material layer 310 covering the top of the select gate structure 200 is also removed.

[0121] In this embodiment, the step of patterning the floating gate material layer 310 at the bottom of the groove 210 includes: performing multiple sub-patterning processes on the floating gate material layer 310 at the bottom of the groove 210 until the floating gate material layer 310 at the bottom of the groove 210 is disconnected along the first direction, and each sub-patterning process forms a first-level step-like morphology on the surface of the floating gate structure 320.

[0122] Each sub-patterning process forms a step-like morphology on the surface of the floating gate structure 320, which means that each sub-patterning process can pattern the floating gate structure 320 into a step with a corner. Accordingly, multiple sub-patterning processes can form a multi-step morphology on the disconnected surface of the floating gate structure 320.

[0123] Accordingly, in this embodiment, during the step of performing multiple sub-patterning processes on the floating gate material layer 310 at the bottom of the groove 210 , the floating gate material layer 310 at the top of the select gate structure 200 is also removed.

[0124] In this embodiment, two sub-patterning processes are performed as an example for description, and the surface where the floating gate structure 320 is disconnected has a two-step morphology. The specific number of sub-patterning processes is not limited.

[0125] Specifically, in this embodiment, Figures 10 to 15 This is the first sub-graphics processing. Figures 16 to 21 This is the second sub-graphics processing.

[0126] In this embodiment, the sub-graphic processing includes: combining reference Figures 10 to 13 , forming a mask layer 410 of the floating gate material layer 310 covering the sidewalls of the groove 210 .

[0127] The mask layer 410 is used as a mask for patterning the floating gate material layer 310 at the bottom of the groove 210 .

[0128] In this embodiment, the floating gate material layer 310 at the bottom of the groove 210 is patterned along the mask layer 410, and the floating gate material layer 310 at the bottom of the mask layer 410 is retained. Accordingly, the thickness of the first mask layer 410 and the difference between the thickness of the mask layer 410 in each sub-patterning process and the thickness of the mask layer 410 in the previous sub-patterning process are the lateral dimensions of the corresponding steps. Therefore, in this embodiment, in the step of forming the floating gate material layer 310 covering the sidewalls of the groove 210, the thickness of the mask layer 410 in the first sub-patterning process is to The difference between the thickness of the mask layer 410 in each sub-patterning process and the thickness of the mask layer 410 in the previous sub-patterning process is to

[0129] In this embodiment, the material of the mask layer 410 includes silicon nitride.

[0130] Silicon nitride has a relatively high hardness as a mask and can easily form a large etching selectivity ratio with polysilicon, which is beneficial for reducing damage to the mask layer 410 when patterning the floating gate material layer 310, thereby ensuring the dimensional accuracy of the pattern transfer.

[0131] Specifically, with reference to Figure 10 and Figure 11 , Figure 10 Based on Figure 8 A cross-sectional view of Figure 11 Based on Figure 9 , the step of forming the mask layer 410 covering the floating gate material layer 310 on the sidewall of the groove 210 includes: forming a mask material layer 400 covering the floating gate material layer 310 .

[0132] The mask material layer 400 is used to form a mask layer 410 .

[0133] In this embodiment, in the step of forming the mask material layer 400 covering the floating gate material layer 310 , the mask material layer 400 also covers the top of the substrate 100 between adjacent memory cell regions 100 a and the sidewalls and top of the select gate structure 200 .

[0134] Accordingly, in this embodiment, in the step of forming the mask material layer 400 covering the floating gate material layer 310 , the mask material layer 400 also covers the second dielectric layer between adjacent memory cell regions 100 a along the second direction.

[0135] Combined with reference Figure 12 and Figure 13 , Figure 12 Based on Figure 10 A cross-sectional view of Figure 13 Based on Figure 11 , the floating gate material layer 310 covering the top of the select gate structure 200 and the mask material layer 400 covering the floating gate material layer 310 at the bottom of the groove 210 are removed, and the mask material layer 400 covering the floating gate material layer 310 covering the sidewall of the groove 210 is retained as the mask layer 410.

[0136] In this embodiment, a dry etching process is used to remove the floating gate material layer 310 covering the top of the select gate structure 200 and the mask material layer 400 covering the floating gate material layer 310 at the bottom of the groove 210 .

[0137] The dry etching process has the characteristic of anisotropic etching, which is beneficial for removing the floating gate material layer 310 covering the top of the selection gate structure 200 and the mask material layer 400 of the floating gate material layer 310 covering the bottom of the groove 210, while retaining the mask material layer 400 of the floating gate material layer 310 covering the side wall of the groove 210 as the mask layer 410.

[0138] Accordingly, in this embodiment, in the step of removing the floating gate material layer 310 covering the top of the selection gate structure 200 and the mask material layer 400 covering the floating gate material layer 310 at the bottom of the groove 210, the mask material layer 400 covering the top of the substrate 100 between adjacent storage cell areas 100a and the top of the selection gate structure 200 is also removed.

[0139] It should be noted that, in this embodiment, in the step of removing the mask material layer 400 covering the top of the substrate 100 between adjacent memory cell areas 100 a and the top of the select gate structure 200 , the second dielectric layer between adjacent memory cell areas 100 a along the second direction is also used to protect the substrate 100 .

[0140] Continue to combine references Figure 12 and Figure 13, a portion of the floating gate material layer 310 at the bottom of the groove 210 exposed by the mask layer 410 is removed, and a step-like morphology is formed in the floating gate material layer 310 at the bottom of the mask layer 410 .

[0141] Part of the floating gate material layer 310 at the bottom of the groove 210 exposed by the mask layer 410 is removed to form a step-like morphology, and the remaining thickness of the floating gate material layer 310 is retained for subsequent formation of a step-like morphology.

[0142] In this embodiment, a portion of the floating gate material layer 310 is removed to form a step-like morphology, that is, the thickness of the portion of the floating gate material layer 310 removed corresponds to the longitudinal dimension of the step. Thus, in this embodiment, in the step of removing the portion of the floating gate material layer 310 at the bottom of the groove 210 exposed by the mask layer 410, the thickness of the portion of the floating gate material layer 310 removed is to

[0143] In this embodiment, a dry etching process is used to remove a portion of the floating gate material layer 310 at the bottom of the groove 210 exposed by the mask layer 410 .

[0144] The dry etching process has the characteristic of anisotropic etching, which is conducive to obtaining a more accurate pattern conversion on the floating gate material layer 310 along the mask layer 410 and improving the dimensional accuracy of the floating gate structure 320 .

[0145] Accordingly, in this embodiment, in the step of removing the portion of the floating gate material layer 310 at the bottom of the groove 210 exposed by the mask layer 410 during the sub-patterning process, the portion of the floating gate material layer 310 at the top of the select gate structure 200 is also removed.

[0146] Combined with reference Figure 14 and Figure 15 , Figure 14 Based on Figure 12 A cross-sectional view of Figure 15 Based on Figure 13 sectional view, the mask layer 410 is removed.

[0147] The mask layer 410 is removed to prepare for subsequent processes.

[0148] In this embodiment, a wet etching process is used to remove the mask layer 410 .

[0149] The wet etching process can easily obtain a larger etching selectivity, thereby facilitating the complete removal of the mask layer 410 while minimizing damage to the floating gate material layer 310 .

[0150] Accordingly, in this embodiment, in the step of removing the mask layer 410 , the mask material layer 400 covering the sidewalls of the select gate structure 200 between adjacent memory cell regions 100 a is also removed.

[0151] In this embodiment, the mask layer 410 in each sub-patterning process covers the position of the step-like morphology of the floating gate material layer 310 formed in the previous sub-patterning process, and the spacing between adjacent mask layers 410 in each sub-patterning process is smaller than the spacing between adjacent mask layers 410 in the previous sub-patterning process.

[0152] The mask layer 410 in each sub-patterning process covers the position of the step-like morphology of the floating gate material layer 310 formed in the previous sub-patterning process, that is, the steps formed in the previous sub-patterning process are protected during the next sub-patterning process, and the spacing between adjacent mask layers 410 in each sub-patterning process is smaller than the spacing between adjacent mask layers 410 in the previous sub-patterning process. By reducing the mask opening of the floating gate material layer 310 at the bottom of the patterned groove 210, a multi-level step-like morphology with a gradually increasing lateral size from top to bottom along the longitudinal direction is formed.

[0153] Combined with reference Figure 16 and Figure 17 , Figure 16 Based on Figure 14 A cross-sectional view of Figure 17 Based on Figure 15 , which is a cross-sectional view of the second sub-patterning process, forming a mask material layer 400 covering the floating gate material layer 310; Figure 18 and Figure 19 , Figure 18 Based on Figure 16 A cross-sectional view of Figure 19 Based on Figure 17 , which is a cross-sectional view showing the steps of removing the floating gate material layer 310 covering the top of the select gate structure 200 and the mask material layer 400 covering the floating gate material layer 310 at the bottom of the groove 210, retaining the mask material layer 400 covering the floating gate material layer 310 on the sidewall of the groove 210 as the mask layer 410, and removing the floating gate material layer 310 of the thickness of the bottom of the groove 210 exposed by the mask layer 410, and forming a step-like morphology in the floating gate material layer 310 at the bottom of the mask layer 410; in combination with reference to FIG. Figure 20 and Figure 21 , Figure 20 Based on Figure 18 A cross-sectional view of Figure 21 Based on Figure 19 , which is a cross-sectional view showing the step of removing the mask layer 410.

[0154] The specific steps are detailed in the previous sub-graphic processing and will not be repeated here.

[0155] Combined with reference Figures 22 to 24 , Figure 23 yes Figure 22 Cross-sectional view along AA direction, Figure 24 yes Figure 22 In the cross-sectional view along the BB direction, a control gate structure 500 is formed extending along the second direction and filling between adjacent floating gate structures 320 of multiple memory cell regions 100a. The control gate structure 500 is also located on the substrate 100 between adjacent memory cell regions 100a and filled between adjacent selection gate structures 200 along the first direction.

[0156] Specifically, in this embodiment, before forming the control gate structure 500 extending along the second direction and filling the adjacent floating gate structures 320 of the multiple memory cell regions 100a, it also includes: removing the second dielectric layer between the floating gate structures 320 in the groove 210, and the second dielectric layer located between the adjacent selection gate structures 200 between the adjacent memory cell regions 100a.

[0157] In this embodiment, a wet etching process is used to remove the second dielectric layer.

[0158] The wet etching process can easily obtain a larger etching selectivity, thereby facilitating reducing damage to the floating gate structure 320 and the substrate 100 during the process of removing the second dielectric layer.

[0159] In this embodiment, after removing the second dielectric layer, the method further includes forming a first dielectric layer 600 conformally covering the stepped surface of the floating gate structure 320 .

[0160] The first dielectric layer 600 is used to isolate the floating gate structure 320 from the control gate structure 500 .

[0161] In this embodiment, the first dielectric layer 600 further extends to cover the top of the substrate 100 and the sidewalls of the select gate structure 200 between adjacent memory cell regions 100 a to isolate the control gate structure 500 from the substrate 100 .

[0162] In this embodiment, the first dielectric layer 600 is an Oxide-Nitride-Oxide (ONO) structure including a silicon oxide layer, a silicon nitride layer on the silicon oxide layer, and a silicon oxide layer on the silicon nitride layer.

[0163] Continue to combine references Figures 22 to 24 , forming an erase gate structure 800 covering the top of the split gate structure 700.

[0164] The erase gate structure 800 is used to implement signal erasure of the memory.

[0165] Specifically, by applying a high voltage to the erase gate structure 800, a potential difference is formed in the dielectric between the erase gate structure 800 and the floating gate structure 320 due to the coupling capacitance, which can pull electrons in the floating gate structure 320 to the erase gate structure 800 through tunneling. As the electrons in the floating gate structure 320 are pulled out, the potential of the floating gate structure 320 increases, and the difference between its potential and that of the erase gate structure 800 decreases, weakening the potential difference between the dielectrics. Finally, the electrons in the floating gate structure 320 are completely pulled out, achieving signal erasure of the memory.

[0166] Accordingly, in this embodiment, in the step of forming the erase gate structure 800 covering the top of the split gate structure 700 , the erase gate structure 800 further extends along the first direction to cover a portion of the top of the select gate structure 200 .

[0167] In this embodiment, in the step of forming the erase gate structure 800 covering the top of the split gate structure 700 , the erase gate structure 800 further extends along the second direction to cover the top of the control gate structure 500 .

[0168] That is, the erase gate structure 800 extends along the second direction across multiple memory cell areas 100a and is located above the second active area 100b. In the memory cell area 100a, the erase gate structure 800 covers the top of the split gate structure 700. Between adjacent memory cell areas 100a, the erase gate structure 800 covers the top of the control gate structure 500.

[0169] In this embodiment, the erase gate structure 800 is made of polysilicon.

[0170] In this embodiment, before forming the erase gate structure 800 covering the top of the split gate structure 700 , the process further includes: forming a third dielectric layer on the top of the split gate structure 700 .

[0171] The third dielectric layer is used to isolate the split gate structure 700 from the erase gate structure 800 .

[0172] In this embodiment, the material of the third dielectric layer includes silicon oxide, which has a better isolation effect.

[0173] It should be noted that in the process of forming the erase gate structure 800, the oxide layer on the top of the select gate structure 200 is also patterned. In the process of patterning the oxide layer on the top of the select gate structure 200, a certain degree of over-etching is also caused to the top of the select gate structure 200, so that the top of the select gate structure 200 that is protruding from the erase gate structure 800 along the first direction presents a concave morphology.

[0174] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be based on the scope defined by the claims.

Claims

1. A semiconductor structure, characterized in that include: A substrate comprising a memory cell region extending along a first direction; a split-gate structure located on the substrate of the memory cell region, the split-gate structure comprising a control gate structure and floating gate structures located on both sides of the control gate structure along the first direction, wherein a contact surface between the floating gate structure and the control gate structure has a multi-step morphology; An erase gate structure covers the top of the split gate structure.

2. The semiconductor structure according to claim 1, wherein The contact surface between the floating gate structure and the control gate structure is a multi-step morphology with a lateral dimension gradually increasing from top to bottom along the longitudinal direction.

3. The semiconductor structure according to claim 1, wherein: The floating gate structures respectively located on both sides of the control gate structure are symmetrical with respect to the control gate structure.

4. The semiconductor structure according to claim 1, wherein: In the contact surface between the floating gate structure and the control gate structure having a multi-stepped morphology, the angle of the step corner is less than or equal to 90°.

5. The semiconductor structure according to claim 1, wherein In the contact surface of the floating gate structure and the control gate structure with a multi-step morphology, the lateral dimension of each step is to The longitudinal dimension of each step is to 6. The semiconductor structure according to claim 1, wherein The semiconductor structure further includes: select gate structures located on both sides of the split gate structure along the first direction; The erase gate structure further extends along the first direction to cover a portion of the top of the select gate structure.

7. The semiconductor structure according to claim 6, wherein: A top surface of the control gate structure is flush with a top surface of the select gate structure.

8. The semiconductor structure according to claim 6, wherein: The memory cell areas are arranged at intervals along a second direction, and the second direction is perpendicular to the first direction; The control gate structure extends along the second direction across the plurality of memory cell regions; The erase gate structure further extends along the second direction to cover the top of the control gate structure; The select gate structure extends along the second direction across the plurality of memory cell regions.

9. The semiconductor structure according to claim 8, wherein: On the substrate between adjacent memory cell regions, the select gate structures are respectively located on both sides of the control gate structure along the first direction.

10. A method for forming a semiconductor structure, characterized in that: include: Providing a substrate, comprising a memory cell region, wherein the memory cell region extends along a first direction; forming a split-gate structure on the substrate of the memory cell region, the split-gate structure comprising a control gate structure and floating gate structures located on both sides of the control gate structure along the first direction, wherein a contact surface between the floating gate structure and the control gate structure has a multi-step morphology; An erase gate structure is formed covering the top of the split gate structure.

11. The method for forming a semiconductor structure according to claim 10, wherein: In the step of forming a split gate structure on the substrate of the memory cell area, the contact surface between the floating gate structure and the control gate structure has a multi-step morphology with a lateral dimension gradually increasing from top to bottom along the longitudinal direction.

12. The method for forming a semiconductor structure according to claim 10, wherein: In the step of forming a split gate structure on the substrate of the memory cell region, the floating gate structures respectively located on both sides of the control gate structure are symmetrical with respect to the control gate structure.

13. The method for forming a semiconductor structure according to claim 10, wherein: In the step of providing the substrate, a selection gate structure is further formed on the substrate along the first direction and located on both sides of the region where the split gate structure is located; In the step of forming a split gate structure on the substrate of the memory cell region, the split gate structure is formed on the substrate of the memory cell region between the select gate structures; In the step of forming an erase gate structure covering the top of the split gate structure, the erase gate structure further extends along the first direction to cover a portion of the top of the select gate structure.

14. The method for forming a semiconductor structure according to claim 13, wherein: In the step of forming a split gate structure on the substrate of the memory cell area, the top surface of the control gate structure is flush with the top surface of the select gate structure.

15. The method for forming a semiconductor structure according to claim 13, wherein: In the step of providing the substrate, the memory cell regions are arranged at intervals along a second direction, the select gate structure extends across the plurality of memory cell regions along the second direction, and the second direction is perpendicular to the first direction; In the step of forming a split gate structure on the substrate of the memory cell region, the control gate structure extends along the second direction across the plurality of memory cell regions; In the step of forming an erase gate structure covering the top of the split gate structure, the erase gate structure further extends along the second direction to cover the top of the control gate structure.

16. The method for forming a semiconductor structure according to claim 15, wherein: In the step of providing the substrate, the select gate structures adjacent to each other along the first direction and the substrate form a groove; The step of forming a split gate structure on the substrate of the memory cell area includes: forming a floating gate material layer in the memory cell area extending along the first direction to cover the sidewalls and bottom of the groove and the top of the select gate structure; performing patterning on the floating gate material layer at the bottom of the groove, retaining the remaining floating gate material layer covering the sidewall of the groove and disconnected along the first direction as the floating gate structure, wherein the disconnected surface of the floating gate structure has a multi-step morphology; A control gate structure is formed extending along the second direction and filling between adjacent floating gate structures of a plurality of memory cell regions. The control gate structure is also located on the substrate between adjacent memory cell regions and filled between adjacent selection gate structures along the first direction.

17. The method for forming a semiconductor structure according to claim 16, wherein: In the step of forming a floating gate material layer in the memory cell region extending along the first direction to cover the sidewalls and bottom of the groove and the top of the select gate structure, the thickness of the floating gate material layer is to 18. The method for forming a semiconductor structure according to claim 16, wherein: The step of patterning the floating gate material layer at the bottom of the groove comprises: performing multiple sub-patterning processes on the floating gate material layer at the bottom of the groove until the floating gate material layer at the bottom of the groove is disconnected along the first direction, each sub-patterning process forming a step-like morphology on the surface of the floating gate structure; The sub-patterning process includes: forming a mask layer of a floating gate material layer covering the sidewalls of the groove; removing a portion of the floating gate material layer at the bottom of the groove exposed by the mask layer, thereby forming a step-shaped morphology in the floating gate material layer at the bottom of the mask layer; removing the mask layer; In which, the mask layer in each sub-patterning process covers the position of the step-like morphology of the floating gate material layer formed in the previous sub-patterning process, and the spacing between adjacent mask layers in each sub-patterning process is smaller than the spacing between adjacent mask layers in the previous sub-patterning process.

19. The method for forming a semiconductor structure according to claim 18, wherein: The mask layer is removed by a wet etching process.

20. The method for forming a semiconductor structure according to claim 18, wherein: In the step of performing multiple sub-patterning processes on the floating gate material layer at the bottom of the groove, the floating gate material layer at the top of the select gate structure is also removed; In the sub-patterning process, in the step of removing a portion of the floating gate material layer having a thickness at the bottom of the groove exposed by the mask layer, a portion of the floating gate material layer having a thickness at the top of the select gate structure is also removed.

21. The method for forming a semiconductor structure according to claim 18, wherein: The step of forming a mask layer of the floating gate material layer covering the sidewalls of the groove includes: forming a mask material layer covering the floating gate material layer; The floating gate material layer covering the top of the select gate structure and the mask material layer covering the floating gate material layer at the bottom of the groove are removed, and the mask material layer covering the floating gate material layer at the sidewall of the groove is retained as the mask layer.

22. The method for forming a semiconductor structure according to claim 21, wherein: In the step of forming a mask material layer covering the floating gate material layer, the mask material layer also covers the top of the substrate between adjacent memory cell regions, and the sidewalls and top of the select gate structure; In the step of removing the floating gate material layer covering the top of the select gate structure and the mask material layer covering the floating gate material layer at the bottom of the groove, the mask material layer covering the top of the substrate between adjacent memory cell areas and the top of the select gate structure is also removed; In the step of removing the mask layer, the mask material layer covering the sidewalls of the select gate structure between adjacent memory cell regions is also removed.

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