Thin film transistor, pixel array substrate, display device and manufacturing method thereof

Abstract

The invention relates to a thin film transistor, a pixel array substrate, a display device and a manufacturing method thereof. The manufacturing method of the thin film transistor comprises the following steps: forming a first metal layer on a substrate and an insulating layer covering the first metal layer; forming an amorphous semiconductor film on the insulating layer; performing heat treatment on the amorphous semiconductor thin film to convert the amorphous semiconductor thin film into a first semiconductor material layer; forming a second semiconductor material layer and a third semiconductor material layer on the first semiconductor material layer to form an active layer; carrying out carrier removal processing on the active layer so as to reduce the number of carriers on the side wall of the active layer; forming a second metal layer on the active layer; and performing etching treatment to divide the second metal layer into a source electrode and a drain electrode.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and in particular to a thin film transistor, a pixel array substrate, a display device and a manufacturing method thereof. Background Art

[0002] Thin Film Transistor (TFT) is a device used as a switching element to control the operation of pixels in general display screens. TFTs can be roughly divided into two types according to the material composition of their active layers: amorphous silicon (a-Si) TFTs and polycrystalline silicon (poly-Si) TFTs.

[0003] Amorphous silicon thin-film transistors have become the mainstream design for large-size panels due to their low cost and relatively simple manufacturing process. In addition, compared to polycrystalline silicon, amorphous silicon can be manufactured at lower temperatures, making it more suitable for some portable devices. However, the current amorphous silicon thin-film transistors have low carrier mobility, typically only 0.2 to 0.5 cm 2 / V×S, such component characteristics will lead to limitations in product applications. Summary of the Invention

[0004] An object of the present invention is to provide a thin film transistor, a pixel array substrate, a display device and a manufacturing method thereof, so as to solve the above-mentioned problems.

[0005] The present invention provides a thin film transistor comprising a gate, an insulating layer, an active layer, a source electrode, and a drain electrode. The insulating layer is formed on the gate electrode. The active layer is formed on the insulating layer. The source electrode is formed on one of the two end portions of the active layer. The drain electrode is formed on the other of the two end portions of the active layer. The active layer comprises a first semiconductor material layer, a second semiconductor material layer, and a third semiconductor material layer stacked in sequence. The first semiconductor material layer is formed on the insulating layer and has an ordered lattice structure; the second semiconductor material layer is formed on the first semiconductor material layer and has a disordered lattice structure; and the third semiconductor material layer is formed on both sides of the second semiconductor material layer, has a disordered lattice structure, and is doped with N-type ions. Semiconductor oxide is substantially absent at the interface between the first semiconductor material layer and the second semiconductor material layer.

[0006] The present invention provides a thin film transistor comprising a gate, an insulating layer, an active layer, a source electrode, and a drain electrode. The insulating layer is formed on the gate electrode. The active layer is formed on the insulating layer. The source electrode is formed on one of the two ends of the active layer. The drain electrode is formed on the other of the two ends of the active layer. The active layer comprises a first semiconductor material layer, a second semiconductor material layer, and a third semiconductor material layer stacked in sequence. The first semiconductor material layer is formed on the insulating layer and has an ordered lattice structure; the second semiconductor material layer is formed on the first semiconductor material layer and has a disordered lattice structure; and the third semiconductor material layer is formed on both sides of the second semiconductor material layer, has a disordered lattice structure, and is doped with N-type ions. The first semiconductor material layer is doped with Group 3A ions.

[0007] The present invention provides a thin film transistor comprising a gate, an insulating layer, an active layer, a source electrode, and a drain electrode. The insulating layer is formed on the gate electrode. The active layer is formed on the insulating layer. The source electrode is formed on one of the two ends of the active layer. The drain electrode is formed on the other of the two ends of the active layer. The active layer comprises a first semiconductor material layer, a second semiconductor material layer, and a third semiconductor material layer stacked in sequence. The first semiconductor material layer is formed on the insulating layer and has an ordered lattice structure; the second semiconductor material layer is formed on the first semiconductor material layer and has a disordered lattice structure; and the third semiconductor material layer is formed on both sides of the second semiconductor material layer, has a disordered lattice structure, and is doped with N-type ions. The thickness ratio of the second semiconductor material layer to the third semiconductor material layer is between 5:8 and 8:5.

[0008] In some embodiments of the present invention, the total thickness of the second semiconductor material layer and the third semiconductor material layer is between to between.

[0009] In some embodiments of the present invention, the thickness of the second semiconductor material layer is between to And the third semiconductor material layer has a corresponding thickness so that the sum of the thicknesses of the second semiconductor material layer and the third semiconductor material layer is The present invention proposes a method for manufacturing a thin film transistor, comprising the following steps: forming a first metal layer and an insulating layer covering the first metal layer on a substrate; forming an amorphous semiconductor thin film on the insulating layer; performing heat treatment on the amorphous semiconductor thin film to convert the amorphous semiconductor thin film into a first semiconductor material layer; performing interface cleaning treatment on the first semiconductor material layer to remove native semiconductor oxide on the surface of the first semiconductor material layer; forming second and third semiconductor material layers on the first semiconductor material layer to form an active layer; forming a second metal layer on the active layer; and performing etching treatment to expose the second semiconductor material layer in the channel region and separate the second metal layer into a source and a drain.

[0010] In some embodiments of the present invention, the manufacturing method further comprises the following step: before performing the heat treatment, performing ion implantation on the amorphous semiconductor film to implant Group 3A ions into the amorphous semiconductor film.

[0011] The present invention proposes a method for manufacturing a thin film transistor, comprising the following steps: forming a first metal layer and an insulating layer covering the first metal layer on a substrate; forming an amorphous semiconductor thin film on the insulating layer; performing heat treatment on the amorphous semiconductor thin film to convert the amorphous semiconductor thin film into a first semiconductor material layer; forming second and third semiconductor material layers on the first semiconductor material layer to form an active layer, wherein the thickness ratio of the second semiconductor material layer to the third semiconductor material layer is between 5:8 and 8:5; forming a second metal layer on the active layer; and performing etching to expose the second semiconductor material layer in the channel region and separate the second metal layer into a source and a drain.

[0012] In some embodiments of the present invention, the manufacturing method further includes the following steps: before forming the second and third semiconductor material layers, performing an interface cleaning treatment on the first semiconductor material layer to remove native semiconductor oxide on the surface of the first semiconductor material layer.

[0013] The present invention provides a pixel array substrate, which includes a thin film transistor manufactured according to the above-mentioned thin film transistor manufacturing method.

[0014] The present invention provides a display device including the pixel array substrate described above.

[0015] The present invention proposes a method for manufacturing a thin film transistor, comprising the following steps: forming a first metal layer and an insulating layer covering the first metal layer on a substrate; forming an amorphous semiconductor thin film on the insulating layer; performing ion implantation on the amorphous semiconductor thin film to implant Group 3A ions into the amorphous semiconductor thin film; performing heat treatment on the amorphous semiconductor thin film implanted with the Group 3A ions to convert the amorphous semiconductor thin film into a first semiconductor material layer; forming second and third semiconductor material layers on the first semiconductor material layer to form an active layer; forming a second metal layer on the active layer; and performing etching to expose the second semiconductor material layer in the channel region and separate the second metal layer into a source and a drain.

[0016] The present invention proposes a method for manufacturing a thin film transistor, comprising the following steps: forming a first metal layer and an insulating layer covering the first metal layer on a substrate; forming an amorphous semiconductor thin film on the insulating layer; performing heat treatment on the amorphous semiconductor thin film to convert the amorphous semiconductor thin film into a first semiconductor material layer; forming second and third semiconductor material layers on the first semiconductor material layer to form an active layer; performing carrier removal treatment on the active layer to reduce the number of carriers at the side walls of the active layer; forming a second metal layer on the active layer; and performing etching treatment to expose the second semiconductor material layer in the channel region and separate the second metal layer into a source and a drain.

[0017] In some embodiments of the present invention, the carrier removal step includes: patterning the active layer to form sidewalls; and over-etching the sidewalls. The sidewalls are uniform planes formed by continuous side surfaces of the first semiconductor material layer, the second semiconductor material layer, and the third semiconductor material layer.

[0018] In some embodiments of the present invention, the method for manufacturing a thin film transistor further includes: performing an oxidation treatment to form a silicon oxide layer on the sidewall.

[0019] In some embodiments of the present invention, the carrier removal process includes: patterning the active layer to form sidewalls; and performing ion implantation to implant Group 3A ions into the sidewalls.

[0020] The present invention provides a pixel array substrate, which includes a thin film transistor manufactured according to the above-mentioned thin film transistor manufacturing method.

[0021] The present invention provides a display device including the pixel array substrate described above.

[0022] Through the technical solutions described in the present invention, the thin-film transistor, pixel array substrate, display device, and manufacturing method thereof proposed in the embodiments of the present invention can, through a specific interface cleaning process in the thin-film transistor manufacturing process, substantially eliminate the presence of semiconductor oxides that are prone to causing bonding defects between the microcrystalline or polycrystalline silicon layer and the amorphous silicon layer in the active layer. This allows the various thin films in the active layer to be well bonded without the problem of film peeling, and effectively improves the carrier mobility and on-off ratio of the thin-film transistor. In addition, the embodiments of the present invention also propose increasing the critical voltage of the thin-film transistor by ion implanting the active layer before the heat treatment step, so that the finished product has better device characteristics. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1A and Figure 1B is a schematic diagram of a display device according to an embodiment of the present invention;

[0024] Figure 2 is a schematic cross-sectional structural diagram of a thin film transistor according to an embodiment of the present invention;

[0025] Figures 3A to 3E Flowchart of steps of a method for manufacturing a thin film transistor according to different embodiments of the present invention;

[0026] Figures 4A to 4F for Figure 3A A schematic flow chart of a method for manufacturing a thin film transistor;

[0027] Figures 5A to 5F for Figure 3B A schematic flow chart of a method for manufacturing a thin film transistor;

[0028] Figures 6A to 6F for Figure 3C A schematic flow chart of a method for manufacturing a thin film transistor;

[0029] Figure 7 SEM photographs of thin film transistors manufactured by the manufacturing method of an embodiment of the present invention and a comparative example;

[0030] Figure 8 Schematic diagram of the on-state current of a thin film transistor manufactured by the manufacturing method of an embodiment of the present invention and a comparative example;

[0031] Figure 9 is a schematic diagram of current-voltage characteristic curves of a thin film transistor manufactured according to a manufacturing method according to an embodiment of the present invention at different ion implantation concentrations;

[0032] Figure 10 is a schematic diagram of current-voltage characteristic curves of a thin film transistor with different thicknesses of active layers manufactured according to a manufacturing method according to an embodiment of the present invention;

[0033] Figure 11 is a schematic diagram of current-voltage characteristic curves of a thin film transistor manufactured through a carrier removal process according to an embodiment of the present invention and a comparative example; and

[0034] Figure 12 Schematic diagram of current-voltage characteristic curves of a thin film transistor manufactured through a carrier removal process according to an embodiment of the present invention and a comparative example. DETAILED DESCRIPTION

[0035] To make the above-mentioned objectives, features, and advantages of this technical solution more clearly understood, specific embodiments of the proposed technical solution are described in detail below with reference to the accompanying drawings. The following descriptions of the various embodiments of the technical solution of the present invention are for illustrative purposes only and are not intended to be all embodiments of the present invention or to limit the present invention to specific embodiments. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without creative effort should fall within the scope of protection of the present invention.

[0036] It should be noted that when an element is referred to as being "disposed on" another element, it may be directly on the other element or there may also be an element centered thereon. When an element is considered to be "connected to" another element, it may be directly connected to the other element or there may be an element centered thereon at the same time. The terms "vertical", "horizontal", "left", "right", "up", "down" and similar expressions used herein are only intended to indicate relative positional relationships based on the accompanying drawings, and do not limit the elements using the terms to being implemented only in a representative manner. When the absolute position of the object being described changes, the description of the relative position may also change accordingly.

[0037] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the art to which the present invention pertains. The terms used herein in the specification of the present invention are for the purpose of describing specific embodiments only and are not intended to limit the present invention. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0038] Figure 1A and Figure 1B is a schematic diagram of a display device according to an embodiment of the present invention, wherein Figure 1A is a top view diagram of the display device 100, and Figure 1B 1 is a side view of the display device 100. Figure 1A The internal components of the display device 100 are displayed in the xy plane. Figure 1BIt shows the configuration of the internal components of the display device 100 in the housing.

[0039] Please refer to Figure 1A and Figure 1B The display device 100 can be any electronic device with a display function, such as a television, a monitor, a laptop computer, or a mobile phone. It may include a display panel 110, a scan driver circuit 120, a data driver circuit 130, a connection module 140, and a control circuit 150. In this embodiment, the display panel 110 has a display area DR and a non-display area SR. The display area DR is used to display images, while the non-display area SR is an area of ​​the display panel 110 that does not display images. The non-display area SR typically surrounds the display area DR and can also be considered the border area of ​​the display device 100. The scan driver circuit 120 and the data driver circuit 130 are disposed in the non-display area SR of the display panel 110. In the figure, the scan driver circuit 120 is shown as being disposed in the non-display area SR on the left and right sides of the display panel 110, and the data driver circuit 130 is shown as being disposed in the non-display area SR on the bottom side of the display panel 110, but the present invention is not limited to this. One end of the connection module 140 is disposed on a side of the non-display region SR close to the data driving circuit 130 , and the control circuit 150 is coupled to the other end of the connection module 140 .

[0040] In terms of the electrical relationships between components, the scan driver circuit 120 is electrically connected to the display panel 110 via traces on the substrate 112. The data driver circuit 130 is electrically connected to the display panel 110 via a first transmission unit WR1 and to the flexible printed circuit board 140 via a second transmission unit WR2. Meanwhile, the control circuit 150 is electrically connected to the data driver circuit 130 via a connection module 140 and a second transmission unit WR2. The first transmission unit WR1 and the second transmission unit WR2 may be transmission lines formed on the substrate 112.

[0041] Specifically, the display panel 110 may include a substrate 112 and a pixel array 114 located in a display region DR. The pixel array 114 is disposed on the substrate 112 and is arranged, for example, in an m×n array, i.e., m columns and n rows, where m and n can be natural numbers selected according to design requirements and are not limited thereto. Pixels in the same column of the pixel array 114 correspond to the same scan line, and pixels in the same row correspond to the same data line. In this embodiment, the pixel array 114 may be electrically connected to the scan driving circuit 120 via scan lines to receive scan signals, and may be electrically connected to the data driving circuit 130 via data lines and a first transmission unit WR1 to receive data driving signals provided by the data driving circuit 130. The data driving circuit 130 provides data driving signals in conjunction with the activation timing of the pixel array 114, so that the pixel array 114 adjusts the light passing therethrough according to the data driving signals to present a corresponding image in the display region DR. In this embodiment, the display panel 110 may be various types of display panels, such as LCD, LED, OLED, mini-LED, or micro-LED, but the present invention is not limited thereto.

[0042] The scan driver circuit 120 is configured to generate scan signals that turn on / enable pixels row by row based on timing control signals. In this embodiment, the scan driver circuit 120 is illustrated as two configurations, one for enabling pixels in odd rows and the other for enabling pixels in even rows. The scan driver circuit 120 on the left side includes scan units 121_1, 121_3, ..., 121_m-1, respectively, connected to odd-numbered scan lines, while the scan driver circuit 120 on the right side includes scan units 121_2, 121_4, and 121_m, respectively, connected to even-numbered scan lines. However, the present invention is not limited to this embodiment. In this embodiment, scan unit 121_x represents any one of the scan units 121_1, 121_3, ..., 121_m-1 on the left side, and scan unit 121_y represents any one of the scan units 121_2, 121_4, and 121_m on the right side. In other words, x may be any odd number less than m, and y may be any even number less than or equal to m, where m is an even number, but the present invention is not limited thereto.

[0043] The data driver circuit 130 is configured to generate a drive signal for driving the pixel array 114 based on the data control signal. While the figures of this embodiment illustrate a single data driver circuit 130 for illustrative purposes, the present invention is not limited thereto. In some embodiments, the data driver circuit 130 may be integrated into multiple driver chips, where the multiple driver chips can collaboratively drive pixels in different portions / regions of the pixel array 114.

[0044] The connection module 140 is used to provide a signal transmission path between the data driving circuit 130 and the control circuit 150 , so that the data control signal generated by the control circuit 150 can be transmitted to the data driving circuit 130 through the connection module 140 and the second transmission part WR2 .

[0045] The pixel array 114 of the display panel 110 includes a plurality of thin film transistors. These thin film transistors are turned on or off in response to received signals to control the operation of corresponding pixels, thereby achieving the aforementioned effect of adjusting the light passing therethrough according to the data drive signal to display the corresponding image in the display area DR.

[0046] In some embodiments, the thin film transistor may be configured as follows: Figure 2 As shown, Figure 2 FIG is a schematic diagram of a cross-sectional structure of a thin film transistor according to an embodiment of the present invention. Figure 2 The thin film transistor 200 includes a gate 210, an insulating layer 220, an active layer 230, a source electrode 240S, and a drain electrode 240D. The gate 210, the insulating layer 220, and the active layer 230 are stacked in sequence from bottom to top (based on the direction of the figure). The source electrode 240S and the drain electrode 240D are respectively formed on the two ends of the active layer 230, and the middle area of ​​the active layer 230 is etched to form a channel region CHA.

[0047] The gate 210, source 240S, and drain 240D may be formed of metals such as molybdenum (Mo), aluminum (Al), titanium (Ti), copper (Cu), or stacked combinations of these metals, but the present invention is not limited thereto. The insulating layer 220 may be a non-metallic dielectric material such as silicon dioxide (SiOx), silicon nitride (SiNx), or stacked combinations of these materials, but the present invention is also not limited thereto.

[0048] The active layer 230 of this embodiment has a three-layer stacked structure at both ends, including a first semiconductor material layer 231, a second semiconductor material layer 232, and a third semiconductor material layer stacked in order from bottom to top. The first semiconductor material layer 231 is formed on the insulating layer 220 and has an ordered lattice structure, such as microcrystalline silicon or polycrystalline silicon. The second semiconductor material layer 232 is formed on the first semiconductor material layer 231 and has a disordered lattice structure, such as amorphous silicon (a-Si). The third semiconductor material layer 233 is formed on both sides of the second semiconductor material layer 232, wherein the third semiconductor material layer 233 has a disordered lattice structure and is doped with N-type ions. In other words, at both ends of the active layer 230, the second semiconductor material layer 232 and the third semiconductor material layer 233 can both be made of amorphous silicon, the difference being that the N-type ion concentration in the third semiconductor material layer 233 is higher than that in the second semiconductor material layer 232.

[0049] On the other hand, the thickness of the active layer 230 within the channel region CHA is thinner than the thickness outside the channel region CHA (i.e., at both ends). Furthermore, the active layer 230 within the channel region CHA is etched to remove the third semiconductor material layer 233, thereby exposing the second semiconductor material layer 232. In other words, only a two-layer structure of the first semiconductor material layer 231 and the second semiconductor material layer 232 exists within the channel region CHA.

[0050] The thin film transistor 200 having the active layer 230 composed of the first to third semiconductor material layers 231 to 233 has a higher carrier mobility than the traditional amorphous silicon thin film transistor. Under the structure of this embodiment, the carrier mobility can be increased to 6 to 8 cm 2 / V×SM; In some embodiments, when the drain-source voltage is 10V, the on-state current can reach 10 -5 A, which is more than 10 times that of traditional amorphous silicon thin-film transistors.

[0051] In addition, in this embodiment, most of the native semiconductor oxide (e.g., SiOx) between the first semiconductor material layer 231 and the second semiconductor material layer 232 is removed, so that substantially no semiconductor oxide exists at the interface between the first semiconductor material layer 231 and the second semiconductor material layer 232. Therefore, the first semiconductor material layer 231 and the second semiconductor material layer 232 can be well bonded without the problem of film peeling, and the device characteristics of the thin film transistor 200, such as carrier mobility and on / off ratio, can be effectively improved.

[0052] It should be noted here that although the carrier mobility of the thin film transistor 200 is significantly improved compared to the traditional amorphous silicon thin film transistor, the critical voltage may be relatively low. In some embodiments, in order to further optimize the electrical properties of the thin film transistor 200, the first semiconductor material layer 231 can also be doped with 3A group ions (i.e., boron group) by ion implantation during the manufacturing process, wherein the doped 3A group ions will form covalent bonds with the semiconductor material in the first semiconductor material layer 231 and provide holes to move the current-voltage characteristic curve of the thin film transistor to the right, thereby increasing the critical voltage and effectively improving the problem of low critical voltage. In some embodiments, the ion concentration of the 3A group ions injected into the first semiconductor material layer 231 can be between 10 12 ~10 13 ions / cm 3 In the embodiment of implanting boron ions, the ion concentration may be, for example, 2×10 12 , 4×10 12 or 6×10 12 , and the injection energy is, for example, 10-20 keV, and the cavity is, for example, at room temperature, but the present invention is not limited thereto.

[0053] In addition, generally have Figure 2 Since the sidewalls of the active layer of the thin film transistor with a structure have more broken links and carriers after etching, the leakage current (Ioff) may be higher than that of traditional amorphous silicon thin film transistors. In the case of high leakage current, the display using the thin film transistor will have problems such as poor contrast, whiteness, flickering, etc. when displaying the picture. In some embodiments, in order to further optimize the electrical properties of the thin film transistor 200, the active layer 230 can be subjected to a carrier removal treatment during formation to reduce the number of free ions on the sidewalls of the active layer 230, thereby reducing the leakage current at the sidewalls.

[0054] The source electrode 240S and the drain electrode 240D are respectively formed on both ends of the active layer 230 and extend from the side of the active layer 230 to cover a portion of the insulating layer 220. More specifically, the source electrode 240S and the drain electrode 240D respectively contact the top of the third semiconductor material layer 233 (i.e., the side away from the second semiconductor material layer 232) and the sidewalls of the first semiconductor material layer 231, the second semiconductor material layer 232, and the third semiconductor material layer 233 (i.e., the side of the active layer 230 away from the channel area CHA), and extend through the sidewalls to contact the top of the insulating layer 220 (i.e., the side away from the gate 210).

[0055] In some embodiments, the thin film transistor 200 may further include a functional layer 250 covering the surface of the device, wherein the functional layer 250 may be formed, for example, on the source electrode 240S, the drain electrode 240D, and a portion or all of the exposed surface of the active layer 230. In some embodiments, the functional layer 250 may be a protective film made of silicon nitride (SiN), for example, but the present invention is not limited thereto.

[0056] It should also be noted that because the signal transmission impedance between the source 240S and the drain 240D of the thin-film transistor 200 is relatively large, when a low voltage (e.g., less than 1V) is applied to the drain-source, the on-current of the thin-film transistor 200 may actually be lower than that of a traditional amorphous silicon thin-film transistor. In other words, when the drain-source voltage (Vds) of the thin-film transistor 200 is low, its on-off ratio may be lower than that of a traditional amorphous silicon thin-film transistor.

[0057] In some embodiments, the problem of low drain-source on-state current at low voltages can be improved by adjusting the thickness ratio of the second semiconductor material layer 232 and the third semiconductor material layer 233 during the manufacturing process. For example, when the total thickness of the second semiconductor material layer 232 and the third semiconductor material layer 233 is fixed, the thickness ratio can be between 5:8 and 8:5.

[0058] In some embodiments, the total thickness of the second semiconductor material layer 232 and the third semiconductor material layer 233 is approximately The thickness of the second semiconductor material layer 232 is and In the case of, the thickness of the third semiconductor material layer 233 can be designed as follows: and This allows the on-state current to be maintained even at low source-drain voltages. This section will be further explained with experimental results.

[0059] Figure 3A is a flow chart of a method for manufacturing a thin film transistor according to an embodiment of the present invention, wherein Figure 3A The manufacturing method can be used to manufacture Figure 2 The thin film transistor 200 described in the embodiment. Figures 4A to 4F To illustrate the manufacturing process of the thin film transistor 200, Figures 4A to 4F In accordance with Figure 3A Schematic diagram of a process for manufacturing a thin film transistor.

[0060] Please refer to Figure 3A and Figure 4AFirst, a first metal layer 210 and an insulating layer 220 covering the first metal layer 210 are formed on the substrate SUB (step S110 ), wherein the first metal layer 210 is used as a gate of the thin film transistor 200 .

[0061] Next, please refer to Figure 3A 、 Figure 4B and Figure 4C , an amorphous semiconductor film 231p is formed on the insulating layer 220 (step S120), and the amorphous semiconductor film 231p is heat-treated to convert the amorphous semiconductor film 231p into a first semiconductor material layer 231 having an orderly arranged lattice structure (step S130).

[0062] In some embodiments, the amorphous semiconductor film 231p is, for example, amorphous silicon. The heat treatment may be, for example, an excimer laser annealing (ELA) technique in which an excimer laser is irradiated on the amorphous silicon to transform the amorphous silicon into microcrystalline silicon or polycrystalline silicon (i.e., the first semiconductor material layer 231) having an orderly lattice structure, but the present invention is not limited thereto.

[0063] After the amorphous semiconductor film 231 p is converted into the first semiconductor material layer 231 , this embodiment further performs an interface cleaning process on the first semiconductor material layer 231 to remove the native semiconductor oxide SO on the surface of the first semiconductor material layer 231 (step S140 ).

[0064] In some embodiments, the interface cleaning process may be performed using a surface treatment process such as wet etching (e.g., chemical treatment) or dry etching (e.g., plasma treatment). In wet etching, the interface cleaning process may be performed using a chemical solution that is corrosive to semiconductor oxide SO, such as a diluted buffered oxide etchant (BOE), diluted hydrofluoric acid (HF), or a mixture of hydrofluoric acid and ammonium fluoride (NH4F), but the present invention is not limited thereto.

[0065] In the embodiment of using a corrosive chemical solution for interface cleaning, the chemical solution can be diluted to an etching rate of 5 to 10% for semiconductor oxide SO. The interface cleaning process is performed for 5 to 30 seconds to prevent the insulating layer 220 and / or the first semiconductor material layer 231 from being corroded while removing the semiconductor oxide SO. In some embodiments, if the chemical solution is HF or BOE, the dilution concentration may be, for example, 1% to 2%, but the present invention is not limited thereto.

[0066] Please refer to Figure 3A and Figure 4D After the interface cleaning process is completed, a second semiconductor material layer 232 and a third semiconductor material layer 233 are formed on the first semiconductor material layer 231 (step S150). The first to third semiconductor material layers 231-233 stacked in sequence from bottom to top constitute the active layer 230 of the thin film transistor 200. In this embodiment, the second semiconductor material layer 232 is composed of amorphous silicon, for example, and the third semiconductor material layer 233 is composed of n-doped amorphous silicon, for example, but the present invention is not limited to this.

[0067] In some embodiments, to ensure that the semiconductor oxide SO removed in step S140 does not regenerate during the manufacturing process, the time interval between step S140 and step S150 needs to be set to less than 1 hour. In other words, the steps of forming the second and third semiconductor material layers 232-233 need to be performed within one hour after completing the interface cleaning process.

[0068] In some embodiments, the second semiconductor material layer 232 is formed to a thickness between to and the third semiconductor material layer 233 is formed with a corresponding thickness so that the total thickness of the second semiconductor material layer 232 and the third semiconductor material layer 233 is approximately between to In some preferred embodiments, the thickness of the second semiconductor material layer 232 is between to and the third semiconductor material layer 233 is formed with a corresponding thickness so that the total thickness of the second semiconductor material layer 232 and the third semiconductor material layer 233 is approximately However, the present invention is not limited thereto.

[0069] Please refer to Figure 3A and Figure 4E After the active layer 230 is formed, the active layer 230 may be patterned, and a second metal layer 240 may be formed on the patterned active layer 230 (step S160 ).

[0070] Please refer to Figure 3A and Figure 4F After forming the second metal layer 240, the element is etched to expose the second semiconductor material layer 232 of the channel region CHA, and the second metal layer 240 is separated into two parts, left and right, by the channel region CHA (step S170), wherein the second metal layer 240 on the left serves as the source 240S of the thin film transistor 200, and the second metal layer 240 on the right serves as the drain 240D of the thin film transistor 200.

[0071] In some embodiments, after step S170 , a functional layer 250 covering the source 240S, the drain 240D and the channel region CHA may be further formed on the device according to design or device requirements.

[0072] Figure 3B is a flow chart of a method for manufacturing a thin film transistor according to another embodiment of the present invention, wherein Figure 3B The manufacturing method can be used to manufacture Figure 2 The thin film transistor 200 described in the embodiment. Figures 5A to 5F To illustrate the manufacturing process of the thin film transistor 200, Figures 5A to 5F In accordance with Figure 3B Schematic diagram of a process for manufacturing a thin film transistor.

[0073] Please refer to Figure 3B and Figure 5A First, a first metal layer 210 and an insulating layer 220 covering the first metal layer 210 are formed on the substrate SUB (step S210 ), wherein the first metal layer 210 is used as a gate of the thin film transistor 200 .

[0074] Please refer to Figure 3B and Figure 5B An amorphous semiconductor film 231p is formed on the insulating layer 220 (step S220), and ion implantation is performed on the amorphous semiconductor film 231p (step S230) to implant Group 3A ions into the amorphous semiconductor film 231p.

[0075] Next, please refer to Figure 3B and Figure 5C The amorphous semiconductor film 231p implanted with the 3A group ions is thermally treated to convert the amorphous semiconductor film 231p into the first semiconductor material layer 231 (step S240).

[0076] In other words, the manufacturing method of this embodiment is similar to the above-mentioned method before heat treatment. Figure 3A The main difference between the embodiments is that this embodiment performs step S230 of ion implantation on the amorphous semiconductor film to dope Group 3A ions into the amorphous semiconductor film 231 p .

[0077] In some embodiments, the amorphous semiconductor film 231p is, for example, amorphous silicon, and the implanted material may be, for example, boron ions (B+). The heat treatment may be, for example, excimer laser annealing (ELA) of amorphous silicon doped with boron ions by irradiating an excimer laser to transform the amorphous silicon into microcrystalline silicon or polycrystalline silicon (i.e., the first semiconductor material layer 231) having an ordered lattice structure, but the present invention is not limited thereto.

[0078] Please refer to Figure 3B and Figure 5D After the heat treatment is completed, a second semiconductor material layer 232 and a third semiconductor material layer 233 are formed on the first semiconductor material layer 231 (step S250). The first to third semiconductor material layers 231-233 stacked in sequence from bottom to top constitute the active layer 230 of the thin film transistor 200. In this embodiment, the second semiconductor material layer 232 is composed of amorphous silicon, for example, and the third semiconductor material layer 233 is composed of n-doped amorphous silicon, for example, but the present invention is not limited to this.

[0079] Please refer to Figure 3B and Figure 5E After the active layer 230 is formed, the active layer 230 may be patterned, and a second metal layer 240 may be formed on the patterned active layer 230 (step S260 ).

[0080] Please refer to Figure 3B and Figure 5F After forming the second metal layer 240, the element is etched to expose the second semiconductor material layer 232 of the channel region CHA, and the second metal layer 240 is separated into two parts, left and right, by the channel region CHA (step S270), wherein the second metal layer 240 on the left serves as the source 240S of the thin film transistor 200, and the second metal layer 240 on the right serves as the drain 240D of the thin film transistor 200.

[0081] In some embodiments, after step S270 , a functional layer 250 covering the source 240S, the drain 240D and the channel region CHA may be further formed on the device according to design or device requirements.

[0082] Compared to conventional thin film transistor manufacturing processes, the purpose of step S230 in this embodiment is to adjust the threshold voltage value rather than to serve as a region for configuring the source / drain. Therefore, the ion concentration of the implanted / doped layer does not need to be too high, and there is no need to perform a rapid thermal annealing (RTA) process on the first semiconductor layer 231 again to activate the ions, thereby effectively simplifying the complexity of the manufacturing process.

[0083] Figure 3C A flowchart of a method for manufacturing a thin film transistor according to another embodiment of the present invention is shown in FIG. Figure 3C The manufacturing method can be used to manufacture Figure 2 The thin film transistor 200 described in the embodiment. Figures 6A to 6F To illustrate the manufacturing process of the thin film transistor 200, Figures 6A to 6F In accordance with Figure 3C Schematic diagram of a process for manufacturing a thin film transistor.

[0084] Please refer to Figure 3C 、 Figure 6A and Figure 6B First, a first metal layer 210 and an insulating layer 220 covering the first metal layer 210 are formed on a substrate SUB (step S310), wherein the first metal layer 210 is used as the gate of the thin film transistor 200. Next, an amorphous semiconductor film 231p is formed on the insulating layer 220 (step S320), and the amorphous semiconductor film 231p is heat-treated to transform the amorphous semiconductor film 231p into a first semiconductor material layer 231 having an orderly arranged lattice structure (step S330).

[0085] In some embodiments, the amorphous semiconductor film 231p is, for example, amorphous silicon. The heat treatment may be, for example, an excimer laser annealing (ELA) technique in which an excimer laser is irradiated on the amorphous silicon to transform the amorphous silicon into microcrystalline silicon or polycrystalline silicon (i.e., the first semiconductor material layer 231) having an orderly lattice structure, but the present invention is not limited thereto.

[0086] Please refer to Figure 3C and Figure 6CAfter the heat treatment is completed, a second semiconductor material layer 232 and a third semiconductor material layer 233 are formed on the first semiconductor material layer 231 (step S340). The first to third semiconductor material layers 231-233 stacked in sequence from bottom to top constitute the active layer 230 of the thin film transistor 200. In this embodiment, the second semiconductor material layer 232 is composed of amorphous silicon, for example, and the third semiconductor material layer 233 is composed of n-doped amorphous silicon, for example, but the present invention is not limited to this.

[0087] Please refer to Figure 3C and Figure 6D After the active layer 230 is formed, a carrier removal process may be performed on the active layer 230 (step S350 ).

[0088] In some embodiments, the carrier removal step S350 may include, for example, first patterning the active layer 230 to form sidewalls SW of the active layer 230, wherein the sidewalls SW are, for example, formed of a uniform, continuous plane of the first semiconductor material layer 231, the second semiconductor material layer 232, and the third semiconductor material layer 233. After the patterning is completed, the sidewalls SW of the patterned active layer 230 are further subjected to over-etching or ion implantation to reduce carrier generation on the sidewalls SW of the active layer 230.

[0089] In some embodiments, the normal direction of the sidewall SW is not parallel to the normal direction of the substrate SUB; in some embodiments, the angle between the normal direction of the sidewall SW and the normal direction of the substrate SUB is less than 45 degrees, but the present invention is not limited thereto.

[0090] In some embodiments, after the patterning process is completed, the carrier removal process step S350 may further include an oxidation process for the sidewall SW, wherein the oxidation process may be performed by introducing oxygen gas, and by properly controlling the time of introducing oxygen gas, a uniform and thin silicon oxide layer is formed on the surface of the sidewall SW, thereby further reducing the leakage current at the sidewall SW. In some embodiments, the thickness of the silicon oxide layer formed on the surface of the sidewall SW may be, for example, between to However, the present invention is not limited thereto.

[0091] Please refer to Figure 3C and Figure 6E After the active layer 230 is formed, the active layer 230 may be patterned, and a second metal layer 240 may be formed on the patterned active layer 230 (step S360 ).

[0092] Please refer to Figure 3C and Figure 6FAfter forming the second metal layer 240, the element is etched to expose the second semiconductor material layer 232 of the channel area CHA, and the second metal layer 240 is separated into two parts, left and right, by the channel area CHA (step S370), wherein the second metal layer 240 on the left serves as the source 240S of the thin film transistor 200, and the second metal layer 240 on the right serves as the drain 240D of the thin film transistor 200.

[0093] In some embodiments, after step S370 , a functional layer 250 covering the source 240S, the drain 240D and the channel region CHA may be further formed on the device according to design or device requirements.

[0094] Compared with the conventional thin film transistor manufacturing process, the purpose of step S350 in this embodiment is to reduce the number of carriers at the sidewall SW of the active layer 230 , thereby effectively reducing the leakage current of the thin film transistor 200 , thereby effectively improving the on / off ratio of the thin film transistor 200 .

[0095] Specifically, in the embodiment of step S350, if a process of patterning followed by over-etching is adopted, the total time of the patterning process plus the over-etching process may be, for example, 60 seconds to 130 seconds, but the present invention is not limited thereto.

[0096] It should be noted that in the above-mentioned process of performing over-etching after patterning, the over-etching step can be achieved by extending the etching time of the patterning process. In other words, from the perspective of actual manufacturing process, the patterning process and the over-etching process can be a continuous process that cannot be clearly distinguished. The focus of the over-etching process is to further etch the sidewalls SW after completing the patterning of the active layer 230 to reduce the number of carriers. This effect is achieved by appropriately extending the etching time. Therefore, although it may not be possible to actually distinguish the difference in the step process from the appearance, the extended etching time can be used to determine whether the over-etching process is performed.

[0097] In some embodiments, if the carrier removal process step S350 is a process of first patterning the active layer 230 to form a sidewall SW in the active layer 230, and then performing ion implantation on the sidewall SW, the ion implantation can be, for example, implanting 3A group ions (such as boron ions) with a light dose and light energy, so that the 3A group ions provide holes in the active layer 230 to obtain free electrons, thereby reducing the leakage current at the sidewall SW.

[0098] In some embodiments, during the process of ion implantation into the sidewall SW, the implanted ion concentration may be between 5×10 12 ~5×10 13 ions / cm 3The implantation energy may be, for example, 10-20 keV and performed in a room temperature chamber, but the present invention is not limited thereto.

[0099] Figure 3D A flowchart of a method for manufacturing a thin film transistor according to another embodiment of the present invention is shown in FIG. Figure 3D The manufacturing method can be used to manufacture Figure 2 The thin film transistor 200 according to the embodiment.

[0100] Please refer to Figure 3D , this embodiment and the aforementioned Figure 3A and / or Figure 3B The embodiment is substantially the same as Figure 3A The difference between the embodiments is that, before the heat treatment step S440, the embodiment further performs the following steps: Figure 3B The ion implantation operation described in step S230 causes the first semiconductor material layer to be doped with 3A group ions. Figure 3B The difference between the embodiments is that, after the heat treatment step S440, the embodiment further performs the following steps: Figure 3A The interface cleaning step S450 described in step S140 is performed to remove the native semiconductor oxide on the first semiconductor material layer.

[0101] In addition, the relevant description of step S410 of this embodiment can refer to the aforementioned Figure 3A Step S110 and Figure 3B Step S210 of this embodiment, the relevant description of step S420 can refer to the aforementioned Figure 3A Step S120 and Figure 3B Step S220 of this embodiment, the relevant description of step S430 can refer to the aforementioned Figure 3B Step S230 of this embodiment, the relevant description of step S440 can refer to the aforementioned Figure 3A Step S130 and Figure 3B Step S240 of this embodiment, the relevant description of step S450 can refer to the aforementioned Figure 3A Step S140 of this embodiment, and the relevant description of steps S460 to S480 of this embodiment can refer to the aforementioned Figure 3A Steps S150 to S170 and Figure 3B Therefore, the repeated parts are not described again here.

[0102] More specifically, compared to the above Figure 3A and Figure 3BAs for the manufacturing method process, not only is an ion implantation process performed (step S430) to improve the critical voltage characteristics, but also an interface cleaning process (step S450) is performed on the amorphous semiconductor film (231p) doped with 3A group ions after it is converted into a polycrystalline or microcrystalline first semiconductor material layer (231) to improve the bonding strength between the first semiconductor material layer and the second semiconductor material layer, so that the overall device characteristics of the thin film transistor are better.

[0103] Figure 3E A flowchart of a method for manufacturing a thin film transistor according to another embodiment of the present invention is shown in FIG. Figure 3E The manufacturing method can be used to manufacture Figure 2 The thin film transistor 200 according to the embodiment.

[0104] Please refer to Figure 3E , this embodiment and the aforementioned Figure 3D The embodiment is substantially the same as Figure 3D The difference between the embodiments is that, before the step S580 of forming the second metal layer, the embodiment further performs the following steps: Figure 3C The carrier removal process described in step S350 reduces the number of carriers on the sidewall of the active layer.

[0105] In addition, the relevant descriptions of steps S510-S560 of this embodiment can refer to the aforementioned Figure 3D Steps S410-S460 of this embodiment, and the relevant description of step S570 of this embodiment can refer to the aforementioned Figure 3C The relevant description of step S350 and steps S580 and S590 of this embodiment can refer to the aforementioned Figure 3C Therefore, the repeated parts are not repeated here.

[0106] More specifically, compared to the above Figure 3C As for the manufacturing method process, after the active layer is further patterned, the side wall of the active layer is further subjected to carrier removal treatment (step S570) to reduce the number of carriers at the side wall of the active layer, thereby reducing the leakage current of the thin film transistor and further improving the switching ratio.

[0107] Figure 7 The SEM photos of the thin film transistor manufactured according to the manufacturing method of the embodiment of the present invention and the comparative example are shown in FIG. Figure 7 The comparative example on the left is a thin film transistor manufactured by a preparation process that does not include the interface cleaning step S140, which includes a gate 210', an insulating layer 220', and an active layer composed of a first semiconductor layer to a third semiconductor layer 231'-233'. As can be seen from the experimental comparison results, the above-mentioned Figure 3A Compared with the comparative example, the thin film transistor manufactured by the manufacturing method does not have the problem of film peeling between the first semiconductor material layer 231 and the second semiconductor material layer 232.

[0108] It should be noted here that Figure 2 、 Figures 4A to 4F 、 Figures 5A to 5F as well as Figures 6A to 6F The illustrated thin film transistor 100 / 200 only schematically illustrates the relative configuration / stack relationship between the layers, and does not indicate the actual thickness ratio between the layers. In other words, depending on the actual manufacturing process and application, the thickness of the layers may not have the same ratio as shown in the drawings. For example, Figure 2 、 Figures 4A to 4F by Figures 5A to 5F In the active layer 230, although the thickness of the second semiconductor material layer 232 is shown to be greater than that of the first semiconductor layer 231 and the third semiconductor layer 233, in other embodiments or practical applications (such as Figure 7 In another embodiment, the thickness of the second semiconductor material layer 232 may also be smaller than that of the first semiconductor layer 231 and the third semiconductor layer 233, but the present invention is not limited thereto.

[0109] Figure 8 Schematic diagram of the conduction current of the thin film transistor experimental example and comparative example manufactured according to the manufacturing method of the embodiment of the present invention. Figure 8 , it can be seen from the experimental results in the figure that Figure 3A The on / off ratio of the thin film transistor experimental example manufactured by the step process is significantly higher than the on / off ratio of the comparative example which does not undergo the interface cleaning process (step S140).

[0110] In addition, in some experimental cases, Figure 3A The carrier mobility of the thin film transistor manufactured by the process can reach 11.12cm 2 / V×S. In contrast, in the comparative example without the interface cleaning process (step S140), the carrier mobility may be affected by the defects and is only about 1.29 cm 2 / V×S.

[0111] Figure 9 The current-voltage characteristic curves of the thin film transistor manufactured according to the manufacturing method of the embodiment of the present invention at different ion implantation concentrations are shown. Figure 9It can be seen from the characteristic curve that the critical voltage of the thin film transistor increases as the concentration of the 3A group ions injected in step S230 / S330 of the above-mentioned manufacturing method increases. In summary, the thin film transistor, pixel array substrate, display device and manufacturing method thereof proposed in the embodiment of the present invention can be processed through a specific interface cleaning process in the manufacturing process of the thin film transistor, so that there is substantially no semiconductor oxide that is easy to cause bonding defects between the microcrystalline or polycrystalline silicon layer (such as the first semiconductor material layer) and the amorphous silicon layer (such as the second semiconductor material layer) in the active layer, thereby allowing the various thin films in the active layer to be well bonded without the problem of film peeling, and the component characteristics such as the carrier mobility and switching ratio of the thin film transistor 200 can be effectively improved. In addition, the embodiment of the present invention also proposes to increase the critical voltage of the thin film transistor by performing ion implantation on the active layer before the heat treatment step, so that the finished product can have better component characteristics.

[0112] Figure 10 The current-voltage characteristic curves of the active layer of the thin film transistor manufactured according to the manufacturing method of the embodiment of the present invention at different thicknesses are shown in FIG. Figure 9 The graph shows the relationship between the on-state current and the gate voltage when a drain-source voltage of 0.5V is applied under four different thickness combinations of the active layer (a) to (d). Figure 9 It can be found from the characteristic curve that the total thickness of the second semiconductor material layer 232 and the third semiconductor material layer 233 is fixed to In the case of (Combination (d)) dropped to (Combination (a)) and the thickness of the third semiconductor material layer 233 corresponds to Rise to The on-state current will increase significantly. Therefore, through the above experimental results, it can be found that even at a low voltage of 0.5V for the drain-source voltage, the on-state current can still reach about 10 - 6 A, and the cut-off current will not be significantly affected, so the on-off ratio can be effectively improved.

[0113] Figure 11 The current-voltage characteristic curves of the thin film transistor manufactured by the carrier removal process and the comparative example, wherein the carrier removal process is implemented by patterning, over-etching and oxidation. Figure 11 From the experimental comparison results, it can be seen that the thin film transistor experimental example produced by the carrier removal step S350 has a better off-current (Ioff) characteristic than the comparative example (which does not adopt step S350), that is, the leakage current is lower.

[0114] Figure 12 The current-voltage characteristic curves of the thin film transistor manufactured by the carrier removal process and the comparative example, wherein the carrier removal process is implemented by patterning and ion implantation. Figure 12 From the experimental comparison results, it can be seen that the thin film transistor experimental example manufactured by the carrier removal step S350 has obviously better cut-off current characteristics compared with the comparative example (step S350 is not used).

[0115] Although the present invention has been disclosed using the above-mentioned embodiments, they are not intended to limit the present invention. Any person skilled in the art may make various changes and modifications to the above-mentioned embodiments without departing from the spirit and scope of the present invention. These changes and modifications still fall within the technical scope protected by the present invention. Therefore, the scope of protection of the present invention shall be based on the definition of the claims.

Claims

1. A method for manufacturing a thin film transistor, characterized in that: Include: forming a first metal layer and an insulating layer covering the first metal layer on a substrate; forming an amorphous semiconductor thin film on the insulating layer; performing a heat treatment on the amorphous semiconductor film to convert the amorphous semiconductor film into a first semiconductor material layer; forming a second semiconductor material layer and a third semiconductor material layer on the first semiconductor material layer to form an active layer; performing a carrier removal process on the active layer to reduce the number of carriers at the sidewalls of the active layer; forming a second metal layer on the active layer; as well as An etching process is performed to expose the second semiconductor material layer in the channel region and separate the second metal layer into a source electrode and a drain electrode.

2. The method for manufacturing a thin film transistor according to claim 1, wherein: The steps of the carrier removal process include: performing patterning on the active layer to form sidewalls; and The sidewalls are overetched.

3. The method for manufacturing a thin film transistor according to claim 2, wherein: The sidewall is a uniform plane formed by continuous side surfaces of the first semiconductor material layer, the second semiconductor material layer, and the third semiconductor material layer.

4. The method for manufacturing a thin film transistor according to claim 2, wherein: Also includes: An oxidation process is performed to form a silicon oxide layer on the sidewalls.

5. The method for manufacturing a thin film transistor according to claim 1, wherein: The steps of the carrier removal process include: performing patterning on the active layer to form sidewalls; and Ion implantation is performed to implant Group 3A ions into the sidewalls.

6. A pixel array substrate, characterized in that: Include: A thin film transistor manufactured by the manufacturing method according to any one of claims 1 to 5.

7. A display device, characterized in that: Include: The pixel array substrate as claimed in claim 6.

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