Multi-functional integrated motor control system for hybrid new energy vehicle

Abstract

The application discloses a multifunctional integrated motor control system for a hybrid new energy vehicle, which comprises a microprocessor chip and an oil pump motor power circuit, a gear shifting motor power circuit, a power generation motor power circuit, a driving motor power circuit, an Elock circuit and a power supply circuit which are electrically connected with the microprocessor chip respectively. The microprocessor chip controls the oil pump motor through the oil pump motor power circuit, and controls the gear shifting motor through the gear shifting motor power circuit. The multifunctional integrated motor control system for the hybrid new energy vehicle uses a BGA292 package MCU main operator chip, realizes four motor control functions and power coupling module control functions, and provides a high reliability hardware basis with a cost performance advantage for a hybrid power system new energy vehicle electric drive controller.

Description

Technical Field

[0001] This invention belongs to the field of motor controller technology, specifically relating to a multi-functional integrated motor control system for hybrid new energy vehicles. Background Technology

[0002] All-in-one electric drive inverters for new energy vehicles can significantly reduce the application costs of connectors, wiring harnesses, and other components in the vehicle, greatly enhancing product competitiveness and are increasingly being adopted in vehicle architecture design. Generally, in all-in-one electric drive inverters, the main arithmetic unit chip with different pin resources is selected based on the number of integrated functions. For dual-controller systems, packages with abundant pin resources, such as BGA516, are typically chosen. However, larger chip sizes lead to higher product prices and increase the risk of BGA solder cracking during vibration.

[0003] Currently, the integrated electric drive controller architecture design for new energy vehicles generally uses an arithmetic unit chip with more pin resources to achieve multi-functional control. This current approach has the following significant drawbacks: 1) The main arithmetic unit chip is expensive, and in multi-functional integrated applications, it needs to be paired with a variety of peripheral circuits; the overall system cost is too high and it is not competitive; the larger the package of the arithmetic unit chip, the higher the risk of cracking of the corner BGA solder joints in hybrid electric vehicle applications.

[0004] 2) The functional safety objectives of traditional generator motors are not clearly defined, resulting in the same functional safety requirements as drive motors, which occupy more resources; and miniaturized main arithmetic unit chips cannot be used.

[0005] 3) Traditional new energy vehicle motors are directly connected to the wheels, and towing is not allowed when the vehicle breaks down, otherwise the motor will overheat and burn out during the towing process.

[0006] 4) Traditional multi-functional integrated controllers do not include BLDC control functions. Independent oil pump control and independent shift motor control will increase the application costs of vehicle connectors, wiring harnesses, and fixing.

[0007] 5) The multi-function integrated controller in traditional hybrid vehicles does not include a high-voltage backup power supply. In the application of the multi-function integrated controller, if the power line becomes unstable, it will affect many functions.

[0008] Therefore, further improvements will be made to address the aforementioned issues. Summary of the Invention

[0009] The main objective of this invention is to provide a multi-functional integrated motor control system for hybrid new energy vehicles. It uses a BGA292 packaged MCU main arithmetic unit chip to realize four motor control functions and power coupling module control functions, providing a cost-effective and highly reliable hardware foundation for the electric drive controller of hybrid new energy vehicles.

[0010] Another objective of this invention is to provide a multifunctional integrated motor control system for hybrid new energy vehicles. Based on a BGA292 packaged main arithmetic unit chip, it implements ASIL-C functional safety target drive motor control functions, and ASIL-B functional safety target generator motor, oil pump motor, and gear shift motor control functions. The design uses an SBC chip to power the system control circuit and performs functional safety verification on the MCU.

[0011] Another objective of this invention is to provide a multi-functional integrated motor control system for hybrid new energy vehicles. The system incorporates a power coupling module control function, which disconnects the motor from the wheel power in cases of vehicle malfunction or when towing is required, thus preventing other problems from occurring.

[0012] Another objective of this invention is to provide a multi-functional integrated motor control system for hybrid new energy vehicles. The SBC and power supply circuit use a 12V battery power supply and a parallel high-voltage power supply output power supply to ensure system reliability to the greatest extent.

[0013] To achieve the above objectives, the present invention provides a multifunctional integrated motor control system for hybrid new energy vehicles, comprising a microprocessor chip and an oil pump motor power circuit, a shift motor power circuit, a generator motor power circuit, a drive motor power circuit, an Elock circuit, and a power supply circuit, all electrically connected to the microprocessor chip, wherein: The microprocessor chip controls the oil pump motor through the oil pump motor power circuit, the microprocessor chip controls the shift motor through the shift motor power circuit, the microprocessor chip controls the generator motor through the generator motor power circuit, the microprocessor chip controls the drive motor through the drive motor power circuit, and the microprocessor chip controls the power coupling module through the Elock circuit.

[0014] As a further preferred technical solution to the above technical solution, for the generator motor and the drive motor, the microprocessor chip collects the resolver feedback signal through the resolver circuit and combines it with the output torque target to control the generator motor and the drive motor respectively. The specific implementation of the microprocessor chip's control of the generator motor and the drive motor is as follows: The microprocessor chip sends a PWM control signal to the corresponding power circuit driver chip according to the expected torque and speed. After power amplification, the driver chip drives the IGBT to work, so that the corresponding motor rotates according to the expected torque and speed. The microprocessor chip simultaneously emits a resolver excitation signal, which is a square wave. After being filtered and amplified by the resolver excitation circuit, it is output to the primary side of the resolver transformer inside the motor. The sine and cosine signals fed back from the resolver are filtered by the resolver sampling point and then input to the microprocessor chip. The chip uses software decoding to identify whether the current speed of the motor matches the expected command. If it does not match the command, it enters the PI closed-loop regulation state and outputs the PWM duty cycle signal under dynamic conditions. Furthermore, the microprocessor chip contains multiple CPUs, allowing different motor control codes to be processed in different CPUs; the hardware interface distinguishes the control signals of different motors through pin design, enabling individual control functions for different motors.

[0015] As a further preferred technical solution to the above technical solution, for the drive motor, the drive motor is designed to meet the ASIL-C functional safety target. The microprocessor chip outputs the PWM control signal to the buffer circuit, i.e., the level conversion chip circuit. The buffer circuit is used to effectively increase the driving capability and perform square wave shaping processing on the model to ensure the quality of the PWM signal output to the back end. At the same time, if the microprocessor chip detects signals including overcurrent, overvoltage or other faults, it directly shuts down the buffer chip of the buffer circuit to avoid the issuance of erroneous signals. The design incorporates a drive feedback function for the motor. The microprocessor chip will analyze the frequency and duty cycle values ​​of the PWM signal sampled via GPIO and compare them with the expected frequency and duty cycle values ​​of the command. If they match, it proves that the actual PWM signal is correctly generated, ensuring the correctness of the generated signal. If the frequency and duty cycle values ​​analyzed from the sampled PWM signal do not match the values ​​in the expected command, it proves that there is a problem in the signal transmission process, requiring the system to enter a fault state and stop for troubleshooting.

[0016] As a further preferred technical solution to the above technical solution, if a fault including overcurrent or overvoltage occurs in the system during the operation of the drive motor and the generator motor, a first-level shutdown logic, a second-level shutdown logic, and a third-level shutdown logic are set, wherein: The first level of shutdown logic is that the output instruction of the microprocessor chip is output at a preset fixed level; the second level of shutdown logic is that the output instruction of the microprocessor chip directly shuts down the electrical buffer chip through the logic circuit. The second level of shutdown logic requires the use of an external resistor to enable the system to enter the predetermined lower bridge arm ASC functional safety state. The first layer of shutdown logic is the normal fault response action of the microprocessor chip when all circuit functions are normal; the second layer of shutdown logic is the establishment of a separate fault channel when the system assumes that some circuit functions have failed and the signal cannot be effectively transmitted from the microprocessor chip to the driver chip, so that the microprocessor chip has the function of directly shutting down the driver chip. The third layer of shutdown logic occurs when the microprocessor chip does not interact with the SBC chip of the power supply circuit via WDG signals. In this case, the SBC chip assumes that the microprocessor chip has a problem and that the signals it sends are unreliable, thus directly shutting down the signal channel.

[0017] As a further preferred technical solution to the above technical solution, for the oil pump motor and the shift motor, the microprocessor chip communicates directly with the corresponding power circuit driver chip via SPI to configure registers to implement status and fault response actions.

[0018] As a further preferred embodiment of the above technical solution, the microprocessor chip communicates with the control chip in the corresponding power circuit of the corresponding motor via SPI, thereby configuring the registers of the drive chip. Specifically, the implementation is as follows: The first step is to set the driver chip to a configurable state via SPI communication bits, and then use SPI communication to initialize the driver chip registers to achieve the chip register initialization and clearing action; The second step is to configure the analog self-test and digital self-test BIST registers so that the driver chip can perform its own status check. The third step is to configure the output frequency and minimum dead time register of the driver chip, and set the frequency value and dead time limit parameters of the chip output signal. The fourth step is to configure the driver chip's fault register and set the chip's response time to overcurrent and overvoltage faults. Fifth step, configure the driver chip registers and set the interaction cycle value with the driver chip WDG; Step 6: Configure the driver chip's fault register to determine the chip's response time to over-temperature faults; Step 7: Configure the driver chip registers to determine if there are any faults that need to be masked; Step 8: Use the SPI communication bit to exit the configurable state of the driver chip.

[0019] As a further preferred technical solution to the above technical solution, the motor control function is also achieved through a buffer circuit, an emergency shutdown circuit, and a resolver circuit, wherein: The design incorporates a buffer circuit at the output, where the digital circuit performs square wave shaping on the MCU output waveform. The buffer chip itself ensures that the emitted waveform has more accurate recognition. The emergency shutdown circuit operates in the indicated state when the system experiences overcurrent or overvoltage faults. After receiving an overvoltage or overcurrent fault, the microprocessor chip must perform at least one operation cycle before issuing a fault response command. When a fault occurs, the emergency shutdown circuit uses the microprocessor chip's GTM function to issue a fault response command without going through a CPU operation cycle. Then, the signal issued at the end of the CPU operation cycle verifies and modifies the emergency fault command signal, achieving the goal of issuing an accurate command both quickly and after signal verification. The resolver circuit includes an excitation circuit and a sampling circuit. The excitation circuit shapes the square wave emitted by the microprocessor chip into a sine wave and sends it to the resolver circuit through power amplification. The secondary side of the resolver circuit provides feedback signals, which are then input to the sampling circuit. After RC filtering, the microprocessor chip decodes the motor speed and position signals through software decoding, thereby realizing the normal control function of the motor. Attached Figure Description

[0020] Figure 1 This is a functional block diagram of the MCU chip of the present invention.

[0021] Figure 2 This is a topology diagram of the multifunctional integrated motor controller system of the present invention.

[0022] Figure 3 This is a power motor drive topology diagram of the multifunctional integrated motor controller of the present invention.

[0023] Figure 4 This is a functional topology diagram of the multifunctional integrated motor controller driving + generator motor of the present invention.

[0024] Figure 5 This is a BLDC drive topology diagram of the multifunctional integrated motor controller of the present invention.

[0025] Figure 6 This is a block diagram illustrating the power coupling function principle of the multifunctional integrated motor controller of the present invention.

[0026] Figure 7 This is a functional block diagram of the power coupling control of the multifunctional integrated motor controller of the present invention. Detailed Implementation

[0027] The following description is intended to disclose the present invention and enable those skilled in the art to implement it. The preferred embodiments described below are merely examples, and other obvious variations will occur to those skilled in the art. The basic principles of the invention defined in the following description can be applied to other embodiments, modifications, improvements, equivalents, and other technical solutions that do not depart from the spirit and scope of the invention.

[0028] In the preferred embodiments of the present invention, those skilled in the art should note that the motors and the like involved in the present invention can be considered as prior art.

[0029] Preferred embodiment.

[0030] like Figure 1-7 As shown, this invention discloses a multi-functional integrated motor control system for hybrid new energy vehicles, including a microprocessor chip (BGA292) and an oil pump motor power circuit electrically connected to the microprocessor chip (i.e., Figure 1 BLDC 1), shift motor power circuit (i.e. Figure 1 BLDC 2), generator power circuit (i.e. Figure 1 Inverter 1), drive motor power circuit (i.e. Figure 1 The circuit consists of Inverter 2), Elock circuit, and power supply circuit, among which: The microprocessor chip controls the oil pump motor through the oil pump motor power circuit, the microprocessor chip controls the shift motor through the shift motor power circuit, the microprocessor chip controls the generator motor through the generator motor power circuit, the microprocessor chip controls the drive motor through the drive motor power circuit, and the microprocessor chip controls the power coupling module through the Elock circuit.

[0031] Specifically, the functional block diagram of the multi-functional integrated motor controller MCU chip is as follows: Figure 1 For generator motors and drive motors, the microprocessor chip uses a resolver circuit (such as...) Figure 1 As shown, the generator motor collects data through resolver circuit 1, and the drive motor collects data through resolver circuit 2. The resolver feedback signal is collected and combined with the output torque target to control the generator motor and drive motor respectively. The specific implementation of the microprocessor chip's control over the generator motor and drive motor is as follows: The microprocessor chip sends a PWM control signal to the corresponding power circuit (i.e., the generator motor power circuit or the drive motor power circuit) according to the expected torque and speed. After power amplification, the drive chip drives the IGBT to work, so that the corresponding motor rotates according to the expected torque and speed. The microprocessor chip simultaneously emits a resolver excitation signal, which is a square wave. After being filtered and amplified by the resolver excitation circuit, it is output to the primary side of the resolver transformer inside the motor. The sine and cosine signals fed back from the resolver are filtered by the resolver sampling point and then input to the microprocessor chip. The chip uses software decoding to identify whether the current speed of the motor matches the expected command. If it does not match the command, it enters the PI closed-loop regulation state and outputs the PWM duty cycle signal under dynamic conditions. Furthermore, the microprocessor chip contains multiple CPUs, allowing different motor control codes to be processed in different CPUs; the hardware interface distinguishes the control signals of different motors through pin design, enabling individual control functions for different motors.

[0032] More specifically, for the drive motor, the design aims for ASIL-C functional safety. The microprocessor chip outputs a PWM control signal to the buffer circuit, i.e., the level conversion chip circuit. The buffer circuit effectively increases the driving capability and performs square wave shaping on the model to ensure the quality of the PWM signal output to the back end. At the same time, if the microprocessor chip detects signals including overcurrent, overvoltage, or other faults, it directly shuts down the buffer chip of the buffer circuit to avoid issuing erroneous signals (SBC, DSP1, and the level conversion chip constitute the basic functional control part of the system; powered by the KL30 voltage provided by the 12V battery of the power supply circuit). The design incorporates a drive feedback function for the drive motor. (To enhance system reliability, the drive motor's control circuit incorporates this function.) The microprocessor chip retrieves the PWM signal via GPIO, analyzes the frequency and duty cycle values, and compares them with the expected command's frequency and duty cycle values. If they match, the actual PWM signal is correctly generated, ensuring signal accuracy. If the frequency and duty cycle values ​​from the retrieved PWM signal do not match the expected command, a problem arises in the signal transmission process, requiring a fault shutdown to await troubleshooting. (The generator motor's impact on vehicle safety is not critical in terms of real-time performance; therefore, the design aims for ASIL-B, eliminating the need to retrieve the PWM signal input from the drive chip's front end, thus reducing the demand on the main arithmetic unit's resources.)

[0033] Furthermore, during the operation of the drive motor and generator motor, if the system experiences faults including overcurrent and overvoltage, a first-level shutdown logic, a second-level shutdown logic, and a third-level shutdown logic are set, wherein: The first-level shutdown logic is that the output instruction of the microprocessor chip is output at a preset fixed level; the second-level shutdown logic is that the output instruction of the microprocessor chip directly shuts down the cache chip (i.e., the level conversion chip) through the logic circuit to achieve a faster and more stable shutdown method. The second-level shutdown logic requires the use of an external resistor to enable the system to enter the predetermined lower bridge arm ASC functional safety state. The first layer of shutdown logic is the normal fault response action of the microprocessor chip when all circuit functions are normal; the second layer of shutdown logic is to establish a separate fault channel when the system assumes that some circuit functions have failed and the signal cannot be effectively transmitted from the microprocessor chip to the driver chip, so that the microprocessor chip has the function of directly shutting down the driver chip (this is a double insurance in case of fault, both will work). The third layer of shutdown logic occurs when the microprocessor chip does not interact with the SBC chip of the power supply circuit via WDG signal. The SBC chip then assumes that the microprocessor chip has a problem and that the signal it sends is unreliable, thus directly shutting off the signal channel (this only works when WDG fails).

[0034] If other serious faults occur in the system, such as high-voltage interlock problems or resolver malfunctions, the microprocessor chip can output targeted instructions based on the location of the fault. Through the emergency shutdown ASC circuit, it can directly control the IGBT isolated driver chip of the drive motor or generator to bring the system into a predetermined functional safety state. The identical sampling design of the drive motor and generator power circuits reduces system cost. The topology is as follows: Figure 3 The topology of the drive motor and generator power section is as follows: Figure 4 .

[0035] Furthermore, for the oil pump motor and shift motor, the microprocessor chip communicates directly with the corresponding power circuit driver chip via SPI to configure registers and implement status and fault response actions. (Integrating the oil pump motor control and shift motor control functions in the hybrid system can significantly reduce system application costs. The oil pump motor control power is relatively small, and a precision sampling resistor is used to collect the output current signal for closed-loop feedback control. The power circuits of the oil pump motor and shift motor use the same design to reduce system costs; the topology is as follows...) Figure 5 ).

[0036] Preferably, the microprocessor chip communicates with the control chip in the corresponding power circuit of the corresponding motor via SPI, thereby configuring the registers of the drive chip. Specifically, the implementation is as follows: The first step is to set the driver chip to a configurable state via SPI communication bits, and then use SPI communication to initialize the driver chip registers to achieve the chip register initialization and clearing action; The second step is to configure the analog self-test and digital self-test BIST registers so that the driver chip can perform its own status check. The third step is to configure the output frequency and minimum dead time register of the driver chip, and set the frequency value and dead time limit parameters of the chip output signal. The fourth step is to configure the driver chip's fault register and set the chip's response time to overcurrent and overvoltage faults. Fifth step, configure the driver chip registers and set the interaction cycle value between the (MCU) and the driver chip WDG; Step 6: Configure the driver chip's fault register to determine the chip's response time to over-temperature faults; Step 7: Configure the driver chip registers to determine if there are any faults that need to be masked; Step 8: Use the SPI communication bit to exit the configurable state of the driver chip.

[0037] Preferably, the motor control function is further implemented through a buffer circuit, an emergency shutdown circuit, and a resolver circuit, wherein: (The output signal of the microprocessor chip may have an irregular waveform after a long transmission.) Design a buffer circuit at the (MCU) output end. Its digital circuit performs square wave shaping on the MCU output waveform. The buffer chip itself ensures that the output waveform has more correct recognition. The emergency shutdown circuit operates in the indicated state when the system experiences overcurrent or overvoltage faults. After receiving an overvoltage or overcurrent fault, the microprocessor chip must perform at least one operation cycle before issuing a fault response command. When a fault occurs, the emergency shutdown circuit uses the microprocessor chip's GTM function to issue a fault response command without going through a CPU operation cycle. Then, the signal issued at the end of the CPU operation cycle verifies and modifies the emergency fault command signal, achieving the goal of issuing an accurate command both quickly and after signal verification. The resolver circuit includes an excitation circuit and a sampling circuit. The excitation circuit shapes the square wave emitted by the microprocessor chip into a sine wave and sends it to the resolver circuit through power amplification. The secondary side of the resolver circuit provides feedback signals, which are then input to the sampling circuit. After RC filtering, the microprocessor chip decodes the motor speed and position signals through software decoding, thereby realizing the normal control function of the motor.

[0038] For the drive motor and generator motor, a single BGA292 microprocessor chip (i.e., microprocessor chip), along with the SBC and peripheral circuits, is used to implement the functional control circuit. The power supply circuit uses an ASIL-D level SBC power supply chip as the power supply circuit for the BGA292 microprocessor chip. At the same time, the SBC and the BGA292 microprocessor chip have WDG monitoring functions. If the BGA292 microprocessor chip fails to feed back the WDG signal on time, the SBC considers the main arithmetic unit chip to be malfunctioning and can directly control the drive chip through the ASC circuit to implement fault actions in an emergency state.

[0039] For the oil pump motor and the shift motor, the control circuit is designed with a main arithmetic unit chip that communicates directly with the driver chip to reduce signal resource usage. The control circuit also includes a power supply module to power all circuits, and a high-voltage power supply circuit with a DC-DC output for redundant 12V battery power.

[0040] This invention utilizes a BGA 292 packaged microprocessor chip to implement four motor control functions and a power coupling module control function. It can optimize the system scheme and cost while ensuring system reliability to the greatest extent. The low-cost optimized architecture is conducive to increasing product competitiveness.

[0041] The main arithmetic unit chip of this invention collects the KL30 voltage and SBC output voltage provided by the 12V battery to ensure normal power supply function.

[0042] In a hybrid powertrain system, there are powertrain components such as an engine, electric motor, and gearbox. If the vehicle malfunctions, the motor, engine, and wheels cannot disengage from the power coupling, which can cause damage to the motor and power components under towing conditions. Therefore, this design incorporates a power coupling module controller, physically structured as a solenoid valve. When the internal coil is active, the internal gears engage to transmit power; in a fault condition, the internal coil is inactive, the internal gears disengage, and power transmission ceases. This design controls the operation of the internal coil. In special circumstances, the main arithmetic unit chip can disengage the power coupling, allowing for more flexible vehicle handling. A schematic diagram of the hybrid power coupling is shown below. Figure 6 The topology of the power coupling module control function is as follows: Figure 7 .

[0043] The solution incorporates a high-voltage backup power supply design. In vehicle applications, if the 12V battery power supply circuit of the vehicle experiences a connection failure or a sudden power outage, the high-voltage battery can continue to supply power to the low-voltage system, ensuring normal system function and achieving the goal of high system reliability.

[0044] The advantages of this invention are: 1) The design utilizes a BGA292 packaged main arithmetic unit (ALU) chip to control the drive motor, generator motor, oil pump motor, shift motor, power coupling module, and high-voltage backup power supply. By analyzing the impact of each function on the system and designing different functional safety targets, all control functions are achieved with 98% pin utilization of the main ALU. This design achieves a high-reliability and high-diagnostic-coverage electric drive inverter system using a relatively low-cost main ALU chip.

[0045] 2) The design incorporates independent drive motor control circuits and generator motor control circuits, allowing for independent control of each motor's abnormalities and fault handling circuits, achieving high reliability. A scheme where the main arithmetic unit directly controls the oil pump motor and gear shift motor enhances the real-time performance of BLDC motor control and avoids redundant circuitry impacting the main arithmetic unit's resource requirements.

[0046] 3) The solution is designed with engine, motor and wheel power coupling module control function. If the vehicle is abnormal, the motor, engine and wheels cannot be disconnected from the power connection. In the case of towing and other working conditions, the vehicle is easier to handle and avoids damage to the motor and power components.

[0047] 4) The design scheme is to use a high-voltage DC-DC power supply circuit, which is connected in parallel with the 12V battery power supply terminal. The output voltage of the high-voltage power supply is designed to be lower than the 12V battery voltage, but it can ensure the normal operating voltage of the system. When the 12V battery power supply voltage is unstable, it can directly intervene to supply power and ensure the normal power supply of the system. When the 12V battery power supply voltage is stable, it does not work as a backup power supply.

[0048] In this invention, the SBC (System-Based Controller) allows for verification of the main arithmetic unit's software operation status. The main arithmetic unit also incorporates sampling and verification of the input signals from the drive motor power chip, which has higher safety requirements, achieving high reliability and high functional safety levels. The main arithmetic unit utilizes direct communication with the oil pump motor and shift motor drive chips to save chip resources and reduce system costs. A high-voltage DC-DC power supply circuit is designed and connected in parallel with the 12V battery power supply. In cases of unstable 12V battery voltage, direct power supply can be provided to ensure normal system power supply.

[0049] This invention integrates multiple motor control functions and power coupling module control functions at a lower cost by using a single small-package main arithmetic unit chip. An independent power supply scheme is designed to ensure the safety of the power system. The main arithmetic unit synchronously realizes the diverse fault states of the electric drive inverter assembly, effectively improving system reliability, enhancing product cost-effectiveness, and increasing the competitiveness of the entire vehicle.

[0050] It is worth mentioning that the technical features such as motors involved in this patent application should be regarded as prior art. The specific structure, working principle, and possible control methods and spatial arrangement of these technical features can be adopted using conventional choices in the field, and should not be regarded as the inventive point of this patent. This patent will not be further elaborated in detail.

[0051] For those skilled in the art, modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this invention should be included within the protection scope of this invention.

Claims

1. A multi-functional integrated motor control system for hybrid new energy vehicles, characterized in that, It includes a microprocessor chip and oil pump motor power circuit, shift motor power circuit, generator motor power circuit, drive motor power circuit, Elock circuit and power supply circuit, which are electrically connected to the microprocessor chip respectively, wherein: The microprocessor chip controls the oil pump motor through the oil pump motor power circuit, the microprocessor chip controls the shift motor through the shift motor power circuit, the microprocessor chip controls the generator motor through the generator motor power circuit, the microprocessor chip controls the drive motor through the drive motor power circuit, and the microprocessor chip controls the power coupling module through the Elock circuit. The microprocessor chip acquires resolver feedback signals through a resolver circuit and combines them with the output torque target to control the generator motor and drive motor respectively. The control principle of the microprocessor chip for the generator motor and drive motor is as follows: The microprocessor chip sends a PWM control signal to the corresponding power circuit driver chip according to the expected torque and speed. After power amplification, the driver chip drives the IGBT to work, so that the corresponding motor rotates according to the expected torque and speed. The microprocessor chip simultaneously emits a resolver excitation signal, which is a square wave. After being filtered and amplified by the resolver excitation circuit, the signal is output to the primary side of the resolver transformer inside the motor. The sine and cosine signals fed back from the secondary side of the resolver transformer are filtered by the resolver sampling circuit and then input to the microprocessor chip. The chip uses software decoding to identify whether the current speed of the motor is consistent with the expected command. If it does not meet the command, it enters the PI closed-loop regulation state and dynamically adjusts the output PWM duty cycle signal. The microprocessor chip contains multiple CPUs, and different motor control codes are processed in different CPUs; the hardware interface distinguishes the control signals of different motors through pin design, so as to realize the individual control function of different motors. The drive motor is set to ASIL-C functional safety target. The microprocessor chip outputs PWM control signal to the buffer circuit, i.e. level conversion chip circuit. The buffer circuit is used to effectively increase the driving capability and perform square wave shaping on the waveform to ensure the quality of the PWM signal output to the back end. At the same time, if the microprocessor chip detects signals including overcurrent, overvoltage or other faults, it directly shuts down the buffer chip of the buffer circuit to avoid the issuance of erroneous signals. The microprocessor chip is configured to use a drive feedback function for the drive motor. It will analyze the frequency and duty cycle values ​​of the PWM signal sampled via GPIO and compare them with the frequency and duty cycle values ​​of the expected command. If they match, the correctness of the actual PWM signal is verified, ensuring the correctness of the signal output. If the frequency and duty cycle values ​​analyzed from the sampled PWM signal do not match the values ​​in the expected command, it indicates a problem in the signal transmission process, requiring the machine to enter a fault state and stop for troubleshooting.

2. The multi-functional integrated motor control system for hybrid new energy vehicles according to claim 1, characterized in that, During the operation of the drive motor and generator motor, if the system experiences faults including overcurrent and overvoltage, a first-level shutdown logic, a second-level shutdown logic, and a third-level shutdown logic are set, wherein: The first-level shutdown logic is that the output instruction of the microprocessor chip is output at a preset fixed level; the first-level shutdown logic is the routine fault response action executed by the microprocessor chip when all circuit functions are considered to be normal. The second-level shutdown logic is that the output instruction of the microprocessor chip directly shuts down the cache chip through the logic circuit. The second-level shutdown logic requires the use of an external resistor to enable the system to enter the predetermined lower bridge arm ASC functional safety state. The second-level shutdown logic assumes that if the system experiences partial circuit failure, the signal cannot be effectively transmitted from the microprocessor chip to the driver chip. Therefore, a separate fault channel is established so that the microprocessor chip has the function of directly shutting down the driver chip. The third layer of shutdown logic occurs when the microprocessor chip does not interact with the SBC chip of the power supply circuit via WDG signals. In this case, the SBC chip assumes that the microprocessor chip has a problem and that the signals it sends are unreliable, thus directly shutting down the signal channel.

3. A multi-functional integrated motor control system for hybrid new energy vehicles according to claim 1, characterized in that, The microprocessor chip communicates with the control chip in the corresponding power circuit of the motor via SPI, thereby configuring the registers of the driver chip. Specifically, the implementation is as follows: The first step is to set the driver chip to a configurable state via SPI communication bits, and then use SPI communication to initialize the driver chip registers to achieve the chip register initialization and clearing action; The second step is to configure the analog self-test and digital self-test BIST registers so that the driver chip can perform its own status check. The third step is to configure the driver chip's output frequency and minimum dead time register, and set the frequency value and dead time limit parameters of the chip's output signal. The fourth step is to configure the driver chip's fault register and set the chip's response time to overcurrent and overvoltage faults. Fifth step, configure the driver chip registers and set the interaction cycle value with the driver chip WDG; Step 6: Configure the driver chip's fault register and set the chip's response time to over-temperature faults; Step 7: Configure the driver chip registers and set the faults that need to be masked; The eighth step is to use the SPI communication bit to make the driver chip exit the configurable state.

4. A multi-functional integrated motor control system for hybrid new energy vehicles according to claim 1, characterized in that, For the oil pump motor and the shift motor, the microprocessor chip communicates directly with the corresponding power circuit driver chip via SPI to configure registers and implement status and fault response actions.

5. A multi-functional integrated motor control system for hybrid new energy vehicles according to claim 1, characterized in that, The motor control function is also achieved through buffer circuits, emergency shutdown circuits, and resolver circuits, among which: The buffer circuit is located at the output end. Its digital circuit performs square wave shaping on the MCU output waveform. Relying on the performance of the buffer chip itself, it ensures that the output waveform is easy to identify. When an overcurrent or overvoltage fault occurs in the system, the emergency shutdown circuit is activated. After receiving an overvoltage or overcurrent fault, the microprocessor chip must perform at least one operation cycle before issuing a fault response command. When a fault occurs, the emergency shutdown circuit uses the microprocessor chip's built-in GTM function to issue a fault response command without going through a CPU operation cycle. Then, the signal issued at the end of the CPU operation cycle verifies and corrects the emergency fault command signal, achieving the goal of issuing an accurate command both quickly and after signal verification. The resolver circuit includes an excitation circuit and a sampling circuit. The excitation circuit shapes the square wave emitted by the microprocessor chip into a sine wave and sends it to the resolver after power amplification. The secondary side of the resolver feeds back the signal and inputs it to the sampling circuit. After RC filtering, the microprocessor chip parses the motor speed and position signals through software decoding code to realize the normal motor control function.

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