EFUSE programming reading circuit and electronic equipment

Abstract

The invention provides an EFUSE programming reading circuit which is characterized in that a comparison voltage output module is used for outputting a comparison voltage, a first end and a second end of a programming control unit in each fuse module are respectively coupled to a first end and a second end of a fuse, and a third end of the programming control unit is grounded. When a programming control signal and a programming power supply control signal are represented to be forbidden, the voltage of the second end of the fuse wire is pulled down to a low level, so that a first comparison unit can carry out comparison conveniently; when the two signals are represented as enabling signals, the voltage of the second end of the fuse wire is pulled up to a preset voltage, and the second end and the third end of the programming control unit are controlled to be conducted so as to fuse the fuse wire; the first comparison unit provides a first current for the fuse wire, compares the voltage value of the first end of the fuse wire with the magnitude of the comparison voltage when the read control signal is enabled, and outputs a comparison result signal. According to the invention, enough programming current is provided only when the fuse needs to be fused, so that the problem of wrong programming is avoided, and long-term reliable reading of the EFUSE is guaranteed.

Description

Technical Field

[0001] The present invention relates to the technical field of power electronics, and in particular to an EFUSE programming and reading circuit and electronic equipment. Background Art

[0002] In modern integrated circuit design, electronic fuses (EFUSE) achieve the "write once, hold forever" feature of data by physically burning metal connections or polysilicon to form a permanent open circuit. They are widely used in chip identification, configuration storage, and lifecycle management.

[0003] However, throughout the chip's lifecycle, the resistance value of the burned-out EFUSE may fluctuate due to factors such as time and temperature, leading to uncertainty in read results and impacting system stability and security. Furthermore, when the chip is operating normally but not reading the EFUSE, the programming circuit may still be falsely triggered due to external interference, glitches, and other issues, leading to incorrect programming of the EFUSE and irreversible functional damage.

[0004] Therefore, how to avoid erroneous programming operations on EFUSE and ensure long-term reliable reading of EFUSE has become a technical problem to be solved urgently in this field. Summary of the Invention

[0005] The present invention provides an EFUSE burning and reading circuit and electronic equipment, which solves the technical problem of how to avoid erroneous burning and writing operations on the EFUSE and ensure long-term reliable reading of the EFUSE.

[0006] According to a first aspect of the present invention, an embodiment of the present invention provides an EFUSE programming and reading circuit, comprising:

[0007] Comparison voltage output module, used for outputting comparison voltage;

[0008] N fuse modules, where N is an integer greater than or equal to 1, and each fuse module includes:

[0009] fuse;

[0010] A burn control unit, having a first end and a second end coupled to the first end and the second end of the fuse, respectively, and a third end grounded. A first control end of the burn control unit receives a burn control signal, a second control end receives a burn power control signal, and a power supply end receives a preset voltage. The burn control unit is configured to: when both the burn control signal and the burn power control signal indicate disable, pull down the voltage at the second end of the fuse to a low level; when both the burn control signal and the burn power control signal indicate enable, pull up the voltage at the second end of the fuse to the preset voltage, and control conduction between the second end and the third end of the burn control unit to blow the fuse.

[0011] a first comparing unit, wherein a first input terminal thereof receives the comparison voltage, a second input terminal thereof is coupled to the first terminal of the fuse, and a control terminal thereof receives a read control signal, wherein the first comparing unit is configured to: provide a first current to the fuse;

[0012] When the read control signal is enabled, the voltage value of the first end of the fuse is compared with the comparison voltage, and a comparison result signal is output.

[0013] Optionally, the programming control unit includes a first NAND gate, a first inverter and a first NMOS transistor;

[0014] The first input end of the first NAND gate receives the writing control signal, the second input end thereof receives the writing power supply control signal, the output end thereof outputs a NAND result signal to the second end of the fuse through the first inverter, the power supply end of the first inverter receives the preset voltage, the drain of the first NMOS tube is coupled to the first end of the fuse, the gate thereof receives the writing power supply control signal, and the source thereof is grounded.

[0015] Optionally, the first inverter is further configured to delay the NAND result signal.

[0016] Optionally, the programming control unit includes a first AND gate, a first inverter, a third inverter and a first NMOS tube;

[0017] The first input terminal of the first AND gate receives the programming control signal, the second input terminal thereof receives the programming power supply control signal, and the output terminal thereof sequentially outputs a NAND result signal to the second terminal of the fuse through the third inverter and the first inverter. The power supply terminal of the first inverter receives the preset voltage. The drain of the first NMOS transistor is coupled to the first terminal of the fuse, the gate thereof receives the programming power supply control signal, and the source thereof is grounded.

[0018] The second end of the first tail current source is coupled to the first input end of the second NAND gate. The second input end of the second NAND gate receives the read control signal, and the output end thereof outputs the comparison result signal through the second inverter.

[0019] Optionally, the first input terminal of each first comparison unit receives the comparison voltage through a second comparison module;

[0020] Each of the first comparison units includes a first tail current source, a second NMOS transistor, a second NAND gate, and a second inverter; the second comparison module includes a second tail current source and a third NMOS transistor;

[0021] The first end of the first tail current source receives the power supply voltage, and the second end thereof is coupled to the drain of the second NMOS tube. The source of the second NMOS tube is coupled to the first end of the fuse, and the gate thereof is coupled to the gate of the third NMOS tube. The first end of the second tail current source receives the power supply voltage, and the second end thereof is coupled to the drain of the third NMOS tube. The drain of the third NMOS tube is also coupled to its gate, and the source thereof is coupled to the output end of the comparison voltage output module.

[0022] Optionally, the comparison voltage includes a high margin voltage, a default comparison voltage, and a low margin voltage; the first control terminal of the comparison voltage output module receives a high margin control signal, and the second control terminal receives a low margin control signal;

[0023] The comparison voltage output module is configured to: output the high margin voltage when the high margin control signal is enabled; output the low margin voltage when the low margin control signal is enabled; otherwise, output the default comparison voltage.

[0024] Optionally, the comparison voltage output module includes a third tail current source, a high margin switch, a first resistor, a second resistor and a low margin switch;

[0025] The first end of the third tail current source receives the supply voltage, and the second end thereof is coupled to the first end of the first resistor through the high margin switch, the control end of the high margin switch receives the high margin control signal, the second end of the first resistor is coupled to the first end of the second resistor, the second end of the second resistor is coupled to the second end of the burning control unit, the low margin switch is connected in parallel with the second resistor, and the control end of the low margin switch receives the low margin control signal.

[0026] Optionally, the high margin switch is a PMOS tube, and the high margin switch receives the high margin control signal through an inverter.

[0027] Optionally, the low margin switch is an NMOS tube.

[0028] According to a second aspect of the present invention, an embodiment of the present invention provides an electronic device, comprising the EFUSE programming and reading circuit according to any one of the first aspects of the present invention.

[0029] Compared with the prior art, the technical solution of the embodiment of the present invention has the following beneficial effects:

[0030] In the EFUSE programming and reading circuit of the present invention, a comparison voltage output module is used to output a comparison voltage. The first and second ends of the programming control unit in each fuse module are respectively coupled to the first and second ends of the fuse, and the third end thereof is grounded. When both the programming control signal and the programming power control signal are disabled, the programming control unit pulls down the voltage of the second end of the fuse to a low level to facilitate comparison by the first comparison unit. When both signals are enabled, the programming control unit pulls up the voltage of the second end of the fuse to a preset voltage and controls the conduction between the second and third ends of the programming control unit to blow the fuse in the fuse. The first comparison unit provides a first current to the fuse and compares the voltage value of the first end of the fuse with the comparison voltage when the reading control signal is enabled, and outputs a comparison result signal. The present invention only provides sufficient programming current when the fuse needs to be blown, avoiding the problem of EFUSE misprogramming and ensuring long-term and reliable reading of the EFUSE.

[0031] Furthermore, the programming control unit includes a first NAND gate, a first inverter, and a first NMOS transistor; the first input of the first NAND gate receives the programming control signal, the second input receives the programming power supply control signal, and the output outputs a NAND result signal to the second end of the fuse through the first inverter. The power supply end of the first inverter receives the preset voltage, the drain of the first NMOS transistor is coupled to the first end of the fuse, the gate receives the programming power supply control signal, and the source is grounded. The first inverter is also used to delay the NAND result signal. Therefore, the present invention prevents the EFUSE from being misprogrammed due to signal glitches by means of a short delay, thereby ensuring long-term and reliable reading of the EFUSE. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0033] Figure 1 This is a structural diagram of an EFUSE programming and reading circuit provided by an embodiment of the prior art;

[0034] Figure 2 This is a schematic diagram of the structure of the EFUSE programming and reading circuit provided by an embodiment of the present invention. Figure 1 ;

[0035] Figure 3 This is a schematic diagram of the structure of the EFUSE programming and reading circuit provided by an embodiment of the present invention. Figure 2 ;

[0036] Figure 4 This is a schematic diagram of the structure of the EFUSE programming and reading circuit provided by an embodiment of the present invention. Figure 3 ;

[0037] Figure 5 This is a schematic diagram of the structure of the EFUSE programming and reading circuit provided by an embodiment of the present invention. Figure 4 . DETAILED DESCRIPTION

[0038] As described in the background art, it is difficult to avoid erroneous programming of EFUSE in the prior art and ensure long-term reliable reading of EFUSE.

[0039] Figure 1 The present invention is a structural diagram of an embodiment of an EFUSE programming and reading circuit.

[0040] Please refer to Figure 1 A first end of the fuse EFUSE RES is coupled to the power supply through a PMOS tube, and a second end thereof is grounded. The gate of the PMOS tube receives a programming control signal Program_EN through an inverter.

[0041] EFUSE is programmed during mass production testing and will not be programmed when the chip is in use. Figure 1 In the example, the programming control signal Program_EN generates a high-level pulse at the input of the inverter when powered on or subjected to interference, causing the PMOS transistor to conduct when the chip is in use. Furthermore, since the programming time of the electromigration EFUSE is within 10 μs, this circuit is very likely to cause an erroneous programming operation on the EFUSE when the chip is in use, making it difficult to ensure long-term reliable reading of the EFUSE.

[0042] In view of this, the present invention provides an EFUSE programming and reading circuit, wherein a comparison voltage output module is used to output a comparison voltage. The first and second ends of the programming control unit in each fuse module are respectively coupled to the first and second ends of the fuse, and the third end thereof is grounded. When both the programming control signal and the programming power control signal are disabled, the programming control unit pulls down the voltage of the second end of the fuse to a low level to facilitate comparison by the first comparison unit. When both signals are enabled, the programming control unit pulls up the voltage of the second end of the fuse to a preset voltage and controls the conduction between the second and third ends of the programming control unit to blow the fuse in the fuse. The first comparison unit provides a first current to the fuse and compares the voltage value of the first end of the fuse with the comparison voltage when the reading control signal is enabled, and outputs a comparison result signal. The present invention only provides sufficient programming current when the fuse is required to blow, avoiding the problem of misprogramming and ensuring long-term and reliable EFUSE reading.

[0043] The following will provide a clear and complete description of the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. All other embodiments obtained by ordinary technicians in this field based on the embodiments of the present invention without making any creative efforts shall fall within the scope of protection of the present invention.

[0044] The terms "first," "second," "third," "fourth," and the like (if any) in the description and claims of the present invention and in the accompanying drawings are used to distinguish similar objects and are not necessarily used to describe a particular order or precedence. It should be understood that the terms used in this manner are interchangeable where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. In addition, the terms "including" and "having," as well as any variations thereof, are intended to cover non-exclusive inclusions, e.g., a process, method, system, product, or apparatus comprising a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units that are not explicitly listed or that are inherent to these processes, methods, products, or apparatus.

[0045] The following specific embodiments are used to describe the technical solution of the present invention in detail. The following specific embodiments can be combined with each other, and the same or similar concepts or processes may not be described in detail in some embodiments.

[0046] Figure 2 The EFUSE programming and reading circuit according to an embodiment of the present invention includes:

[0047] A comparison voltage output module 10 is used to output a comparison voltage;

[0048] N fuse modules, where N is an integer greater than or equal to 1.

[0049] In an embodiment of the present invention, each fuse module includes:

[0050] Fuse EFUSE RES;

[0051] The programming control unit 30 has a first terminal and a second terminal coupled to the first terminal and the second terminal of the fuse EFUSE RES, respectively, and a third terminal grounded. The first control terminal receives the programming control signal Program_EN, the second control terminal receives the programming power control signal Fsource, and the power supply terminal receives a preset voltage VCC. The programming control unit 30 is configured to: when both the programming control signal Program_EN and the programming power control signal Fsource are disabled, pull down the voltage at the second terminal of the fuse EFUSE RES to a low level; when both the programming control signal Program_EN and the programming power control signal Fsource are enabled, pull up the voltage at the second terminal of the fuse EFUSE RES to the preset voltage VCC, and control conduction between the second terminal and the third terminal of the programming control unit 30 to blow the fuse EFUSE RES.

[0052] A first comparing unit 40, having a first input terminal receiving the comparison voltage, a second input terminal coupled to the first terminal of the fuse EFUSE RES, and a control terminal receiving a read control signal Sense_EN. The first comparing unit 40 is configured to: provide a first current to the fuse EFUSE RES;

[0053] When the read control signal Sense_EN is enabled, the voltage value of the first end of the fuse EFUSE RES is compared with the comparison voltage, and a comparison result signal Sense_OUT is output.

[0054] It can be seen that the present invention adopts dual enabling logic to ensure the reliability and safety of the system. It should be understood that the programming control signal Program_EN received by each fuse module is independent.

[0055] Specifically, when the programming control unit 30 pulls down the voltage of the second end of the fuse EFUSE RES to a low level, corresponding voltages may be generated across the two ends of the fuse EFUSE RES, facilitating comparison by the first comparison unit 40 .

[0056] In actual use, the programming power control signal Fsource is enabled only when programming is required, which is equivalent to cutting off the power supply for EFUSE programming at other times. Even if the programming control signal Program_EN glitches or the programming power supply jumps violently, EFUSE cannot be burned out.

[0057] When the programming control unit 30 raises the voltage of the second end of the fuse EFUSE RES to the preset voltage VCC, it can provide sufficient programming current for blowing the fuse EFUSE RES, thereby avoiding the EFUSE misprogramming problem caused by glitches and ensuring long-term reliable reading of the EFUSE.

[0058] In actual use, there are various ways to cut off the power supply for EFUSE programming while the chip is operating. As a specific embodiment, the EFUSE programming and reading circuit may further include a power supply control module (not shown in the figure), whose control terminal receives the programming control signal Program_EN. The power supply control module is configured to output the preset voltage VCC based on the programming control signal Program_EN. The preset voltage VCC includes a first preset voltage VCC1 and a second preset voltage VCC2. The first preset voltage VCC1 is output when the programming control signal Program_EN is disabled, and the second preset voltage VCC2 is output when the programming control signal Program_EN is enabled. The first preset voltage VCC1 is lower than the second preset voltage VCC2.

[0059] In this way, even if the programming control signal Program_EN glitches or the programming power supply jumps violently when the first comparison unit 40 performs comparison, the fuse EFUSE RES cannot obtain sufficient programming current, thereby avoiding the EFUSE misprogramming problem caused by the glitches and ensuring long-term reliable reading of the EFUSE.

[0060] Regarding the programming control unit 30, in a specific implementation, please refer to Figure 3 The programming control unit 30 includes a first NAND gate NAND1, a first inverter INV_Pro and a first NMOS transistor MN1;

[0061] A first input end of the first NAND gate NAND1 receives the programming control signal Program_EN, a second input end thereof receives the programming power supply control signal Fsource, and an output end thereof outputs a NAND result signal to the second end of the fuse EFUSE RES through the first inverter INV_Pro. A power supply end of the first inverter INV_Pro receives the preset voltage VCC. A drain of the first NMOS transistor MN1 is coupled to the first end of the fuse EFUSE RES, a gate thereof receives the programming power supply control signal Fsource, and a source thereof is grounded.

[0062] In the embodiment of the present invention, the size of the PMOS tube in the first inverter INV_Pro needs to be designed to be slightly larger to ensure that a fusing current of about 30 mA can pass instantaneously when programming EFUSE.

[0063] In a preferred embodiment, the first inverter INV_Pro is further configured to delay the NAND result signal.

[0064] It can be seen that the present invention avoids the second and third terminals of the programming control unit 30 from forming a path when the programming control signal Program_EN has a signal glitch by a short delay, further avoiding the EFUSE miswriting problem and ensuring long-term reliable reading of the EFUSE.

[0065] In another specific embodiment, please refer to Figure 4 The programming control unit 30 includes a first AND gate AND, a first inverter INV_Pro, a third inverter INV3 and a first NMOS transistor MN1;

[0066] A first input end of the first AND gate AND receives the programming control signal Program_EN, a second input end thereof receives the programming power supply control signal Fsource, and an output end thereof sequentially outputs a NAND result signal to the second end of the fuse EFUSE RES through the third inverter INV3 and the first inverter INV_Pro. A power supply end of the first inverter INV_Pro receives the preset voltage VCC. A drain of the first NMOS transistor MN1 is coupled to the first end of the fuse EFUSE RES, a gate thereof receives the programming power supply control signal Fsource, and a source thereof is grounded.

[0067] Obviously, the present invention also achieves delaying the NAND result signal by using two inverters connected in series. Of course, the present invention does not limit the delay method, and those skilled in the art can select a suitable circuit as needed.

[0068] In actual use, to save circuit area, please refer to Figure 3 , the first input terminal of each first comparison unit 40 receives the comparison voltage through the second comparison module 20 .

[0069] In the case where only the default comparison voltage is needed to determine the state of the EFUSE, a specific implementation method is provided. Figure 3 Each first comparison unit 40 includes a first tail current source I1, a second NMOS transistor MN2, a second NAND gate NAND2, and a second inverter INV2; the second comparison module 20 includes a second tail current source I2 and a third NMOS transistor MN3;

[0070] A first end of the first tail current source I1 receives the power supply voltage VDD, a second end of the first tail current source I1 is coupled to the drain of the second NMOS transistor MN2, a source of the second NMOS transistor MN2 is coupled to the first end of the fuse EFUSE RES, and a gate of the second tail current source I1 is coupled to the gate of the third NMOS transistor MN3. A first end of the second tail current source I2 receives the power supply voltage VDD, a second end of the first tail current source I2 is coupled to the drain of the third NMOS transistor MN3, the drain of the third NMOS transistor MN3 is also coupled to its gate, and a source of the second tail current source I2 is coupled to the output end of the comparison voltage output module 10.

[0071] A second end of the first tail current source I1 is coupled to a first input end of the second NAND gate NAND2 . A second input end of the second NAND gate NAND2 receives the read control signal Sense_EN, and an output end thereof outputs the comparison result signal Sense_OUT through the second inverter INV2 .

[0072] exist Figure 3 In the example of , the first comparison unit 40 and the second comparison module 20 may constitute a current comparator. When the fuse EFUSE RES is blown, the comparison result signal Sense_OUT is 1; otherwise, the comparison result signal Sense_OUT is 0.

[0073] However, before the chip leaves the factory, it is also necessary to test whether the resistance value of the EFUSE meets the standard. This ensures that even if the EFUSE resistance value fluctuates during long-term use, it can still be correctly read, ensuring reliability. In a specific embodiment, the comparison voltage includes a high margin voltage, a default comparison voltage, and a low margin voltage; the first control terminal of the comparison voltage output module 10 receives a high margin control signal, and the second control terminal receives a low margin control signal;

[0074] The comparison voltage output module 10 is configured to: output the high margin voltage when the high margin control signal is enabled; output the low margin voltage when the low margin control signal is enabled; otherwise, output the default comparison voltage.

[0075] In this case, the first comparison unit 40 reads the fuse EFUSE RES three times using three comparison voltages. If the comparison result signals Sense_OUT outputted three times are consistent, it indicates that the fuse EFUSE RES is in a normal blown state or a normal unblown state. If the three results are inconsistent, it means that the resistance value of the fuse EFUSE RES falls within the fuzzy range, and reliable reading cannot be guaranteed. The chip should be eliminated.

[0076] In a specific implementation, please refer to Figure 5 , the comparison voltage output module 10 includes a third tail current source I3, a high margin switch Q1, a first resistor R1, a second resistor R2 and a low margin switch Q2;

[0077] A first end of the third tail current source I3 receives the supply voltage VDD, and a second end of the third tail current source I3 is coupled to the first end of the first resistor R1 through the high margin switch Q1. The control end of the high margin switch Q1 receives the high margin control signal Hi_margin. The second end of the first resistor R1 is coupled to the first end of the second resistor R2. The second end of the second resistor R2 is coupled to the second end of the programming control unit 30. The low margin switch Q2 is connected in parallel with the second resistor R2. The control end of the low margin switch Q2 receives the low margin control signal Low_margin.

[0078] In this embodiment, the comparison voltage output module 10 outputs different comparison voltages by turning on and off the high margin switch Q1 and the low margin switch Q2 to complete the chip test before shipment.

[0079] exist Figure 5 In the example, the low margin switch Q2 is an NMOS transistor, the high margin switch Q1 is a PMOS transistor, and the high margin switch Q1 receives the high margin control signal Hi_margin via an inverter INV4. Of course, the present invention is not limited to this, and those skilled in the art can set the corresponding MOS transistor type and the state of the control signal as needed.

[0080] In addition, the present invention further provides an electronic device including any of the above-described EFUSE programming and reading circuits. For example, the electronic device may be an on-board control unit, an industrial controller, a wearable device, or other device requiring chip programming, although the present invention is not limited thereto.

[0081] In summary, the embodiments of the present invention provide a comparison voltage output module to output a comparison voltage. The first and second ends of the writing control unit in each fuse module are respectively coupled to the first and second ends of the fuse, and the third end thereof is grounded. When both the writing control signal and the writing power control signal are disabled, the writing control unit pulls down the voltage of the second end of the fuse to a low level to facilitate comparison by the first comparison unit. When both signals are enabled, the writing control unit pulls up the voltage of the second end of the fuse to a preset voltage and controls the conduction between the second and third ends of the writing control unit to blow the fuse in the fuse. The first comparison unit provides a first current to the fuse and compares the voltage value of the first end of the fuse with the comparison voltage when the reading control signal is enabled, and outputs a comparison result signal. The present invention only provides sufficient writing current when the fuse needs to be blown, avoiding the problem of miswriting and ensuring long-term and reliable reading of the EFUSE.

[0082] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be based on the scope defined by the claims.

Claims

1. An EFUSE programming and reading circuit, characterized in that: include: Comparison voltage output module, used for outputting comparison voltage; N fuse modules, where N is an integer greater than or equal to 1, and each fuse module includes: fuse; A burn control unit, having a first end and a second end coupled to the first end and the second end of the fuse, respectively, and a third end grounded. A first control end of the burn control unit receives a burn control signal, a second control end receives a burn power control signal, and a power supply end receives a preset voltage. The burn control unit is configured to: when both the burn control signal and the burn power control signal indicate disable, pull down the voltage at the second end of the fuse to a low level; when both the burn control signal and the burn power control signal indicate enable, pull up the voltage at the second end of the fuse to the preset voltage, and control conduction between the second end and the third end of the burn control unit to blow the fuse. a first comparing unit, wherein a first input terminal thereof receives the comparison voltage, a second input terminal thereof is coupled to the first terminal of the fuse, and a control terminal thereof receives a read control signal, wherein the first comparing unit is configured to: provide a first current to the fuse; When the read control signal is enabled, the voltage value of the first end of the fuse is compared with the comparison voltage, and a comparison result signal is output.

2. The EFUSE programming and reading circuit according to claim 1, wherein: The programming control unit includes a first NAND gate, a first inverter and a first NMOS tube; The first input end of the first NAND gate receives the writing control signal, the second input end thereof receives the writing power supply control signal, the output end thereof outputs a NAND result signal to the second end of the fuse through the first inverter, the power supply end of the first inverter receives the preset voltage, the drain of the first NMOS tube is coupled to the first end of the fuse, the gate thereof receives the writing power supply control signal, and the source thereof is grounded.

3. The EFUSE programming and reading circuit according to claim 2, wherein: The first inverter is further configured to delay the NAND result signal.

4. The EFUSE programming and reading circuit according to claim 1, wherein: The programming control unit includes a first AND gate, a first inverter, a third inverter and a first NMOS tube; The first input end of the first AND gate receives the writing control signal, the second input end thereof receives the writing power control signal, and the output end thereof sequentially outputs a NAND result signal to the second end of the fuse through the third inverter and the first inverter. The power supply end of the first inverter receives the preset voltage, the drain of the first NMOS tube is coupled to the first end of the fuse, the gate thereof receives the writing power control signal, and the source thereof is grounded.

5. The EFUSE programming and reading circuit according to claim 1, wherein: The first input terminal of each of the first comparison units receives the comparison voltage through the second comparison module; Each of the first comparison units includes a first tail current source, a second NMOS transistor, a second NAND gate, and a second inverter; the second comparison module includes a second tail current source and a third NMOS transistor; The first end of the first tail current source receives a power supply voltage, the second end of the first tail current source is coupled to the drain of the second NMOS transistor, the source of the second NMOS transistor is coupled to the first end of the fuse, and the gate of the second NMOS transistor is coupled to the gate of the third NMOS transistor. The first end of the second tail current source receives the power supply voltage, the second end of the second tail current source is coupled to the drain of the third NMOS transistor, the drain of the third NMOS transistor is also coupled to the gate, and the source of the second tail current source is coupled to the output end of the comparison voltage output module; The second end of the first tail current source is coupled to the first input end of the second NAND gate. The second input end of the second NAND gate receives the read control signal, and the output end thereof outputs the comparison result signal through the second inverter.

6. The EFUSE programming and reading circuit according to claim 5, wherein: The comparison voltage includes a high margin voltage, a default comparison voltage and a low margin voltage; the first control terminal of the comparison voltage output module receives a high margin control signal, and the second control terminal receives a low margin control signal; The comparison voltage output module is configured to: output the high margin voltage when the high margin control signal is enabled; output the low margin voltage when the low margin control signal is enabled; otherwise, output the default comparison voltage.

7. The EFUSE programming and reading circuit according to claim 6, wherein: The comparison voltage output module includes a third tail current source, a high margin switch, a first resistor, a second resistor and a low margin switch; The first end of the third tail current source receives the supply voltage, and the second end thereof is coupled to the first end of the first resistor through the high margin switch, the control end of the high margin switch receives the high margin control signal, the second end of the first resistor is coupled to the first end of the second resistor, the second end of the second resistor is coupled to the second end of the burning control unit, the low margin switch is connected in parallel with the second resistor, and the control end of the low margin switch receives the low margin control signal.

8. The EFUSE programming and reading circuit according to claim 7, wherein: The high margin switch is a PMOS tube, and the high margin switch receives the high margin control signal through an inverter.

9. The EFUSE programming and reading circuit according to claim 7, wherein: The low margin switch is an NMOS tube.

10. An electronic device, characterized in that: The device comprises the EFUSE programming and reading circuit according to any one of claims 1 to 9.

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