Pulse neural network distributed system based on adaptive time sequence granularity

Abstract

The invention provides a spiking neural network distributed system based on adaptive time sequence granularity, and relates to the technical field of computers, and the system comprises a spiking neural network splitting and cross-node communication module which is used for adaptively splitting a spiking neural network and supporting distributed communication on a GPU; the spiking neural network reconstruction module based on state-parameter decoupling is used for optimizing neuron internal state management during distributed deployment of the spiking neural network, and optimization comprises state parameter decoupling through a container and membrane potential cross-time sequence transmission through a serialization controller; and the timing sequence granularity self-adaptive spiking neural network communication module is used for dynamically adjusting the timing sequence granularity of the spiking neural network in a distributed environment and optimizing communication between GPU nodes according to the dynamically determined timing sequence granularity. By adopting the scheme, the time sequence granularity can be adaptively adjusted, the calculation efficiency and the communication overhead can be balanced, and the overall performance of the system can be improved.

Description

Technical Field

[0001] The present application relates to the field of computer technology, and in particular to a pulse neural network distributed system based on adaptive timing granularity. Background Art

[0002] Spiking Neural Networks (SNNs), as a third-generation neural network model, have attracted widespread attention in fields such as brain-inspired computing and low-power edge intelligence due to their biological plausibility and energy efficiency. Unlike traditional artificial neural networks, SNNs rely on the temporal dynamics of pulse signals to encode and process information. Neurons within the network only spike at specific moments, exhibiting significant temporal dependence and computational sparsity.

[0003] In practice, SNN models typically require multiple time-step iterations to complete information processing. Traditional SNN inference systems primarily employ two computational modes: the full-time-step model, in which each network module completes T iterations before passing the results to downstream modules; and the single-step immediate-pass model, in which each module immediately passes the results to downstream modules after completing a single step, requiring the entire network to iterate T times. Each model has its own advantages and disadvantages. The former reduces inter-module communication overhead but increases end-to-end latency, leading to "pipeline cavitation"—the idleness of resources caused by asynchrony between computation and data transfer. The latter, while potentially improving response speed and increasing computational unit utilization, significantly increases inter-module communication frequency and system overhead. Furthermore, SNNs contain neuronal state variables known as membrane potentials, which are stored internally and updated sequentially. In distributed deployments, this can prevent inter-time-step dependencies from being correctly passed in order, leading to timing synchronization issues. These significant differences from existing traditional artificial neural models make their computational logic incompatible and unsuitable for use with mainstream large-scale distributed ANN frameworks.

[0004] Current research and application of distributed computing systems for large-scale spiking neural networks is very immature. They typically employ fixed time-step processing strategies and are unable to dynamically adjust computational granularity based on network characteristics, hardware resources, and task requirements. This makes it difficult to achieve an optimal balance between computational efficiency and communication overhead in complex heterogeneous computing environments, particularly in complex distributed scenarios with multiple cards and nodes. Furthermore, current SNN distributed systems struggle to effectively handle differences in spike sparsity between different modules, resulting in wasted computing resources and unnecessary communication overhead. Summary of the Invention

[0005] The present application aims to solve one of the technical problems in the related art at least to a certain extent.

[0006] To this end, the purpose of this application is to propose a pulse neural network distributed system based on adaptive timing granularity, which can adaptively adjust the timing granularity, balance computing efficiency and communication overhead to improve the overall performance of the system, and adapt to the needs of various different distributed application scenarios on traditional GPUs or neuromorphic hardware, and provide support for high-order large model parallel training and reasoning such as model parallelism and pipeline parallelism.

[0007] To achieve the above objectives, the present application proposes a pulse neural network distributed system based on adaptive timing granularity, including a pulse neural network splitting and cross-node communication module, a pulse neural network reconstruction module based on state-parameter decoupling, and a pulse neural network communication module with adaptive timing granularity, wherein:

[0008] Spiking neural network splitting and cross-node communication module, which is used to adaptively split spiking neural networks and support distributed communication on GPUs;

[0009] A spiking neural network reconstruction module based on state-parameter decoupling is used to optimize the internal state management of neurons during the distributed deployment of spiking neural networks. The optimization includes state parameter decoupling through containers and cross-sequence transmission of membrane potential through serialized controllers.

[0010] The pulse neural network communication module with adaptive timing granularity is used to dynamically adjust the timing granularity of the pulse neural network in a distributed environment and optimize the communication between GPU nodes based on the dynamically determined timing granularity.

[0011] The pulse neural network distributed system based on adaptive timing granularity in the embodiment of the present application realizes adaptive splitting of the pulse neural network according to scale through the pulse neural network splitting and cross-node communication module, and supports its distributed communication on the GPU; through the pulse neural network reconstruction module based on state-parameter decoupling, it solves the key problem of internal state management of neurons in the pulse neural network during distributed deployment, thereby realizing distributed parallelism of various types of SNNs, thereby supporting multi-GPU and multi-node deployment of ultra-large-scale networks; through the pulse neural network communication module with adaptive timing granularity, it can adaptively select the optimal communication encapsulation granularity in the network, solving the limitations of the traditional fixed timing strategy of the pulse neural network in a distributed environment.

[0012] Additional aspects and advantages of the present application will be given in part in the description below, and in part will become apparent from the description below, or will be learned through practice of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] The above and / or additional aspects and advantages of the present application will become apparent and easily understood from the following description of the embodiments in conjunction with the accompanying drawings, in which:

[0014] Figure 1 A schematic diagram of the structure of a pulse neural network distributed system based on adaptive timing granularity provided in an embodiment of the present application.

[0015] Figure 2 This is an example diagram of the 4-card network layer splitting of ResNet50 in an embodiment of the present application;

[0016] Figure 3 This is an example diagram of the state-parameter decoupling of a spiking neuron according to an embodiment of the present application;

[0017] Figure 4 This is an example diagram of the SNodeSequential controller structure of an embodiment of the present application;

[0018] Figure 5 This is an example diagram of pipeline parallel calculation of the pulse time step subsequence according to an embodiment of the present application;

[0019] Figure 6 Schematic diagram of a multi-GPU comparison experiment of SNN video memory usage at different time steps in an embodiment of the present application;

[0020] Figure 7 This is a schematic diagram of the splitting effect of the pulse neural network communication module with adaptive timing granularity on Spiking-ResNet50 according to an embodiment of the present application;

[0021] Figure 8 This is an example diagram of the topology-aware partitioning steps in an embodiment of the present application;

[0022] Figure 9 This is an example of a pulse event communicator according to an embodiment of the present application. Figure 1 ;

[0023] Figure 10 This is an example of a pulse event communicator according to an embodiment of the present application. Figure 2 ;

[0024] Figure 11 This is an example diagram of an adaptive load balancer according to an embodiment of the present application;

[0025] Figure 12 This is an example diagram of an IF neuron according to an embodiment of the present application;

[0026] Figure 13 This is an example diagram of the SNode sequence container of an embodiment of the present application;

[0027] Figure 14 This is an example diagram of an adaptive time step controller according to an embodiment of the present application;

[0028] Figure 15This is an example diagram of a multi-stage pulse buffer according to an embodiment of the present application. DETAILED DESCRIPTION

[0029] The following describes in detail embodiments of the present application, examples of which are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are intended to be used to explain the present application, and should not be construed as limiting the present application.

[0030] The following describes a pulse neural network distributed system based on adaptive timing granularity according to an embodiment of the present application with reference to the accompanying drawings.

[0031] Embodiment 1 of the present application provides a pulse neural network distributed system based on adaptive timing granularity.

[0032] Figure 1 A schematic diagram of the structure of a pulse neural network distributed system based on adaptive timing granularity provided in an embodiment of the present application.

[0033] like Figure 1 As shown, the pulse neural network distributed system based on adaptive timing granularity includes:

[0034] Spiking neural network splitting and cross-node communication module, which is used to adaptively split spiking neural networks and support distributed communication on GPUs;

[0035] In this embodiment, the module implements adaptive splitting of spiking neural networks by scale and supports distributed communication on traditional GPUs or brain-like chips, specifically including:

[0036] (1) Network topology-aware model segmentation tool: Typical practical spiking neural networks are composed of dozens to hundreds of computational modules, and the modules usually form a simple sequential connection relationship, making them naturally suitable for model parallelization by dividing the network by layer. Based on the hierarchical structure and connection topology of the spiking neural network, this tool can identify natural split points in the network and divide the SNN model into multiple independently deployable sub-networks, ensuring that information transfer at the split boundaries is minimized.

[0037] Taking ResNet50 as an example, Figure 2 This is an example diagram of the 4-card network layer splitting of ResNet50.

[0038] (2) Asynchronous Pulse Event Communication Framework: This framework establishes an event-driven pulse information transmission mechanism that triggers event recording only when a neuron emits a pulse. It also supports packaging pulse outputs at any time step into a communication packet within a buffer and sending them uniformly via Remote Procedure Calls (RPCs), significantly reducing the amount of data exchanged between nodes. This framework includes pulse event serialization, priority scheduling, and batch processing mechanisms, enabling intelligent routing based on pulse timestamps and target neurons, reducing communication latency.

[0039] (3) Computational load adaptive balancing scheduler: Given a given computing hardware model, this scheduler can dynamically adjust computing resources and model partitioning strategies based on the activity and computational characteristics of neurons in each layer of the SNN to ensure load balancing across nodes. This technology monitors the resource utilization and pulse processing delay of each computing node in real time, and readjusts model partitioning during runtime to avoid computational bottlenecks. Furthermore, based on the number of hardware computing units and storage capacity, it can adaptively construct storage-optimal / computation-optimal multi-class model splitting strategies for user selection.

[0040] A spiking neural network reconstruction module based on state-parameter decoupling is used to optimize the internal state management of neurons during the distributed deployment of spiking neural networks. The optimization includes state parameter decoupling through containers and cross-sequence transmission of membrane potential through serialized controllers.

[0041] In this embodiment, this module solves the key problem of neuron internal state management in distributed deployment of spiking neural networks, specifically including:

[0042] (1) SNN simulation container for distributed modeling: To address the problem that dynamic states such as SNN neuron membrane potential cannot be correctly transmitted in the remote procedure call (RPC) framework, this container implements an innovative state-parameter decoupling architecture, decoupling the internal neuron state (such as membrane potential) from the parameters, encapsulating and managing it through a dedicated container SNode, and building a stateless parallel network structure. This design eliminates the need to store states within neurons, but instead dynamically obtains and updates membrane potentials through the container, thereby supporting efficient communication in a standard distributed framework.

[0043] In its implementation, the simulation container parameterizes the membrane potential V and extracts and stores its changes at the end of each time step. For multiple SNode neurons, the container designs storage space of appropriate length to ensure independent management of the state of each neuron. During the calculation of each time step, the container first passes the membrane potential V of the previous time step as input to the neuron. The neuron calculates whether to fire a pulse based on the input signal and the previous membrane potential state and updates the membrane potential. The container then extracts the updated membrane potential and stores it in the state snapshot for the next time step. In this way, the container achieves seamless state transfer and supports pipelined parallel computing across multiple nodes. Figure 3 An example diagram of state-parameter decoupling of spiking neurons.

[0044] The specific storage format of membrane potential has been changed as follows:

[0045] Self.V→V

[0046] Taking the spiking neuron SNode of the Integrate-and-Fire (IF) model as an example, the parameter propagation function is changed as follows:

[0047] X=SNode(X)→X,NewV=SNode(X,PreV)

[0048] (2) Serialization controller adapted to RPC framework: To be compatible with RPC multi-node computing of standard Sequential neural network, this embodiment is designed as follows Figure 4 The SNodeSequential controller shown in Figure 1 enables cross-time sequence transmission of membrane potential in the simulation container. Specifically, SNodeSequential first expands the input and output of the forward propagation function of spiking neurons, adding an additional parameter V for transmitting membrane potential. Next, a potential container is designed to store and manage the membrane potentials of all SNodes. At the end of each time step, the potential container extracts and saves the updated membrane potentials of all spiking neurons and transmits it back to the original neuron as the old state at the beginning of the next time step.

[0049] During the forward propagation process, SNodeSequential searches for all spiking neurons and non-spiking layers in the model, and dynamically takes over the state of the membrane potential of the spiking layer, while skipping the non-spiking layer. For each SNode layer (such as IFNode), it processes the membrane potential contained in the input and the current input respectively, decides whether to issue a pulse, and updates the state of the membrane potential. The updated membrane potential will be saved in the above-mentioned potential container and called cyclically in the next time step. In this way, the serialization module realizes differentiated processing of ordinary layers (such as convolutional layers, fully connected layers) and spiking neuron layers. This enables the reconstructed SNN network to be seamlessly integrated into the existing distributed computing framework.

[0050] To realize the automatic control of the above process, this module consists of the following steps:

[0051] 1) Computational Module Traversal and Identification: By traversing all modules of the neural network, we identify those containing spiking neurons (SNode). For these modules, we further examine their sublayers to ensure that each spiking neuron can support the propagation of the membrane potential (V). Specifically, we use the named_modules() method provided by PyTorch to traverse all modules in the network. For each module, we check whether it is of type nn.Sequential and contains an SNode layer. If these conditions are met, we proceed to further processing of the module.

[0052] 2) Dynamic Module Replacement: Replace the Sequential module containing spiking neurons with a custom SNodeSequential module. During this replacement process, ensure that the membrane potential of each spiking neuron is correctly transmitted and managed. Specifically, for each identified Sequential module, traverse its sublayers and replace each SNode with an instance that supports membrane potential input and output. The modified sublayers are reassembled into an SNodeSequential module, which replaces the original module.

[0053] The introduction of this serialization controller supports the automatic reconstruction and serialization of pulse neural network models to more efficiently adapt to distributed training or inference requirements without the need for users to manually adjust each module.

[0054] The pulse neural network communication module with adaptive timing granularity is used to dynamically adjust the timing granularity of the pulse neural network in a distributed environment and optimize the communication between nodes based on the dynamically determined timing granularity.

[0055] In this embodiment, the module solves the problem of adaptive timing granularity control of spiking neural networks in a distributed environment and overcomes the limitations of traditional fixed timing strategies, including:

[0056] (1) Dynamic timing granularity controller: This embodiment innovatively proposes an adaptive timing granularity control method between the “full time step mode” and the “single-step instant delivery mode”. This mechanism allows the system to dynamically determine the optimal time step packing number K (1≤K≤T, T is the total number of time steps) based on the computing resource status, network topology characteristics and task requirements, and divide the time step into Subsequences are generated to find the optimal balance between computational efficiency and communication overhead. Each computing node can independently determine its timing granularity, thereby achieving performance optimization in heterogeneous hardware environments. The specific steps on a specific single hardware are as follows:

[0057] Time step division: The time step sequence t = 1, 2, ..., T is packaged into multiple time step subsequences with intervals of K. After completing the calculation of each subsequence, the submodule deployed on the hardware passes the output to the module on the next hardware.

[0058] Pipeline filling and execution: At the beginning of training, the pipeline is gradually filled until all devices are in working state. For example, device D1 first processes the time step of the first subsequence, then passes the result to device D2, and so on. Once the pipeline is filled, all devices can execute their respective time step calculation tasks in parallel. Device D i When processing the i-th time subsequence S i At the same time, its downstream equipment D i+1 Already processing the i+1th time subsequence S i+1 . Figure 5 An example diagram of pipelined parallel computation of a sequence of pulse time steps.

[0059] (2) Multi-level buffered pulse time aggregation system: This embodiment designs an efficient pulse event buffering mechanism that can intelligently aggregate and compress pulse events generated within K consecutive time steps according to the dynamically determined time series granularity K. The system adopts a time window sliding strategy to minimize the amount of communication data while ensuring time series accuracy, and supports automatic selection of the optimal encoding method for pulse sequences with different sparsities. The specific mechanism includes

[0060] Hierarchical pulse event buffering structure: This embodiment designs a three-level buffering architecture consisting of a fast cache, an intermediate buffer, and a transmission buffer pool. The fast cache is located at the first level and is used to capture the original pulse events within a single time step; the intermediate buffer is the second level, which collects pulse events of consecutive time steps according to the currently determined timing granularity K; the transmission buffer pool is the third level, which finally encodes and packages the aggregated events for network transmission. This hierarchical design significantly reduces the impact of buffering operations on the main computing path and improves the overall system throughput.

[0061] Adaptive Time Window Sliding Mechanism: This embodiment implements a pulse event aggregation strategy based on dynamic time windows. The system dynamically adjusts the time window size based on the optimal time granularity K determined in real time, and uses a sliding window technique to smoothly transition between consecutive time steps. This mechanism supports real-time adjustment of the time granularity based on network conditions and computational load without interrupting computation.

[0062] Multi-mode pulse code compression technology: This embodiment designs multiple coding and compression algorithms suitable for different pulse sparsities and distribution characteristics. For highly sparse pulse trains, an event representation based on timestamps and neuron indices is used; for densely distributed pulses, bitmap-based compression coding is used; and for pulse patterns with spatiotemporal localization, differential coding combined with run-length compression is used. The system automatically selects the optimal coding method based on real-time pulse characteristics, minimizing the amount of transmitted data while ensuring decoding efficiency.

[0063] The combination of the above modules can efficiently process large-scale multi-node pulse event streams in distributed SNN environments, dynamically and adaptively divide timing accuracy, maximize computing unit utilization, and significantly reduce communication overhead.

[0064] The distributed pulse neural network system based on adaptive timing granularity of the embodiment of the present application includes a pulse neural network reconstruction module based on state-parameter decoupling, which can realize distributed parallelization of various types of SNNs, thereby supporting multi-GPU and multi-node deployment of ultra-large-scale networks, such as Figure 6 As shown in the figure, it can achieve large-scale model reasoning and training that cannot be completed on a single GPU through distributed splitting; it also includes a pulse neural network communication module with adaptive timing granularity, which can adaptively select the optimal communication encapsulation granularity in the network. When used alone, the splitting effect on Spiking-ResNet50 is shown in the figure. Figure 7 The full set of system parallel acceleration experiments in this embodiment covers multiple basic models such as Spiking-ResNet50, VGG16, and AlexNet, and the acceleration effects are shown in Tables 1, 2, and 3.

[0065] Table 1 Total simulation time consumption and time optimization acceleration ratio of Spiking-ResNet50 at different timing granularities

[0066]

[0067] Table 2 Total simulation time consumption and time optimization speedup ratio of Spiking-VGG16 at different timing granularities

[0068]

[0069] Table 3 Total simulation time consumption and time optimization acceleration ratio of Spiking-AlexNet at different timing granularities

[0070]

[0071] As shown in Tables 1, 2, and 3, we can see that in medium-sized networks, the speedup ratio can usually reach more than 3 times, and as the network scale continues to increase, the speedup ratio can reach as high as more than 5 times.

[0072] The test results of the pulse neural network distributed system based on adaptive timing granularity of this embodiment on the ultra-large-scale (a total of 1 billion synapses) network structure described in Table 4 are shown in Table 5.

[0073] Table 4 Structure of ultra-large-scale spiking neural network

[0074]

[0075] Table 5. Total simulation time consumption and time optimization speedup ratio of billion-synaptic spike neural network at different timing granularity

[0076]

[0077]

[0078] This embodiment of the application provides a distributed deployment method based on the Spiking-ResNet50 model. This model replaces the ReLU activation function of the traditional ResNet50 with spiking neurons, forming a deep spiking neural network with temporal dynamics. In this embodiment, four NVIDIA A100 GPUs are used for distributed deployment, each with 40GB of video memory and interconnected via NVLink.

[0079] (1) Implementation of Pulse Neural Network Splitting and Cross-node Communication Module

[0080] 1) Network topology-aware model segmentation

[0081] The Spiking-ResNet50 model consists of 1 input layer, 1 convolutional layer, 16 residual blocks (each residual block contains 3 convolutional layers), 1 global average pooling layer and 1 fully connected layer. Figure 8 The Spiking-ResNet50 model was segmented using the following steps and the following segmentation scheme was obtained:

[0082] Partition 1: input layer, first convolutional layer, 1st-4th residual blocks;

[0083] Partition 2: 5th-8th residual blocks;

[0084] Partition 3: 9th-12th residual blocks;

[0085] Partition 4: 13th-16th residual blocks, global average pooling layer, fully connected layer.

[0086] This partitioning method takes into account the computational complexity and parameter size of each residual block, ensuring load balancing among GPUs.

[0087] 2) To achieve efficient pulse information transmission, the following Figure 9 、 Figure 10 The event-driven communication framework shown in the figure has the following features:

[0088] Event-driven: events are recorded only when neurons fire spikes;

[0089] Batch processing: Send in batches after a certain number of events accumulate in the buffer;

[0090] Adaptive compression: selects the optimal encoding method based on pulse sparsity;

[0091] Asynchronous transmission: non-blocking communication is achieved through the RPC mechanism.

[0092] 3) Computational load adaptive balancing scheduler

[0093] To ensure load balancing among GPUs, the following Figure 11 The scheduling mechanism shown: By monitoring GPU utilization, memory usage, and processing latency, it automatically adjusts model partitions to balance the load. For example, after the initial partitioning of the Spiking-ResNet50 model, if it is detected that the processing latency of partition 1 is significantly higher than that of other partitions, the scheduler will automatically transfer the fourth residual block from partition 1 to partition 2, thereby optimizing overall performance.

[0094] (2) Implementation of the spiking neural network reconstruction module based on state-parameter decoupling

[0095] 1) Design the SNode container to manage the membrane potential state of the spiking neuron: Figure 12 As shown in Figure 3, taking the standard IF neuron as an example, this design decouples the neuron’s membrane potential state V from its internal state, enabling it to be passed as input and output parameters in a distributed environment.

[0096] 2) Adapt the serialization controller of RPC framework, the design is as follows Figure 13 The SNodeSequential container shown supports the compatibility of spiking neural networks with the standard RPC framework.

[0097] (3) Implementation of pulse neural network communication module with adaptive timing granularity

[0098] 1) Dynamic timing granularity controller, designed as Figure 14 The controller shown can dynamically adjust the timing granularity according to the computing environment and balance computing efficiency and communication overhead.

[0099] 2) A multi-level buffered pulse time aggregation system is designed to efficiently process pulse events across time steps. Figure 15 The three-level buffer system shown in the figure has the following advantages:

[0100] Fast cache: Efficiently processes pulse data in a single time step, reducing the latency of the main computation path;

[0101] Intermediate buffer: Aggregates pulse events at time granularity K to reduce encoding / decoding overhead;

[0102] Transmission pool: performs final encoding on the aggregated events and prepares them for network transmission;

[0103] Adaptive coding: Automatically select the optimal compression method based on pulse sparsity.

[0104] This example tested the performance of Spiking-ResNet50 at different time series granularities in a distributed deployment. For the image classification task on the CIFAR-10 dataset, with a total of 60,000 samples, four NVIDIA A100 GPUs were used, with a batch size of 64 and a total number of 64 time steps. The test results are as follows:

[0105] Timing granularity (K) Total inference time (seconds) 1 (single-step mode) 123.4 2 86.8 4 60.5 8 51.3 16 (optimal granularity) 38.2 32 42.3 64 (total time steps) 44.5

[0106] The results show that the best performance is achieved when the timing granularity K = 10, which is also the value at which the adaptive controller converges after dynamic adjustment. Compared with the fixed single-step mode, the adaptive scheme increases the overall system throughput by approximately 3.5 times, demonstrating the effectiveness of this embodiment.

[0107] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "example", "specific example" or "some examples" means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic expressions of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art can combine and combine different embodiments or examples described in this specification and features of different embodiments or examples without contradiction.

[0108] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of the technical features being referred to. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of such features. Throughout the description of this application, "plurality" means at least two, for example, two, three, etc., unless otherwise specifically defined.

[0109] Any process or method description in a flowchart or otherwise described herein may be understood to represent a module, segment or portion of code comprising one or more executable instructions for implementing the steps of a custom logical function or process, and the scope of the preferred embodiments of the present application includes alternative implementations in which functions may be performed out of the order shown or discussed, including performing functions in a substantially simultaneous manner or in the reverse order depending on the functions involved, which should be understood by those skilled in the art to which the embodiments of the present application belong.

[0110] The logic and / or steps represented in the flowcharts or otherwise described herein, for example, can be considered as a sequenced list of executable instructions for implementing the logical functions, and can be embodied in any computer-readable medium for use by, or in conjunction with, an instruction execution system, apparatus, or device (e.g., a computer-based system, a system including a processor, or other system that can fetch and execute instructions from an instruction execution system, apparatus, or device). For purposes of this specification, a "computer-readable medium" can be any device that can contain, store, communicate, propagate, or transport a program for use by, or in conjunction with, an instruction execution system, apparatus, or device. More specific examples (a non-exhaustive list) of computer-readable media include the following: an electrical connection with one or more wires (electronic devices), a portable computer disk cartridge (magnetic device), random access memory (RAM), read-only memory (ROM), erasable and programmable read-only memory (EPROM or flash memory), fiber optic devices, and a portable compact disc read-only memory (CDROM). Furthermore, the computer-readable medium may even be paper or other suitable medium on which the program is printed, since the program may be obtained electronically, for example, by optically scanning the paper or other medium and then editing, interpreting or processing it in another suitable manner if necessary, and then storing it in a computer memory.

[0111] It should be understood that various parts of the present application can be implemented using hardware, software, firmware, or a combination thereof. In the above embodiments, multiple steps or methods can be implemented using software or firmware stored in a memory and executed by a suitable instruction execution system. For example, if implemented using hardware, as in another embodiment, any one of the following technologies known in the art or a combination thereof can be used to implement: a discrete logic circuit having a logic gate circuit for implementing a logic function on a data signal, an application-specific integrated circuit having a suitable combination of logic gate circuits, a programmable gate array (PGA), a field programmable gate array (FPGA), etc.

[0112] Those skilled in the art will understand that all or part of the steps in the method of the above embodiment can be completed by instructing related hardware through a program, and the program can be stored in a computer-readable storage medium. When the program is executed, it includes one or a combination of the steps of the method embodiment.

[0113] In addition, the functional units in the various embodiments of the present application may be integrated into a processing module, or each unit may exist physically separately, or two or more units may be integrated into a module. The above-mentioned integrated module may be implemented in the form of hardware or in the form of a software functional module. If the integrated module is implemented in the form of a software functional module and sold or used as an independent product, it may also be stored in a computer-readable storage medium.

[0114] The storage medium mentioned above may be a read-only memory, a magnetic disk, or an optical disk, etc. Although the embodiments of the present application have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting the present application. Persons skilled in the art may make changes, modifications, substitutions, and variations to the above embodiments within the scope of the present application.

Claims

1. A pulse neural network distributed system based on adaptive timing granularity, characterized in that: It includes a pulse neural network splitting and cross-node communication module, a pulse neural network reconstruction module based on state-parameter decoupling, and a pulse neural network communication module with adaptive timing granularity, among which, The spiking neural network splitting and cross-node communication module is used to adaptively split the spiking neural network and support distributed communication on the GPU; The state-parameter decoupling-based spiking neural network reconstruction module is used to optimize the internal state management of neurons during the distributed deployment of the spiking neural network. The optimization includes achieving state parameter decoupling through containers and achieving cross-time sequence transmission of membrane potential through serialized controllers. The pulse neural network communication module with adaptive timing granularity is used to dynamically adjust the timing granularity of the pulse neural network in a distributed environment and optimize the communication between GPU nodes based on the dynamically determined timing granularity.

2. The system according to claim 1, wherein The pulse neural network splitting and cross-node communication module includes: A network topology-aware model segmentation tool that identifies natural split points in the network based on the hierarchical structure and connection topology of the spiking neural network (SNN). It then divides the spiking neural network (SNN) model into at least one independently deployed sub-network, minimizing information transfer at the split boundary. Asynchronous pulse event communication framework, used to establish an event-driven pulse information transmission mechanism, triggering event recording when neurons fire pulses; The computing load adaptive balancing scheduler is used to dynamically adjust computing resources and model segmentation strategies according to the activity and computing characteristics of neurons in each layer of SNN to ensure load balance among GPU nodes.

3. The system according to claim 1, wherein: The asynchronous pulse event communication framework includes pulse event serialization, priority scheduling and batch processing mechanisms. The asynchronous pulse event communication framework performs intelligent routing based on the timestamp of the pulse and the target neuron.

4. The system according to claim 1, wherein: The pulse neural network reconstruction module based on state-parameter decoupling includes: An SNN simulation container for distributed modeling, which is used to decouple the internal state of neurons from their parameters and encapsulate and manage the internal state of neurons through a dedicated container SNode; A serialization controller adapted to the RPC framework is used for RPC multi-node computing compatible with standard neural networks to achieve cross-time transmission of membrane potential.

5. The system according to claim 4, wherein: The SNN simulation container for distributed modeling is specifically used for: The membrane potential V is represented by a parameter and its change is extracted and stored at the end of each time step.

6. The system according to claim 4, wherein: The serialization controller adapted to the RPC framework is specifically used to: Traverse all modules of the spiking neural network and identify the modules containing spiking neurons SNode. For each identified module, check its sublayers to ensure that each spiking neuron supports the transmission of membrane potential V. The standard sequential module containing spiking neurons was replaced with a custom module that supports the transmission of membrane potential V.

7. The system according to claim 1, wherein: The pulse neural network communication module with adaptive timing granularity includes: Dynamic timing granularity controller, used to dynamically determine the optimal number of time step packaging K based on computing resource status, network topology characteristics and task requirements; The multi-level buffered pulse time aggregation system is used to adopt a time window sliding strategy to intelligently aggregate and compress pulse events generated within K consecutive time steps according to the dynamically determined optimal timing granularity K.

8. The system according to claim 1, wherein: The dynamic timing granularity controller is specifically used to: The total number of time steps T is divided into n = T / K subsequences, 1≤K≤T.

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