Brain-like calculation compiling method, device and equipment for multi-chip heterogeneous system

Abstract

The invention provides a brain-like calculation compiling method, device and equipment for a multi-chip heterogeneous system, and the method comprises the steps: describing a spiking neural network model based on a pre-defined spiking neural network dialect, and obtaining the dialect description of the spiking neural network model; analyzing the dialect description of the spiking neural network model to obtain key information of the spiking neural network model, optimizing the spiking neural network model based on the key information to obtain a target spiking neural network model, and determining an intermediate representation of the target spiking neural network model; and converting the intermediate representation of the target pulse neural network model to obtain instruction data matched with the multi-chip heterogeneous system. According to the method, the spiking neural network model is converted into the unified intermediate representation, so that the workload of brain-like calculation compiling can be reduced, the compiling complexity is reduced, and the execution efficiency and performance of brain-like calculation on a multi-chip heterogeneous system are improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of chips, in particular to a brain-computer computing compilation method, device and equipment for a multi-chip heterogeneous system. BACKGROUND

[0002] With the deep development of artificial intelligence technology, brain-computer computing, as a frontier field of simulating biological neural network mechanisms, is becoming a key direction to break through the bottleneck of traditional computing. In the practical application of brain-computer computing, the collaborative work of various processors and brain-computer chips has become the norm. However, these computing devices have significant differences in architecture and programming mode. The traditional brain-computer computing compilation method relies on the professional knowledge of developers and needs to consider the differences between different chips, which is time-consuming and complex, and affects the execution efficiency and performance of brain-computer computing on a multi-chip heterogeneous system. SUMMARY

[0003] The present application provides a brain-computer computing compilation method, device and equipment for a multi-chip heterogeneous system, to solve the defects of the prior art that the brain-computer computing compilation method relies on the professional knowledge of developers, needs to consider the differences between different chips, is time-consuming and complex, and affects the execution efficiency and performance of brain-computer computing on a multi-chip heterogeneous system.

[0004] The present application provides a brain-computer computing compilation method for a multi-chip heterogeneous system, comprising: Based on a pre-defined spiking neural network dialect, the spiking neural network model is described to obtain a dialect description of the spiking neural network model; The dialect description of the spiking neural network model is analyzed to obtain key information of the spiking neural network model, based on which the spiking neural network model is optimized to obtain a target spiking neural network model, and an intermediate representation of the target spiking neural network model is determined; The intermediate representation of the target spiking neural network model is converted to obtain instruction data compatible with the multi-chip heterogeneous system; the instruction data is used for resource scheduling and performance optimization of the multi-chip heterogeneous system.

[0005] In some embodiments, the spiking neural network model is described based on a pre-defined spiking neural network dialect to obtain a dialect description of the spiking neural network model, comprising: The neurons and synapses of the spiking neural network model are taken as nodes, and the connection relationship between the neurons and synapses is taken as edges to construct a topology graph of the spiking neural network model; Based on the topology graph of the spiking neural network model, the transmission direction and path of the pulse signal are determined to construct a computation graph of the spiking neural network model; Based on the spiking neural network dialect, a description of the computation graph is obtained, and a dialect description of the computation graph is obtained.

[0006] In some embodiments, the dialect description of the spiking neural network model is parsed to obtain key information of the spiking neural network model, including: Based on the dialect description of the spiking neural network model, key vocabularies are identified, including neuron type vocabularies, synapse type vocabularies, and network structure vocabularies; From the dialect description of the spiking neural network model, key descriptions are determined, including neuron attribute descriptions, synapse attribute descriptions, and network structure descriptions; The key descriptions are parsed to obtain parsed key descriptions; Based on the key vocabularies and the parsed key descriptions, key information is determined, including the types and attributes of neurons, the types and attributes of synapses, and the feature information of network structures.

[0007] In some embodiments, the spiking neural network model is optimized, including at least one of the following: The key parameters of the spiking neural network model are optimized, including neuron parameters and synapse weights; The computation graph of the spiking neural network model is optimized.

[0008] In some embodiments, the determination of the intermediate representation of the target spiking neural network model includes: Based on the spiking neural network dialect, the target spiking neural network model is described to obtain an intermediate representation of the target spiking neural network model.

[0009] In some embodiments, the conversion of the intermediate representation of the target spiking neural network model to instruction data compatible with the multi-chip heterogeneous system includes: A mapping relationship between the intermediate representation and the instruction set of the multi-chip heterogeneous system is determined; The intermediate representation is traversed to extract feature information of each neuron and feature information of each synapse of the target spiking neural network model; Based on the mapping relationship between the intermediate representation and the instruction set of the multi-chip heterogeneous system, and the feature information of each neuron and the feature information of each synapse, instruction data compatible with the multi-chip heterogeneous system is generated.

[0010] In some embodiments, the multi-chip heterogeneous system includes a general-purpose processor, a general-purpose graphics processor, and multiple brain-like chips; the multiple brain-like chips use a unified programming interface.

[0011] In some embodiments, the method further comprises: optimizing the instruction data to obtain optimized instruction data; the instruction data comprises instructions of general-purpose processors, instructions of general-purpose graphic processors and instructions of various brain-like chips; performing resource scheduling optimization and performance optimization on the multi-chip heterogeneous system based on the optimized instruction data.

[0012] The application further provides a brain-like computing compilation device for a multi-chip heterogeneous system, comprising: a description unit configured to describe a spiking neural network model based on a pre-defined spiking neural network dialect to obtain a dialect description of the spiking neural network model; a processing unit configured to analyze the dialect description of the spiking neural network model to obtain key information of the spiking neural network model, optimize the spiking neural network model based on the key information to obtain a target spiking neural network model, and determine an intermediate representation of the target spiking neural network model; a conversion unit configured to convert the intermediate representation of the target spiking neural network model to obtain instruction data compatible with the multi-chip heterogeneous system; the instruction data is used for resource scheduling and performance optimization on the multi-chip heterogeneous system.

[0013] The application further provides an electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor implements the brain-like computing compilation method for a multi-chip heterogeneous system as described above when executing the computer program.

[0014] The brain-like computing compilation method, device and equipment for a multi-chip heterogeneous system provided by the application can reduce the workload of brain-like computing compilation, reduce the complexity of compilation, and improve the execution efficiency and performance of brain-like computing on a multi-chip heterogeneous system by describing a spiking neural network model based on a pre-defined spiking neural network dialect to obtain a dialect description of the spiking neural network model, analyzing the dialect description of the spiking neural network model to obtain key information of the spiking neural network model, optimizing the spiking neural network model based on the key information to obtain a target spiking neural network model, determining an intermediate representation of the target spiking neural network model, and converting the intermediate representation of the target spiking neural network model to obtain instruction data compatible with the multi-chip heterogeneous system. BRIEF DESCRIPTION OF DRAWINGS

[0015] In order to more clearly illustrate the technical solutions in the present application or the prior art, the following will briefly introduce the drawings needed to be used in the embodiments or prior art description. Obviously, the drawings in the following description are only some embodiments of the present application, and for those skilled in the art, other drawings can also be obtained without creative labor.

[0016] Figure 1 is a flowchart of a brain-computer computing method for a multi-chip heterogeneous system provided by an embodiment of the present application.

[0017] Figure 2 is a flowchart of a pulse neural network model provided by an embodiment of the present application.

[0018] Figure 3 is a structural diagram of a brain-computer computing device for a multi-chip heterogeneous system provided by an embodiment of the present application.

[0019] Figure 4 is a structural diagram of an electronic device provided by an embodiment of the present application. DETAILED DESCRIPTION

[0020] In order to make the objects, technical solutions and advantages of the present application clearer, the following will combine the drawings in the present application to clearly and completely describe the technical solutions in the present application. Obviously, the described embodiments are only some of the embodiments of the present application, not all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor are within the protection scope of the present application.

[0021] Figure 1 is a flowchart of a brain-computer computing method for a multi-chip heterogeneous system provided by an embodiment of the present application. As shown in Figure 1 , a brain-computer computing method for a multi-chip heterogeneous system is provided, including the following steps: step 110, step 120 and step 130. The method flow steps are only as one possible implementation of the present application.

[0022] Step 110, based on a pre-defined pulse neural network dialect, describing a pulse neural network model to obtain a dialect description of the pulse neural network model.

[0023] Among them, the pulse neural network dialect refers to a pre-defined structured description language, including field-specific grammar, semantic constraints, keyword system, parameter specification and the like.

[0024] Optionally, the pulse neural network dialect at least includes the following keywords: NETWORK: declare a network; INPUT: Input layer, specify neuron number, encoder type; HIDDEN: Hidden layer, specify name, neuron number, brain-like computing model, parameters; OUTPUT: Output layer, specify neuron number, encoding method; CONNECT: Connect two layers, specify source layer, target layer, connection type (full connection, sparse, etc.), learning rule; TRAIN: Training configuration, specify optimizer, learning rate, training period, etc.

[0025] Among them, the spiking neural network model refers to a specific network instantiation structure, at least including: neuron type, network topology (number of layers / connection method), encoding mechanism (Poisson / rate / phase encoding), learning rule (gradient / backpropagation), hyperparameters (threshold / decay rate).

[0026] Optionally, the spiking neural network model includes an input layer, a hidden layer, and an output layer.

[0027] Step 120, parse the dialect description of the spiking neural network model to obtain the key information of the spiking neural network model, and based on the key information, optimize the spiking neural network model to obtain a target spiking neural network model, and determine the intermediate representation of the target spiking neural network model.

[0028] Optionally, specific operations or calculation modes in the spiking neural network model are optimized, such as updating nodes in dynamic signal flow, optimizing edge connections and other operations to improve the execution efficiency of the model.

[0029] Optionally, according to the actual needs of brain-like computing, the structure and parameters of the spiking neural network model are adjusted to realize more efficient calculation. For example, introduce sparse activation and event triggering mechanism, combined with dynamic gating, Top-K path selection and learnable activation threshold, on-demand calculation, path compression, and reduce the calculation load.

[0030] Optionally, the communication and storage of the computation graph of the spiking neural network model are optimized. For example, by adjusting the partitioning and communication strategy of the computation graph, reducing the amount of data and communication frequency transmitted between different chips or computing nodes, and reducing the communication overhead.

[0031] Optionally, the computation nodes, connection structure and data flow order of the computation graph of the spiking neural network model are optimized.

[0032] Specifically, if the connections in the computation graph are sparse, the sparse connection structure can be further optimized. By reorganizing the connections between neurons, the connections are made more efficient, reducing the computational overhead in sparse matrix operations. For example, by using sparse matrix storage and operation techniques, the synaptic weights of sparse connections are compressed, improving computational efficiency.

[0033] Specifically, it is checked whether there are invalid connections in the computation graph, and by analyzing the transmission of pulse signals on the connections, the invalid connections are removed to reduce unnecessary calculations.

[0034] Specifically, for a computation graph with cross-layer connections, such as residual connections, it is analyzed whether these cross-layer connections are reasonable and whether they have a positive effect on network performance. If it is found that certain cross-layer connections do not have a significant positive effect on network performance or have a negative effect, they can be adjusted or removed.

[0035] In some embodiments, the intermediate representation of the target spiking neural network model is determined, comprising: Based on the spiking neural network dialect, the target spiking neural network model is described to obtain the intermediate representation of the target spiking neural network model.

[0036] Optionally, the computation graph of the target spiking neural network model is determined, and the computation graph of the target spiking neural network model is described.

[0037] Step 130, converting the intermediate representation of the target spiking neural network model to obtain instruction data compatible with the multi-chip heterogeneous system; the instruction data is used for resource scheduling and performance optimization of the multi-chip heterogeneous system.

[0038] The multi-chip heterogeneous system integrates multiple different types of brain-like chips, aiming to improve computing power through the collaborative work of different brain-like chips.

[0039] In some embodiments, the multi-chip heterogeneous system includes: a general-purpose processor, a general-purpose graphics processor, and a plurality of brain-like chips; the plurality of brain-like chips adopt a unified programming interface.

[0040] The general-purpose processor is good at logical control and serial processing, and is suitable for processing complex instructions and sequential tasks; the general-purpose graphics processor has strong parallel computing power and can efficiently process large-scale parallel tasks; the brain-like chip has a unique neural synapse structure and uses pulse signal processing for calculation, which is more suitable for simulating the computing mode of biological neural networks.

[0041] Optionally, a multi-layer intermediate representation system (such as high-level, middle-level, and bottom-level) is used to realize gradual mapping from algorithm semantics to hardware instructions, improving compatibility.

[0042] Specifically, the high layer is used for defining a spiking neural network dialect, expressing sparsity and space-time parallelism of neurons, encapsulating a computing unit such as a neuron group, describing a spiking neural network model in a manner of a computation graph, and optimizing the computation graph, such as operator fusion.

[0043] Specifically, the middle layer is used for abstracting memory operations and matrix operations, converting memory layouts, optimizing implementation manners of specific operators, and optimizing memory access.

[0044] Specifically, the bottom layer is used for implementing conversion and optimization of specific instructions, and generating an efficient instruction sequence.

[0045] In the embodiment of the present application, the spiking neural network model is described based on a pre-defined spiking neural network dialect to obtain a dialect description of the spiking neural network model, the dialect description of the spiking neural network model is analyzed to obtain key information of the spiking neural network model, the spiking neural network model is optimized based on the key information to obtain a target spiking neural network model, and an intermediate representation of the target spiking neural network model is determined; and the intermediate representation of the target spiking neural network model is converted to obtain instruction data compatible with a multi-chip heterogeneous system, which can reduce the workload of brain-like computing compilation, reduce the complexity of compilation, and improve the execution efficiency and performance of brain-like computing on a multi-chip heterogeneous system.

[0046] Figure 2 A flowchart for describing the spiking neural network model is provided in the embodiment of the present application. As shown in Figure 2 In some embodiments, step 110 describes the spiking neural network model based on a pre-defined spiking neural network dialect to obtain a dialect description of the spiking neural network model, including: Step 111, constructing a topology graph of the spiking neural network model by taking neurons and synapses of the spiking neural network model as nodes and taking connection relationships between the neurons and the synapses as edges; Step 112, determining a transmission direction and a path of a spiking signal based on the topology graph of the spiking neural network model, and constructing a computation graph of the spiking neural network model; Step 113, describing the computation graph based on the spiking neural network dialect to obtain a dialect description of the computation graph.

[0047] Optionally, the neurons and the synapses are abstracted as nodes in the computation graph, the flow direction of data in the form of a spiking sequence between the nodes is determined, a forward propagation process from an input layer to an output layer, and a possible feedback connection are determined.

[0048] It can be understood that by constructing the topology graph of the spiking neural network model, determining the transmission direction and path of the spiking signal, and constructing the computation graph of the spiking neural network model, the connection relationship between neurons and synapses can be clearly and intuitively displayed, and the propagation mode of the spiking signal in the network is clear, which helps to understand the dynamic behavior and information processing process of the model; by using the spiking neural network dialect to describe the computation graph, the structure and behavior of the model can be expressed in a standardized and normalized language, so that the description of the model is more accurate and easy to understand, and convenience is provided for subsequent model implementation, optimization and verification.

[0049] In some embodiments, the dialect description of the spiking neural network model is parsed to obtain key information of the spiking neural network model, including: Based on the dialect description of the spiking neural network model, key vocabularies are identified, including neuron type vocabularies, synapse type vocabularies, and network structure vocabularies; From the dialect description of the spiking neural network model, key descriptions are determined, including neuron attribute descriptions, synapse attribute descriptions, and network structure descriptions; The key descriptions are parsed by syntax analysis to obtain parsed key descriptions; Based on the key vocabularies and the parsed key descriptions, key information is determined, including the type and attribute of the neuron, the type and attribute of the synapse, and the feature information of the network structure.

[0050] It can be understood that by identifying key vocabularies and determining key descriptions, the core features of the spiking neural network model can be accurately extracted from the dialect description, including the types, attributes of neurons and synapses, and the characteristics of the network structure; the key descriptions are parsed by syntax analysis to ensure the standardization and consistency of the parsing process, avoiding the subjectivity and randomness of human interpretation, and improving the reliability and accuracy of the parsing result; the obtained key information provides a solid foundation for subsequent model optimization, and helps the maintenance and expansion of the model.

[0051] In some embodiments, the spiking neural network model is optimized, including at least one of the following: The key parameters of the spiking neural network model are optimized, including neuron parameters and synapse weights; The computation graph of the spiking neural network model is optimized.

[0052] Optionally, the threshold of the neuron is adjusted appropriately according to the performance of the spiking neural network model. For example, if the network output is too sparse, the threshold can be appropriately reduced to make the neuron more likely to fire a pulse; otherwise, the threshold is increased.

[0053] Optionally, the membrane potential decay constant is changed to adjust the degree of memory of the neuron to the historical input signal according to the task requirements. For long-time sequence dependent tasks, the constant can be appropriately increased to retain more historical information.

[0054] Optionally, the number of neurons in the hidden layer is appropriately increased or decreased according to the performance and complexity of the spiking neural network model. If the network expression ability is insufficient, the number of neurons is increased; if overfitting occurs, the number of neurons is appropriately reduced.

[0055] Optionally, the connection mode between neurons is changed, such as changing part of the full connection to local connection or increasing the cross-layer connection, to change the information propagation path and improve the network performance.

[0056] Optionally, the computation graph of the spiking neural network model is optimized, such as operator fusion, operator splitting, operator rearrangement, etc., to reduce redundant operations and data transmission in the computation graph and improve the execution efficiency of the model.

[0057] Optionally, the vectorization operation (such as vector loading and storage, vector calculation, etc.) in the spiking neural network model is optimized to improve the efficiency and performance of the operation.

[0058] In some embodiments, the intermediate representation of the target spiking neural network model is converted to obtain instruction data compatible with the multi-chip heterogeneous system, including: determining the mapping relationship between the intermediate representation and the instruction set of the multi-chip heterogeneous system; traversing the intermediate representation to extract feature information of each neuron and feature information of each synapse of the target spiking neural network model; based on the mapping relationship between the intermediate representation and the instruction set of the multi-chip heterogeneous system, and the feature information of each neuron and the feature information of each synapse, generating instruction data compatible with the multi-chip heterogeneous system.

[0059] Optionally, according to the characteristics of the instruction set of the multi-chip heterogeneous system, the mapping rules between the intermediate representation and the instruction set are formulated. For example, the neuron state update operation in the intermediate representation is mapped to specific arithmetic operation instructions and logic operation instructions; the pulse transmission operation is mapped to data transmission instructions and conditional jump instructions, etc.

[0060] Optionally, the instruction data structure compatible with the multi-chip heterogeneous system is created, including instruction storage space, data buffer, state register, etc.

[0061] The instruction data is optimized to obtain optimized instruction data; the instruction data includes instructions of general-purpose processors, instructions of general-purpose graphics processors, and instructions of multiple types of brain chips. Based on the optimized instruction data, resource scheduling optimization and performance optimization are performed on the multi-chip heterogeneous system.

[0062] Optionally, the generated instruction data is optimized, including instruction scheduling, instruction fusion, instruction redundancy elimination, etc. For example, by adjusting the execution order of instructions, reducing the data correlation between instructions, and improving the parallel execution degree of instructions; fusing multiple related instructions to reduce the number of instructions and the overhead of instruction execution; removing repeated instructions or redundant operations to improve the efficiency of instruction data.

[0063] Optionally, the memory access mode is optimized, such as using data prefetching, data reuse, etc., to improve the memory access efficiency.

[0064] Optionally, according to the characteristics of the target hardware in the system, instruction scheduling, register allocation, etc. are optimized to fully utilize the computing power and performance of the hardware, including reordering and scheduling general processor instructions to reduce instruction correlation and pipeline stall, reasonable allocation and scheduling of thread blocks and threads in general graphics processors to improve parallel computing efficiency.

[0065] Optionally, the memory layout of data is optimized, such as data alignment, data blocking, etc. to improve the storage efficiency and access speed of data in memory. Through reasonable memory layout optimization, the cache mechanism and memory hierarchy of hardware can be fully utilized to further improve the performance of brain-inspired computing.

[0066] The following describes the brain-inspired computing compilation device for a multi-chip heterogeneous system provided by the embodiments of the present application. The brain-inspired computing compilation device for a multi-chip heterogeneous system described below can be mutually corresponding and referenced with the brain-inspired computing compilation method for a multi-chip heterogeneous system described above.

[0067] Figure 3 The structure diagram of the brain-inspired computing compilation device for a multi-chip heterogeneous system provided by the embodiments of the present application is shown in Figure 3 The brain-inspired computing compilation device for a multi-chip heterogeneous system includes: A description unit 310 is configured to describe the spiking neural network model based on the pre-defined spiking neural network dialect, to obtain the dialect description of the spiking neural network model. A processing unit 320 is configured to analyze the dialect description of the spiking neural network model to obtain the key information of the spiking neural network model, and optimize the spiking neural network model based on the key information to obtain a target spiking neural network model and determine the intermediate representation of the target spiking neural network model. The conversion unit 330 is configured to convert the intermediate representation of the target spiking neural network model to obtain instruction data compatible with the multi-chip heterogeneous system, and the instruction data is used for resource scheduling and performance optimization of the multi-chip heterogeneous system.

[0068] Optionally, the spiking neural network model is described based on a predefined spiking neural network dialect to obtain a dialect description of the spiking neural network model, including: A topology graph of the spiking neural network model is constructed by taking neurons and synapses of the spiking neural network model as nodes and taking a connection relationship between the neurons and the synapses as edges; Based on the topology graph of the spiking neural network model, a transmission direction and a path of a spiking signal are determined, and a computation graph of the spiking neural network model is constructed; The computation graph is described based on the spiking neural network dialect to obtain a dialect description of the computation graph.

[0069] Optionally, the dialect description of the spiking neural network model is parsed to obtain key information of the spiking neural network model, including: Based on the dialect description of the spiking neural network model, key vocabularies are identified, and the key vocabularies include neuron type vocabularies, synapse type vocabularies, and network structure vocabularies; Key descriptions are determined from the dialect description of the spiking neural network model, and the key descriptions include neuron attribute descriptions, synapse attribute descriptions, and network structure descriptions; The key descriptions are subjected to syntax analysis to obtain parsed key descriptions; Based on the key vocabularies and the parsed key descriptions, key information is determined, and the key information includes types and attributes of neurons, types and attributes of synapses, and feature information of network structures.

[0070] Optionally, the spiking neural network model is optimized, including at least one of the following: Key parameters of the spiking neural network model are optimized, and the key parameters include neuron parameters and synapse weights; The computation graph of the spiking neural network model is optimized.

[0071] Optionally, the intermediate representation of the target spiking neural network model is determined, including: The target spiking neural network model is described based on a spiking neural network dialect to obtain an intermediate representation of the target spiking neural network model.

[0072] Optionally, the intermediate representation of the target spiking neural network model is converted to obtain instruction data compatible with the multi-chip heterogeneous system, including: A mapping relationship between the intermediate representation and an instruction set of the multi-chip heterogeneous system is determined; Traverse the intermediate representation, extract feature information of each neuron of the target spiking neural network model, and feature information of each synapse; Based on the mapping relationship between the intermediate representation and the instruction set of the multi-chip heterogeneous system, and the feature information of each neuron and the feature information of each synapse, generate instruction data compatible with the multi-chip heterogeneous system.

[0073] Optionally, the multi-chip heterogeneous system comprises: a general-purpose processor, a general-purpose graphics processor, and a plurality of brain-like chips; the plurality of brain-like chips adopt a unified programming interface.

[0074] Optionally, the brain-like computing compilation device for the multi-chip heterogeneous system further comprises an optimization unit, configured to: Optimize the instruction data to obtain optimized instruction data; the instruction data comprises instructions of the general-purpose processor, instructions of the general-purpose graphics processor, and instructions of the plurality of brain-like chips; Based on the optimized instruction data, perform resource scheduling optimization and performance optimization on the multi-chip heterogeneous system.

[0075] It should be noted that the brain-like computing compilation device for the multi-chip heterogeneous system provided by the embodiment of the present application can realize all the method steps realized by the brain-like computing compilation method for the multi-chip heterogeneous system provided by the method embodiment, and can achieve the same technical effects. Therefore, the same parts and beneficial effects of the method embodiment in this embodiment will not be described in detail.

[0076] Figure 4 The structure schematic diagram of the electronic device provided by the embodiment of the present application is shown in Figure 4 As shown in the figure, the electronic device can include: a processor (processor) 410, a communication interface (Communications Interface) 420, a memory (memory) 430 and a communication bus 440, wherein the processor 410, the communication interface 420, the memory 430 complete the communication among each other through the communication bus 440. The processor 410 can call the logic instructions in the memory 430 to execute the brain-like computing compilation method for the multi-chip heterogeneous system, which comprises: based on the pre-defined spiking neural network dialect, describing the spiking neural network model to obtain the dialect description of the spiking neural network model; analyzing the dialect description of the spiking neural network model to obtain the key information of the spiking neural network model, based on the key information, optimizing the spiking neural network model to obtain the target spiking neural network model, determining the intermediate representation of the target spiking neural network model; converting the intermediate representation of the target spiking neural network model to obtain instruction data compatible with the multi-chip heterogeneous system; the instruction data is used for resource scheduling and performance optimization of the multi-chip heterogeneous system.

[0077] In addition, the logic instructions in the memory 430 described above can be implemented in the form of a software function unit and sold or used as an independent product, and can be stored in a computer readable storage medium. Based on such understanding, the technical solutions of the present application essentially or the parts that contribute to the prior art or parts of the technical solutions can be embodied in the form of a software product. The computer software product is stored in a storage medium, and includes several instructions to make a computer device (which can be a personal computer, a server, or a network device, etc.) execute all or part of the steps of the methods described in the various embodiments of the present application. The aforementioned storage medium includes: a U disk, a mobile hard disk, a read-only memory (ROM, Read-Only Memory), a random access memory (RAM, Random Access Memory), a magnetic disk or an optical disk, and various media that can store program codes.

[0078] The device embodiments described above are only schematic, wherein the units illustrated as separate components can or can not be physically separate, and the components illustrated as units can or can not be physical units, i.e., can be located in one place, or can be distributed on multiple network units. Part or all of the modules can be selected to achieve the purpose of the embodiment according to actual needs. Those skilled in the art can understand and implement without creative labor.

[0079] From the description of the above embodiments, those skilled in the art can clearly understand that each embodiment can be realized by means of software and necessary general hardware platform, and of course can also be realized by hardware. Based on such understanding, the above technical solutions essentially or the parts that contribute to the prior art can be embodied in the form of a software product. The computer software product can be stored in a computer readable storage medium, such as ROM / RAM, magnetic disk, optical disk, etc., and includes several instructions to make a computer device (which can be a personal computer, a server, or a network device, etc.) execute the methods described in each embodiment or some parts of the embodiment.

[0080] Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present application, and not to limit them; although the present application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that: it can still modify the technical solutions recorded in the foregoing embodiments, or make equivalent replacement to some technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present application.

Claims

1. A brain-inspired computing compilation method for a multi-chip heterogeneous system, characterized in that, The method comprises the following steps: a predefined pulse neural network dialect is used to describe a pulse neural network model, and a dialect description of the pulse neural network model is obtained; the dialect description of the pulse neural network model is analyzed, and key information of the pulse neural network model is obtained; the pulse neural network model is optimized based on the key information, a target pulse neural network model is obtained, and an intermediate representation of the target pulse neural network model is determined; the intermediate representation of the target pulse neural network model is converted, and instruction data suitable for the multi-chip heterogeneous system is obtained; the instruction data is used for resource scheduling and performance optimization of the multi-chip heterogeneous system. 2.The brain-inspired computing compilation method for multi-chip heterogeneous system according to claim 1, wherein, The method comprises the following steps: a topology graph of the pulse neural network model is constructed by taking neurons and synapses of the pulse neural network model as nodes and taking connection relationships between the neurons and the synapses as edges; a calculation graph of the pulse neural network model is constructed by determining a transmission direction and a path of a pulse signal based on the topology graph of the pulse neural network model; the calculation graph is described based on the pulse neural network dialect, and a dialect description of the calculation graph is obtained. 3.The brain-inspired computing compilation method for multi-chip heterogeneous system of claim 1, wherein, The method comprises the following steps: key vocabularies are identified based on the dialect description of the pulse neural network model, the key vocabularies comprising neuron type vocabularies, synapse type vocabularies and network structure vocabularies; key descriptions are determined from the dialect description of the pulse neural network model, the key descriptions comprising neuron attribute descriptions, synapse attribute descriptions and network structure descriptions; the key descriptions are subjected to syntax analysis, and analyzed key descriptions are obtained; key information is determined based on the key vocabularies and the analyzed key descriptions, the key information comprising types and attributes of neurons, types and attributes of synapses and feature information of network structures. 4.The brain-inspired computing compilation method for multi-chip heterogeneous system according to claim 1, wherein, The pulse neural network model is optimized by at least one of the following methods: key parameters of the pulse neural network model are optimized, the key parameters comprising neuron parameters and synapse weights; the calculation graph of the pulse neural network model is optimized.

5. The brain-inspired computing compilation method for multi-chip heterogeneous system according to claim 1, wherein, The method comprises the following steps: the target pulse neural network model is described based on the pulse neural network dialect, and an intermediate representation of the target pulse neural network model is obtained.

6. The brain-inspired computing compilation method for multi-chip heterogeneous system according to claim 1, wherein, The method comprises the following steps: a mapping relationship between the intermediate representation and an instruction set of the multi-chip heterogeneous system is determined; feature information of each neuron and feature information of each synapse of the target pulse neural network model are extracted by traversing the intermediate representation; generate instruction data compatible with the multi-chip heterogeneous system based on the mapping relationship between the intermediate representation and an instruction set of the multi-chip heterogeneous system, and the feature information of each neuron and the feature information of each synapse.

7. The brain-inspired computing compilation method for multi-chip heterogeneous system according to any one of claims 1-6, characterized in that, The multi-chip heterogeneous system comprises a general-purpose processor, a general-purpose graphics processor, and a plurality of brain-like chips; and the plurality of brain-like chips adopt a unified programming interface. 8.The brain-inspired computing compilation method for multi-chip heterogeneous system according to claim 7, wherein, The method further comprises: optimizing the instruction data to obtain optimized instruction data; the instruction data comprises instructions of the general-purpose processor, instructions of the general-purpose graphics processor, and instructions of the plurality of brain-like chips; performing resource scheduling optimization and performance optimization on the multi-chip heterogeneous system based on the optimized instruction data.

9. A brain-inspired computing compiling device for a multi-chip heterogeneous system, comprising: comprises: a description unit configured to describe a spiking neural network model based on a predefined spiking neural network dialect to obtain a dialect description of the spiking neural network model; a processing unit configured to analyze the dialect description of the spiking neural network model to obtain key information of the spiking neural network model, optimize the spiking neural network model based on the key information, obtain a target spiking neural network model, and determine an intermediate representation of the target spiking neural network model; a conversion unit configured to convert the intermediate representation of the target spiking neural network model to obtain instruction data compatible with the multi-chip heterogeneous system; the instruction data is used for resource scheduling and performance optimization on the multi-chip heterogeneous system.

10. An electronic device comprising a memory, a processor, and a computer program stored on the memory and running on the processor, characterized in that, The processor executes the computer program to implement the brain-like computing compilation method for the multi-chip heterogeneous system according to any one of claims 1 to 8.

Images