Memory, programming method and programming verification method of memory, and memory system

Abstract

The embodiment of the invention discloses a memory, a programming method and a programming verification method of the memory, and a memory system. The programming verification method comprises the following steps: acquiring an ith verification result of an ith programming verification operation; wherein the programming state range verified by the ith programming verification operation is from the nth state to the (n + k) th state, i and n are positive integers, k is a natural number, and the (n + k) th state is smaller than or equal to the highest programming state of the memory; according to the verification sub-result of the nth state and the verification sub-result of the (n + k) th state in the ith verification result, determining a programming state range needing to be verified by the (i + 1) th programming verification operation; and executing the (i + 1)-th programming verification operation according to the determined programming state range required to be verified by the (i + 1)-th programming verification operation.

Description

[0001] This application is a divisional application of the Chinese patent application with the application date of August 31, 2021, application number 202180003091.2, and invention name “Memory, memory programming method and programming verification method, memory system”. Technical Field

[0002] The embodiments of the present disclosure relate to, but are not limited to, the field of semiconductors, and in particular to a memory, a programming method and a programming verification method for a memory, and a memory system. Background Art

[0003] Flash memory is widely used as a storage medium in portable electronic devices such as mobile phones and digital cameras. Flash memory typically uses a single-transistor memory cell, which allows for high memory density, high reliability, and low power consumption. By programming a charge storage structure (e.g., a floating gate or charge trap) or other physical phenomena (e.g., phase change or ferroelectricity), the change in the threshold voltage of the memory cell determines the data state (e.g., data value) of each memory cell.

[0004] In related technologies, after applying programming pulses to memory for programming, a program-verify operation is required. The number of programming pulses applied and the number of program-verify operations performed are important factors determining programming time. Therefore, how to shorten programming time while ensuring programming quality has become an urgent problem to be solved. Summary of the Invention

[0005] Embodiments of the present disclosure provide a memory, a memory programming method and a program verification method, and a memory system.

[0006] According to a first aspect of an embodiment of the present disclosure, a program verification method for a memory is provided, comprising:

[0007] Obtaining an i-th verification result of an i-th program-verification operation; wherein the programming state range verified by the i-th program-verification operation is from the n-th state to the n+k-th state, i and n are positive integers, k is a natural number, and the n+k-th state is less than or equal to the highest programming state of the memory;

[0008] determining a programming state range to be verified in an (i+1)th program-verification operation according to a verification sub-result of the nth state and a verification sub-result of the (n+k)th state in the (i)th verification result;

[0009] The (i+1)th program-verification operation is performed according to the determined program state range that needs to be verified in the (i+1)th program-verification operation.

[0010] In some embodiments, determining the programming state range to be verified for the (i+1)th program-verification operation based on the verification sub-result of the nth state and the verification sub-result of the (n+k)th state in the (i)th verification result includes:

[0011] determining, according to a verification sub-result of the nth state in the i-th verification result, a lowest programming state to be verified in the (i+1)th program-verification operation;

[0012] A highest programming state to be verified in the (i+1)th program-verification operation is determined according to a verification sub-result of the (n+k)th state in the (i)th verification result.

[0013] In some embodiments, the verification sub-result of the nth state in the i-th verification result includes: i-th statistical data of the nth state, used to count the number of failed bits programmed to the nth state;

[0014] The determining, based on the verification sub-result of the n-th state in the i-th verification result, a lowest programming state to be verified in the (i+1)-th program-verification operation includes:

[0015] determining a number of failed bits for programming the nth state based on an i-th statistical data of the nth state;

[0016] When the number of failed bits programmed for the nth state is less than a first preset value, determining that the lowest programmed state to be verified in the (i+1)th program-verification operation is the (n+1)th state;

[0017] When the number of failed bits in programming the nth state is greater than or equal to the first preset value, determining that the lowest programming state to be verified in the (i+1)th program-verification operation is the nth state;

[0018] or,

[0019] When a ratio of the number of failed bits programmed to the nth state to the number of bits whose target state is the nth state is less than a first preset ratio, determining that the lowest programmed state to be verified in the (i+1)th program-verification operation is the (n+1)th state;

[0020] When the ratio of the number of failed bits programmed to the nth state to the number of bits whose target state is the nth state is greater than or equal to the first preset ratio, the lowest programmed state to be verified in the (i+1)th program verification operation is determined to be the nth state.

[0021] In some embodiments, the program verification method further includes:

[0022] Obtaining the number of cycles of the memory cell to be programmed;

[0023] According to the number of cycles, a value range of the first preset value or a value range of the first preset ratio is determined.

[0024] In some embodiments, the value range of the first preset value is within the range allowed by the error correction mechanism of the error correction code performed on the memory.

[0025] In some embodiments, the verification sub-result of the n+kth state in the i-th verification result includes: i-th statistical data of the n+kth state, used to count the number of successful bits programmed into the n+kth state;

[0026] The determining, based on the verification sub-result of the n+kth state in the i-th verification result, the highest programming state to be verified in the (i+1)th program-verification operation includes:

[0027] determining a number of successful bits programmed into the n+k th state according to an i-th statistical data of the n+k th state;

[0028] When the number of successful bits programmed for the n+kth state is greater than a second preset value, and the n+kth state is less than the highest programmed state of the memory, determining that the highest programmed state to be verified in the i+1th program-verification operation is the n+k+1th state;

[0029] When the number of successful bits programmed for the n+kth state is less than or equal to the second preset value, determining that the highest programmed state to be verified in the (i+1)th program-verification operation is the (n+k)th state;

[0030] or,

[0031] When a ratio of the number of successful bits programmed to the n+kth state to the number of bits whose target state is the n+kth state is greater than a second preset ratio, determining that the highest programmed state to be verified in the (i+1)th program-verification operation is the (n+k+1)th state;

[0032] When the ratio of the number of successful bits programmed to the n+kth state to the number of bits whose target state is the n+kth state is less than or equal to the second preset ratio, the highest programmed state to be verified in the (i+1)th program verification operation is determined to be the n+kth state.

[0033] In some embodiments, the program verification method further includes:

[0034] Obtaining a step size and / or a programming voltage slope of incremental step pulse programming; determining a value range of the second preset value or the second preset ratio based on the step size and / or the programming voltage slope; wherein the programming verification method is applied to an incremental step pulse programming method;

[0035] or,

[0036] Obtaining the number of cycles of the memory cell to be programmed; and determining a value range of the second preset value or a value range of the second preset ratio according to the number of cycles.

[0037] In some embodiments, the second preset ratio ranges from 2% to 3%.

[0038] In some embodiments, determining the programming state range to be verified for the (i+1)th program-verification operation based on the verification sub-result of the nth state and the verification sub-result of the (n+k)th state in the (i)th verification result includes:

[0039] Sampling the verification sub-result of the n-th state and the verification sub-result of the n+k-th state in the i-th verification result respectively to obtain i-th sampling statistical data of the n-th state and i-th sampling statistical data of the n+k-th state;

[0040] determining, based on i-th sampling statistical data of the n-th state, a lowest programming state to be verified in the (i+1)th programming-verification operation;

[0041] A highest programmed state that needs to be verified in the (i+1)th program-verification operation is determined based on the i-th sampling statistical data of the (n+k)-th state.

[0042] According to a second aspect of an embodiment of the present disclosure, a memory programming method is provided, comprising:

[0043] Applying an (i+1)th programming pulse to a memory cell to be programmed in the memory;

[0044] During the application of the (i+1)th programming pulse, counting the number of failed bits in programming the nth state and programming the (n+k)th state in the (i)th programming operation based on the verification sub-result of the nth state and the verification sub-result of the (n+k)th state in the (i)th verification result of the (i)th programming verification operation to obtain an (i)th counting result; wherein the programming states verified by the (i)th programming verification operation range from the (n)th state to the (n+k)th state, i and n are positive integers, k is a natural number, and the (n+k)th state is less than or equal to the highest programming state of the memory;

[0045] Determining a programming state range to be verified for an (i+1)th programming verification operation based on the (i)th counting result; wherein the programming state range to be verified for the (i)th programming verification operation is from the (n)th state to the (n+k)th state, where i and n are positive integers, k is a natural number, and the (n+k)th state is less than or equal to the highest programming state of the memory;

[0046] The (i+1)th program-verification operation is performed according to the determined program state range that needs to be verified in the (i+1)th program-verification operation.

[0047] In some embodiments, the i-th counting result includes: the number of failed bits programmed to the n-th state in the i-th programming operation;

[0048] The step of determining a programming state range to be verified for an (i+1)th program-verification operation according to the (i)th counting result includes:

[0049] When the number of failed bits programmed for the nth state is less than a first preset value, determining that the lowest programmed state to be verified in the (i+1)th program-verification operation is the (n+1)th state;

[0050] When the number of failed bits in programming the nth state is greater than or equal to the first preset value, determining that the lowest programming state to be verified in the (i+1)th program-verification operation is the nth state;

[0051] or,

[0052] When a ratio of the number of failed bits programmed to the nth state to the number of bits whose target state is the nth state is less than a first preset ratio, determining that the lowest programmed state to be verified in the (i+1)th program-verification operation is the (n+1)th state;

[0053] When the ratio of the number of failed bits programmed to the nth state to the number of bits whose target state is the nth state is greater than or equal to the first preset ratio, the lowest programmed state to be verified in the (i+1)th program verification operation is determined to be the nth state.

[0054] In some embodiments, the i-th counting result includes: the number of failed bits programmed to the n+k-th state in the i-th programming operation;

[0055] The step of determining a programming state range to be verified for an (i+1)th program-verification operation according to the (i)th counting result includes:

[0056] When the number of successful bits programmed for the n+kth state is greater than a second preset value, and the n+kth state is less than a highest programmed state of the memory, determining that the highest programmed state to be verified in the i+1th program-verification operation is the n+k+1th state;

[0057] When the number of successful bits programmed for the n+kth state is less than or equal to the second preset value, determining that the highest programmed state to be verified in the (i+1)th program-verification operation is the (n+k)th state;

[0058] or,

[0059] When a ratio of the number of successful bits programmed to the n+kth state to the number of bits whose target state is the n+kth state is greater than a second preset ratio, determining that the highest programmed state to be verified in the (i+1)th program-verification operation is the (n+k+1)th state;

[0060] When the ratio of the number of successful bits programmed to the n+kth state to the number of bits whose target state is the n+kth state is less than or equal to the second preset ratio, the highest programmed state to be verified in the (i+1)th program verification operation is determined to be the n+kth state.

[0061] In some embodiments, counting the number of failed bits in programming the nth state and programming the n+kth state in the i-th programming operation according to the verification sub-result of the n-th state and the verification sub-result of the n+k-th state in the i-th verification result of the i-th program-verification operation to obtain the i-th counting result includes:

[0062] Sampling the verification sub-result of the n-th state and the verification sub-result of the n+k-th state in the i-th verification result respectively to obtain i-th sample data of the n-th state and i-th sample data of the n+k-th state;

[0063] According to the i-th sampling sample data of the n-th state and the i-th sampling sample data of the n+k-th state, the number of failed bits of programming of the n-th state and programming of the n+k-th state in the i-th programming operation is counted to obtain the i-th counting result.

[0064] According to a third aspect of an embodiment of the present disclosure, there is provided a memory, including:

[0065] a memory cell array comprising a plurality of memory cell rows;

[0066] a plurality of word lines, the plurality of word lines being coupled to the plurality of memory cell rows, respectively; and

[0067] a peripheral circuit coupled to the plurality of word lines and configured to perform a program verification operation on a selected row of memory cells among the plurality of memory cell rows, the selected row of memory cells being coupled to a selected word line, wherein, to perform the program verification operation, the peripheral circuit is configured to:

[0068] Obtaining an i-th verification result of an i-th program-verification operation; wherein the programming state range verified by the i-th program-verification operation is from the n-th state to the n+k-th state, i and n are positive integers, k is a natural number, and the n+k-th state is less than or equal to the highest programming state of the memory;

[0069] determining a programming state range to be verified in an (i+1)th program-verification operation according to a verification sub-result of the nth state and a verification sub-result of the (n+k)th state in the (i)th verification result;

[0070] The (i+1)th program-verification operation is performed according to the determined program state range that needs to be verified in the (i+1)th program-verification operation.

[0071] According to a fourth aspect of an embodiment of the present disclosure, a memory is provided, including:

[0072] a memory cell array comprising a plurality of memory cell rows;

[0073] a plurality of word lines, the plurality of word lines being coupled to the plurality of memory cell rows, respectively; and

[0074] a peripheral circuit coupled to the plurality of word lines and configured to perform a program operation on a selected row of memory cells from among the plurality of memory cell rows, the selected row of memory cells being coupled to a selected word line, wherein, to perform the program operation, the peripheral circuit is configured to:

[0075] Applying an (i+1)th programming pulse to a memory cell to be programmed in the memory;

[0076] During the application of the (i+1)th programming pulse, counting the number of failed bits in programming the nth state and programming the (n+k)th state in the (i)th programming operation based on the verification sub-result of the nth state and the verification sub-result of the (n+k)th state in the (i)th verification result of the (i)th programming verification operation to obtain an (i)th counting result; wherein the programming states verified by the (i)th programming verification operation range from the (n)th state to the (n+k)th state, i and n are positive integers, k is a natural number, and the (n+k)th state is less than or equal to the highest programming state of the memory;

[0077] determining a programming state range to be verified for an (i+1)th program-verification operation according to the (i)th counting result;

[0078] The (i+1)th program-verification operation is performed according to the determined program state range that needs to be verified in the (i+1)th program-verification operation.

[0079] According to a fifth aspect of an embodiment of the present disclosure, there is provided a memory system, including:

[0080] One or more memories according to the third aspect of the embodiment of the present disclosure or the fourth aspect of the embodiment of the present disclosure;

[0081] A memory controller is coupled to the memory and configured to control the memory.

[0082] In the related art, a fixed start time (start loop) is usually determined for each programming state to be verified based on empirical values. For example, after applying the third programming pulse (i.e., applying the third programming pulse), programming verification (PV2) is started on the second state, and the verification start loop of the second state is 3. In this way, the range of programming states to be verified for each programming verification operation is fixed. However, when the programming speed changes, this fixed start time determined based on empirical values ​​may not be the most suitable verification start time. Specifically, when the set verification start time is earlier than the most suitable verification start time, starting the programming verification too early will extend the time of the programming verification operation, thereby extending the programming time. When the set verification start time is later than the most suitable verification start time, over-programming may occur, thereby reducing the programming quality.

[0083] Compared with each programming verification operation having a fixed range of programming states that need to be verified, in the embodiment of the present disclosure, the range of programming states that need to be verified for the (i+1)th programming verification operation performed after applying the next programming pulse is determined based on the verification result of the (i)th programming verification operation, that is, the range of programming states that need to be verified for the next programming verification operation is determined based on the result of the previous programming verification operation. The starting time of each programming state to be verified can be dynamically determined. Not only is the method simple, but it can also improve the accuracy of the starting time of each programming state to be verified. On the one hand, it can reduce the increase in programming time due to the early setting of the programming verification start time, which is conducive to shortening the programming time; on the other hand, it can reduce over-programming caused by the late setting of the programming verification start time, which is conducive to ensuring better programming quality.

[0084] In addition, compared to the need to manually set different fixed starting times when programming the same programming state in different units (such as blocks or word lines), the embodiments of the present disclosure do not require manual setting of fixed starting times, and can track the differences in memory programming performance through verification results, and then automatically determine the range of programming states that need to be verified for each programming verification operation. The method is simple and can timely adjust the range of programming states that need to be verified for programming verification operations according to memory performance, which is conducive to improving programming quality. BRIEF DESCRIPTION OF THE DRAWINGS

[0085] Figure 1 1 is a threshold voltage distribution diagram of a programming operation according to an exemplary embodiment;

[0086] Figure 2 is a flowchart showing a programming verification method according to an exemplary embodiment;

[0087] Figure 3 is a flowchart of a programming method according to an exemplary embodiment;

[0088] Figure 4 is a partial flow chart of a programming method according to an exemplary embodiment;

[0089] Figure 5 is a schematic diagram of a memory according to an exemplary embodiment;

[0090] Figure 6 is a partial cross-sectional view of a memory cell array including a NAND memory string according to an exemplary embodiment;

[0091] Figure 7 is a block diagram of a memory including a memory cell array and a peripheral circuit according to an exemplary embodiment;

[0092] Figure 8 is a schematic diagram of another memory according to an exemplary embodiment;

[0093] Figure 9a is a block diagram of a memory system according to an exemplary embodiment;

[0094] Figure 9b is a block diagram showing another memory system according to an exemplary embodiment;

[0095] Figure 10a is a schematic diagram of a memory card according to an exemplary embodiment;

[0096] Figure 10b is a schematic diagram of a solid-state drive (SSD) according to an exemplary embodiment. DETAILED DESCRIPTION

[0097] In order to make the purpose, technical solutions and advantages of the present disclosure more clear, the technical solutions of the present disclosure will be further described in detail below with reference to the accompanying drawings and examples. Although the accompanying drawings show exemplary implementation methods of the present disclosure, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the embodiments described herein. On the contrary, these embodiments are provided to enable a more thorough understanding of the present disclosure and to fully convey the scope of the present disclosure to those skilled in the art.

[0098] The following paragraphs describe the present disclosure in more detail by way of example with reference to the accompanying drawings. The advantages and features of the present disclosure will become more apparent from the following description and claims. It should be noted that the drawings are highly simplified and not to exact scale, and are intended solely to facilitate and clearly illustrate the embodiments of the present disclosure.

[0099] It will be understood that the meanings of “on,” “over,” and “over” in this disclosure should be interpreted in the broadest manner, such that “on” not only means being “on” something with no intervening features or layers (i.e., directly on something), but also includes being “on” something with intervening features or layers.

[0100] In the embodiments of the present disclosure, the term "A is connected to B" includes a situation where A and B are connected with each other in contact with each other, or a situation where A is connected to B without contact with each other with other components interposed between A and B.

[0101] In the embodiments of the present disclosure, the terms "first," "second," etc. are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It is understood that the specific order or sequence of "first," "second," etc. can be interchanged where permitted, so that the embodiments of the present disclosure described herein can be implemented in an order other than that illustrated or described herein.

[0102] In the disclosed embodiments, the term "layer" refers to a portion of a material including an area having a thickness. A layer may extend over the entirety of a lower or upper structure, or may have an extent that is smaller than the extent of a lower or upper structure. In addition, a layer may be an area of ​​a homogeneous or inhomogeneous continuous structure having a thickness that is less than the thickness of a continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure, or a layer may be between any horizontal faces at the top and bottom surfaces of a continuous structure. A layer may extend horizontally, vertically, and / or along an inclined surface. A layer may include multiple sublayers. For example, an interconnect layer may include one or more conductor and contact sublayers (in which interconnect lines and / or via contacts are formed), and one or more dielectric sublayers.

[0103] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the art in the art of the present disclosure. The terms used herein are only for the purpose of describing the embodiments of the present disclosure and are not intended to limit the present disclosure.

[0104] It should be noted that the technical solutions described in the embodiments of the present disclosure can be arbitrarily combined without conflict.

[0105] NAND memory is a non-volatile memory device that uses a nonlinear macrocell model. Its advantages include large capacity and fast rewrite speed, making it suitable for storing large amounts of data. NAND memory is widely used in embedded products such as digital cameras, MP3 players, memory cards, and compact USB flash drives.

[0106] In the development of NAND memory, the storage cells of early NAND memory particles were mostly single-level cells (SLC), that is, one storage cell stored 1 bit of data. At this time, each storage cell had two states, specifically 0 and 1.

[0107] With the development of NAND memory, the storage unit of NAND memory particles has gradually evolved from a single-level cell to a multi-level cell (MLC), that is, one storage cell stores 2 bits of data, followed by the introduction of a triple-level cell (TLC), that is, one storage cell stores 3 bits of data, and even a quad-level cell (QLC), that is, one storage cell stores 4 bits of data. Correspondingly, the state of the storage unit of the NAND memory particle has also changed from 2 to 4, 8 or even 16.

[0108] NAND memory operations consist of three parts: erase, program (write), and read. Erasing can be performed on a per-block basis, while programming and reading can be performed on a per-page basis. NAND memory programming, for example, involves three steps: pressure programming (applying programming pulses), program verification (PV), and scanning the verification results.

[0109] For NAND memory, the programming time (t PROG ) is a key metric for measuring NAND memory performance. Therefore, R&D personnel have been dedicated to researching how to improve programming speed and shorten programming time while ensuring programming quality (for example, maintaining the read budget window). Because the duration of the applied programming pulses cannot be changed, the number of applied programming pulses, the number of program verifications performed, the duration of each program verification, and the time it takes to scan the verification results are all important factors in determining programming time.

[0110] Taking a TLC memory cell as an example, a TLC memory cell has one erased state and seven programmed states, with the programmed states being designated L1, L2, L3, L4, L5, L6, and L7, respectively, from state 1 to state 7. The conventional programming method for TLC is to initiate a program verification operation for each state between the application of two adjacent programming pulses. This method suffers from the following problem: after the first programming pulse is applied, only a very small portion of the memory cells actually reach the L1 state, while no memory cells reach the L2, L3, L4, L5, L6, or L7 states. Initiating a program verification operation for at least any of the L2 to L7 states at this point increases the number of required program verification operations and the time required for these operations. It may even cause the time required for the program verification operation and scanning the verification results to occupy at least half of the entire programming process, severely reducing programming speed.

[0111] In order to increase the programming speed, Table 1 shows the starting time corresponding to each programming verification state in the improved related programming verification method.

[0112] Program Verification (PV) Start loop PV1 1 PV2 3 PV3 4 PV4 5 PV5 7 PV6 9 PV7 11

[0113] Table 1 Program verification operations and start times for different programming states

[0114] Among them, PV1 represents the programming verification operation on the 1st state (L1), PV2 represents the programming verification operation on the 2nd state (L2), PV3 represents the programming verification operation on the 3rd state (L3), PV4 represents the programming verification operation on the 4th state (L4), PV5 represents the programming verification operation on the 5th state (L5), PV6 represents the programming verification operation on the 6th state (L6), and PV7 represents the programming verification operation on the 7th state (L7).

[0115] The starting time of the programming verification operation can be defined by the number of programming pulses after which the programming verification operation begins. For example, the starting time of the programming verification operation of the first state is 1, which means that the programming verification of the first state begins after the first programming pulse is applied and before the second programming pulse is applied.

[0116] During a programming operation, all memory cells to be programmed start from an erased state. Typically, several programming pulses are applied before the threshold voltage of the memory cells being programmed reaches a higher programmed state. Therefore, in related art, programming speed can be increased by reducing the number of program verifications.

[0117] Specifically, in the related art, the improved programming method can avoid performing program-verify operations for higher programming states after an earlier programming pulse. As shown in Table 1, the program-verify method uses a fixed start time to control when program-verify is initiated for each programming state. For example, the start time for program-verify operation for state 3 is set to 4. That is, after applying the first three programming pulses, the third state is not verified. Instead, the program-verify operation for state 3 (i.e., PV3) begins after applying the fourth programming pulse.

[0118] Compared to performing program verification on each state after each programming pulse, the improved method described above reduces the number of program verifications to a certain extent. However, considering that different units being programmed simultaneously may have different programming characteristics, setting the same start time for all dies, blocks, or word lines (WL) in each state will still result in errors. Therefore, to ensure programming quality, sufficient margin is required when setting the start time of the program verification operation for each programming state. If different units are being programmed, a fixed program verification operation start time must be set for each unit based on empirical values. This approach consumes a large amount of circuit resources and increases testing time.

[0119] In addition, the programming characteristics of NAND are also affected by many other factors. For example, as the number of cycles (cycling) or temperature and other conditions change, the performance of each storage cell will change, resulting in different programming performance of NAND. By setting a fixed start time for each programming verification operation, it is impossible to track the changes in these programming characteristics. Therefore, the fixed start time is not the most suitable start time. When the fixed start time set for the programming verification operation is earlier than the most suitable start time, starting the programming verification too early will extend the time of the verification operation, thereby extending the programming time. When the fixed start time set for the programming verification operation is later than the most suitable start time, over-programming may occur, thereby reducing the programming quality.

[0120] Take TLC as an example, Figure 1 FIG1 is a diagram showing a threshold voltage distribution diagram of a memory for programming operation according to an exemplary embodiment. It should be noted that TLC has 7 programming states: Figure 1 Only programming of five programming states (ie, L1 to L5) is shown as an example.

[0121] Reference Figure 1 As shown, Figure 18 sub-graphs are shown, namely (a), (b), (c), (d), (e), (f), (g) and (h), each of which includes 5 curves, each of which represents the distribution of memory cells with the same target programming state after applying a programming pulse. th1 、V th2 、V th3 、V th4 、V th5 、V th6 and V th7 They represent, respectively: the starting threshold voltage of the 1st state, the starting threshold voltage of the 2nd state, the starting threshold voltage of the 3rd state, the starting threshold voltage of the 4th state, the starting threshold voltage of the 5th state, the starting threshold voltage of the 6th state, and the starting threshold voltage of the 7th state. Specifically:

[0122] Figure (a) shows the threshold voltage distribution curve obtained by performing the first program-verify operation on the memory cell after applying the first programming pulse starting from the erased state. The first program-verify operation includes program verification (PV1) performed on the first state, that is, the programming state range verified by the first program-verify operation is L1.

[0123] Figure (b) shows the threshold voltage distribution curve obtained by performing a second program-verify operation on the memory cell after applying the next programming pulse based on Figure (a). That is, Figure (b) shows the threshold voltage distribution curve obtained by performing a second program-verify operation on the memory cell after applying the second programming pulse starting from the erased state. The second program-verify operation includes a program-verify (PV1) performed on the first state, that is, the programming state range verified by the second program-verify operation is L1.

[0124] It is understandable that if the start time of executing PV2 is set to 2, combined with Figure 1 As shown in the curve (b), after applying the second programming pulse, the threshold voltage of the memory cell is lower than the threshold voltage of the second state. Therefore, there is no need to perform programming verification on the second state after applying the second programming pulse.

[0125] That is, compared to setting the start time of the program verification operation for the second state to 3 (such as Figure 1 As shown in Figure 3 (c), setting the start time for program-verify for the second state to 2 increases the program-verify time, thereby increasing the programming time. In other words, when the fixed start time for the program-verify operation is set earlier than the optimal start time, starting the program-verify operation too early will extend the verification time, thereby increasing the programming time.

[0126] Figure (c) shows the threshold voltage distribution curve obtained by performing the third program-verify operation on the memory cell after applying the next programming pulse based on Figure (b). That is, Figure (c) shows the threshold voltage distribution curve obtained by performing the third program-verify operation on the memory cell after applying the third programming pulse starting from the erased state. It should be emphasized that the third program-verify operation includes program-verify (PV1) on the first state and program-verify (PV2) on the second state, and the programming states verified by the third program-verify operation range from L1 to L2.

[0127] Figure (d) shows the threshold voltage distribution curve obtained by performing the fourth program-verify operation on the memory cell after applying the next programming pulse based on Figure (c). That is, Figure (d) shows the threshold voltage distribution curve obtained by performing the fourth program-verify operation on the memory cell after applying the fourth programming pulse starting from the erased state. The fourth program-verify operation includes program-verify (PV1) on the first state and program-verify (PV2) on the second state. The programming states verified by the fourth program-verify operation range from L1 to L2.

[0128] Figure (e) shows the threshold voltage distribution curve obtained by performing the fifth program-verify operation on the memory cell after applying the next programming pulse based on Figure (d). That is, Figure (e) shows the threshold voltage distribution curve obtained by performing the fifth program-verify operation on the memory cell after applying the fifth programming pulse starting from the erased state. The fifth program-verify operation includes program-verify (PV1) on the first state, program-verify (PV2) on the second state, and program-verify (PV3) on the third state. The programming states verified by the fifth program-verify operation range from L1 to L3.

[0129] It is understandable that if the start time of executing PV2 is set to 5, combined with Figure 1 As shown in the curve (e), after the fifth programming pulse, the threshold voltage of some memory cells has already exceeded the threshold voltage of the third state, indicating overprogramming. Therefore, if program verification of the second state is started only after the fifth programming pulse, overprogramming will occur.

[0130] That is, compared to setting the start time of the program verification operation for the second state to 3 (such as Figure 1 As shown in (c), setting the start time for program-verify operation for the second state to 5 may result in over-programming, which reduces programming quality. In other words, when the fixed start time for program-verify operation is set later than the optimal start time, over-programming may occur, thereby reducing programming quality.

[0131] Figure (f) shows the threshold voltage distribution curve obtained by performing the sixth program-verify operation on the memory cell after applying the next programming pulse based on Figure (e). That is, Figure (e) shows the threshold voltage distribution curve obtained by performing the sixth program-verify operation on the memory cell after applying the sixth programming pulse starting from the erased state. The sixth program-verify operation includes program-verify (PV1) on the first state, program-verify (PV2) on the second state, and program-verify (PV3) on the third state. The programming states verified by the sixth program-verify operation range from L1 to L3.

[0132] Figure (g) shows the threshold voltage distribution curve obtained by performing the seventh program-verify operation on the memory cell after applying the next programming pulse based on Figure (f). That is, Figure (g) shows the threshold voltage distribution curve obtained by performing the seventh program-verify operation on the memory cell after applying the seventh programming pulse starting from the erased state. The seventh program-verify operation includes program-verify (PV2) on the second state, program-verify (PV3) on the third state, and program-verify (PV4) on the fourth state. The programming states verified by the seventh program-verify operation range from L2 to L4.

[0133] Figure (h) shows the threshold voltage distribution curve obtained by performing the eighth program-verify operation on the memory cell after applying the next programming pulse based on Figure (g). That is, Figure (h) shows the threshold voltage distribution curve obtained by performing the eighth program-verify operation on the memory cell after applying the eighth programming pulse starting from the erased state. The eighth program-verify operation includes program-verify (PV2) on the second state, program-verify (PV3) on the third state, and program-verify (PV4) on the fourth state. The programming states verified by the eighth program-verify operation range from L2 to L4. This process continues in this manner until programming is complete.

[0134] from Figure 1 It can be seen that after applying a programming pulse, the threshold voltages of memory cells in different programming states will move simultaneously. When the threshold voltage of a memory cell reaches its target threshold voltage, a program inhibit condition can be applied to this memory cell so that when the next programming pulse is applied, the threshold voltage of the memory cell that has reached the target threshold voltage will not move further. It can be understood that during the application of the next programming pulse, the threshold voltage of the memory cell that has not reached the target threshold voltage will increase, and the threshold voltage distribution curve will shift toward a higher threshold voltage.

[0135] For example, the threshold voltage range of the higher program state may be predicted based on information obtained by performing program verification on the lower program state.

[0136] Specifically: Combined Figure 1As shown in (c), (d) and (e), for Figure 1 In (c), the highest programming state for programming verification is state 2. Then, based on the verification result obtained by performing the programming verification operation (PV2) on state 2, it can be predicted how many storage cells whose target programming state is state 3 will reach their target state after the next programming pulse is applied.

[0137] For example, if among the memory cells whose target state is the 2nd state, only a very small number of memory cells, or even no memory cells, have reached the 2nd state, then it can be predicted that after applying the next programming pulse, no memory cells whose target programming state is the 3rd state will be able to reach the 3rd state, that is, the 3rd state will not be programmed successfully. Therefore, there is no need to start the programming verification operation for the 3rd state after applying the next programming pulse. In this way, the number of programming states that need to be verified in the next programming verification operation can be reduced, which is conducive to shortening the programming verification time, reducing the number of verification results to be processed, and improving programming efficiency.

[0138] For example, if more memory cells have reached the second state among the memory cells whose target state is the second state, it can be predicted that after the next programming pulse is applied, there will be memory cells whose target programming state is the third state that can reach the third state. Therefore, it is necessary to start the programming verification operation for the third state after the next programming pulse is applied. In this way, the occurrence of over-programming can be reduced and the programming quality can be improved.

[0139] In view of this, the present disclosure provides a memory programming verification method according to an embodiment of the present invention. Figure 2 As shown, the programming verification method includes the following steps:

[0140] S100: Obtaining an i-th verification result of an i-th program-verification operation; wherein the programming state range verified by the i-th program-verification operation is from the n-th state to the n+k-th state, i and n are positive integers, k is a natural number, and the n+k-th state is less than or equal to the highest programming state of the memory;

[0141] S110: Determine a programming state range to be verified in an (i+1)th program-verification operation based on a verification sub-result of the nth state and a verification sub-result of the (n+k)th state in the (i)th verification result;

[0142] S120: performing an (i+1)th program-verification operation according to the determined program state range that needs to be verified in the (i+1)th program-verification operation.

[0143] Exemplarily, the memory may include a memory array consisting of multiple memory cells, and the memory cells may include single-level cells (SLC), multi-level cells (MLC), triple-level cells (TLC), quad-level cells (QLC), or cells with more levels.

[0144] In S100 , the i-th program verification operation may be understood as a program verification operation performed on the memory cell to be programmed starting from the erased state, after applying the i-th program pulse and before applying the (i+1)-th program pulse.

[0145] The programming state range verified by the i-th programming verification operation is from the n-th state to the n+k-th state, that is, the lowest state verified by the i-th programming verification operation is the n-th state, the highest state is the n+k-th state, and the i-th programming verification operation needs to verify the states between the n-th state and the n+k-th state.

[0146] The i-th verification result is used to indicate a programming result of the memory cell to be programmed after applying i programming pulses. The i-th verification result may include at least one of the following: first-type indication information indicating whether each memory cell to be programmed passed programming; second-type indication information indicating whether each memory cell to be programmed failed programming; and third-type indication information indicating the number of memory cells that reached a target programming state.

[0147] In S110, the verification sub-result of the nth state is used to represent the result obtained by performing program verification on the memory cells whose target programming state is the nth state during the i-th program verification operation. The verification sub-result of the nth state may include at least one of the following: first-type indication information indicating whether programming of each memory cell whose target programming state is the nth state has passed; second-type indication information indicating whether programming of each memory cell whose target programming state is the nth state has failed; and third-type indication information indicating the number of memory cells that have reached the nth target programming state.

[0148] Similarly, the verification sub-result for the n+kth state is used to represent the result of program verification performed on the memory cells whose target programming state is the n+kth state during the i-th program verification operation. The verification sub-result for the n+kth state may include at least one of the following: first-category indication information indicating whether programming of each memory cell whose target programming state is the n+kth state has passed; second-category indication information indicating whether programming of each memory cell whose target programming state is the n+kth state has failed; and third-category indication information indicating the number of memory cells that have reached the target programming state of the n+kth state.

[0149] It should be emphasized that the value of k can be equal to 0. When k is equal to 0, the value of n is equal to the value of n+k, that is, the i-th program-verification operation only performs program-verification on the n-th state.

[0150] Taking TLC as an example, the highest programming state of the memory is state 7, so the value of n+k is less than or equal to 7. Taking QLC as an example, the highest programming state of the memory is state 15, so the value of n+k is less than or equal to 15.

[0151] When performing program verification on different program states, the starting verification levels are different. In S110 , determining a program state range to be verified for the (i+1)th program verification operation may include determining a verification level range for the (i+1)th program verification operation.

[0152] In some embodiments, S110 includes:

[0153] Determining a lowest programming state to be verified for an (i+1)th program-verification operation according to a verification sub-result of the nth state in the (i)th verification result;

[0154] A highest program state to be verified in an (i+1)th program-verification operation is determined based on a verification sub-result of the (n+k)th state in the (i)th verification result.

[0155] In S120 , program verification may be performed on all memory cells whose target states are within a program state range that needs to be verified in the (i+1)th program verification operation.

[0156] Alternatively, in S120, the (i+1)th program-verification may be performed only on memory cells whose target states are within the programming state range required for verification in the (i+1)th program-verification operation and which were not successfully programmed in the previous programming operation. This can reduce the number of memory cells requiring verification and shorten the program-verification time. It should be emphasized that in this case, the obtained (i+1)th verification result includes not only data indicating whether the programming of the memory cell for which the (i+1)th program-verification operation was performed was successful, but also information indicating the number of memory cells that have been successfully programmed.

[0157] In actual application, the (i+1)th program verification operation may be performed after applying the (i+1)th program pulse. It is understood that the steps given in the above program verification method may be executed repeatedly until programming is completed or until the maximum number of program verifications that can be performed is reached.

[0158] Compared with each programming verification operation having a fixed range of programming states that need to be verified, in the embodiment of the present disclosure, the range of programming states that need to be verified for the (i+1)th programming verification operation performed after applying the next programming pulse is determined based on the verification result of the (i)th programming verification operation, that is, the range of programming states that need to be verified for the next programming verification operation is determined based on the result of the previous programming verification operation. The starting time of each programming state to be verified can be dynamically determined, and the accuracy of the starting time of each programming state to be verified can be improved. On the one hand, it can reduce the increase in programming time caused by setting the programming verification start time too early, which is conducive to shortening the programming time; on the other hand, it can reduce over-programming caused by setting the programming verification start time too late, which is conducive to ensuring better programming quality.

[0159] In addition, compared to the need to manually set different fixed starting times when programming the same programming state in different units (for example, blocks or word lines), the embodiments of the present disclosure do not require manual setting of fixed starting times. Instead, the differences in memory programming performance are tracked through verification results, and the range of programming states that need to be verified for each programming verification operation is automatically determined. The method is simple and can timely adjust the range of programming states that need to be verified for programming verification operations according to memory performance, which is conducive to improving programming quality.

[0160] In some embodiments, the verification sub-result of the nth state in the i-th verification result includes: i-th statistical data of the nth state, for counting the number of failed bits programmed to the nth state;

[0161] The determining, based on the verification sub-result of the n-th state in the i-th verification result, the lowest programming state to be verified in the (i+1)-th program-verification operation includes:

[0162] determining a number of failed bits for programming the nth state based on an i-th statistical data of the nth state;

[0163] When the number of failed bits in programming the nth state is less than a first preset value, determining that the lowest programming state to be verified in the (i+1)th programming verification operation is the (n+1)th state;

[0164] When the number of failed bits programmed for the nth state is greater than or equal to a first preset value, the lowest programmed state to be verified in the (i+1)th program-verification operation is determined to be the nth state.

[0165] The i-th statistical data of the n-th state may include data indicating whether the n-th program verification operation for each memory cell whose target state is the n-th state passes. Based on the i-th statistical data of the n-th state, the number of failed bits in the i-th program operation for the n-th state may be determined.

[0166] For example, binary coding can be used to indicate whether a memory cell has passed programming. For example, 0 can be used to indicate programming passed, and 1 can be used to indicate programming failed. Alternatively, 1 can be used to indicate programming passed, and 0 can be used to indicate programming failed. During implementation, those skilled in the art can select an appropriate method to indicate whether a memory cell has passed programming based on actual circumstances, and the embodiments of the present disclosure are not limited thereto.

[0167] It is understood that when the number of failed bits in programming the nth state is less than a first predetermined value, programming of the nth state can be considered successful. Therefore, in the next program-verify process, there is no need to program-verify the nth state again. This shortens the program-verify time and improves the programming speed compared to verifying the nth state each time.

[0168] When the number of failed bits in programming the nth state is greater than or equal to the first preset value, it can be considered that programming the nth state has not been successful. Therefore, in the next program verification process, program verification of the nth state needs to be continued.

[0169] In some embodiments, when a ratio of the number of failed bits programmed to the nth state to the number of bits whose target state is the nth state is less than a first predetermined ratio, determining that the lowest programmed state to be verified in the (i+1)th program-verification operation is the (n+1)th state;

[0170] When the ratio of the number of failed bits programmed to the nth state to the number of bits whose target state is the nth state is greater than or equal to a first preset ratio, the lowest programmed state to be verified in the (i+1)th program verification operation is determined to be the nth state.

[0171] Similarly, when the ratio of the number of bits that failed programming in the nth state to the number of bits whose target state is the nth state is less than a first predetermined value, programming of the nth state can be considered successful. Therefore, in the next program-verify process, program-verify of the nth state is not required. This shortens the program-verify time and improves the programming speed compared to verifying the nth state each time.

[0172] When the ratio of the number of failed bits programmed for the nth state to the number of bits whose target state is the nth state is greater than or equal to a first preset value, we can consider that the programming of the nth state has not been successful. Therefore, in the next programming verification process, it is necessary to continue programming verification for the nth state.

[0173] In some embodiments, the method further comprises:

[0174] Obtaining the number of cycles of the memory cell to be programmed;

[0175] According to the number of cycles, a value range of the first preset value or a value range of the first preset ratio is determined.

[0176] Performing one erase and one write operation on a memory is called a cycle. As the number of cycles increases, the programming performance of the memory may change, resulting in changes in programming speed. It is understandable that a cycle is defined based on the smallest unit of programming. For example, when programming with a block as the smallest unit, the number of cycles for each memory cell in the block is essentially the same.

[0177] It should be emphasized that when the memory is programmed in different minimum units, the number of loops obtained is the number of loops of the minimum unit in which the programming is performed.

[0178] Compared with providing a fixed first preset value, in the embodiment of the present disclosure, by obtaining the number of cycles of the storage unit to be programmed and determining the first preset value based on the number of cycles, the programming characteristics that change with the number of cycles can be tracked during the programming verification process, and the range of the first preset value can be flexibly adjusted, thereby reducing the slow programming speed caused by improper determination of the first preset value, which is conducive to improving the programming speed and ensuring better programming quality.

[0179] In some embodiments, the value range of the first preset value is within the range allowed by an error correction code (ECC) mechanism performed on the memory.

[0180] It is important to emphasize that, to ensure programming quality, the program verification operation for the nth state must be stopped only after programming the nth state is complete. Due to the existence of the ECC error correction mechanism, when the number of bits that fail programming the nth state is within the range allowed by the ECC error correction mechanism, ECC error correction can be used to correct at least some of the failed bits, ensuring that correct data can be read from the memory.

[0181] In the embodiment of the present disclosure, since the value range of the first preset value is within the range allowed by the ECC mechanism, when the number of failed bits in programming the nth state is less than the first preset value, the failed bits can be corrected through the ECC error correction mechanism to ensure that the programming of the nth state can be completed smoothly, and the next programming verification does not need to verify the nth state, which is beneficial to reducing the number of programming states that need to be verified and improving programming efficiency.

[0182] In some embodiments, the first preset ratio ranges from 0.4% to 0.6%. For example, the first preset ratio may be 0.5%.

[0183] In some embodiments, the verification sub-result of the n+kth state in the i-th verification result includes: i-th statistical data of the n+kth state, used to count the number of successful bits programmed to the n+kth state;

[0184] The step of determining the highest programming state to be verified in the (i+1)th program-verification operation according to the verification sub-result of the (n+k)th state in the (i)th verification result includes:

[0185] determining the number of successful bits programmed into the n+k th state based on the i th statistical data of the n+k th state;

[0186] When the number of successful bits programmed into the (n+k)th state is greater than a second preset value and the (n+k)th state is less than the highest programmed state of the memory, determining that the highest programmed state to be verified in the (i+1)th program-verification operation is the (n+k+1)th state;

[0187] When the number of successful bits programmed into the (n+k)th state is less than or equal to a second preset value, the highest programmed state to be verified in the (i+1)th program-verification operation is determined to be the (n+k)th state.

[0188] The i-th statistical data of the n+k-th state may include data indicating whether the n-th program-verify operation for each memory cell whose target state is the n+k-th state passes. Based on the i-th statistical data of the n+k-th state, the number of failed bits in the i-th program operation for the n+k-th state may be determined.

[0189] When the number of successful bits programmed for the n+kth state is greater than the second preset value, and the n+kth state is less than the highest programming state of the memory, it can be considered that after the next application of the programming pulse, there may be many memory cells whose target programming state is the n+kth state that will reach the target state, and there may be memory cells whose target state is the n+k+1th state that will reach the target state. Therefore, in the next programming verification process, it is necessary to perform programming verification on the n+k+1th state to reduce over-programming caused by starting verification of the n+k+1th state too late.

[0190] When the number of successful bits programmed for the n+kth state is less than or equal to the second preset value, it can be considered that the programming of the n+kth state has not been successful, and after the next application of the programming pulse, the probability of the storage cell whose target state is the n+k+1th state reaching the target state is very low. Therefore, in the next programming verification process, there is no need to start verifying the n+k+1th state, and the highest state that needs to be verified in the next programming verification operation is still the n+kth state.

[0191] In some embodiments, when a ratio of the number of successful bits programmed to the n+k th state to the number of bits whose target state is the n+k th state is greater than a second predetermined ratio, determining that the highest programmed state to be verified in the (i+1) th program-verification operation is the (n+k+1) th state;

[0192] When the ratio of the number of successful bits programmed to the n+kth state to the number of bits whose target state is the n+kth state is less than or equal to a second preset ratio, the highest programmed state to be verified in the (i+1)th program verification operation is determined to be the n+kth state.

[0193] Similarly, when the ratio of the number of successful bits programmed for the n+kth state to the number of bits whose target state is the n+kth state is greater than a second preset value, and the n+kth state is less than the highest programming state of the memory, it can be considered that after the next application of the programming pulse, there may be many storage cells whose target programming state is the n+kth state that will reach the target state, and there may be storage cells whose target state is the n+k+1th state that will reach the target state. Therefore, in the next programming verification process, it is necessary to start programming verification for the n+k+1th state to reduce over-programming caused by starting verification of the n+k+1th state too late.

[0194] When the ratio of the number of successful bits programmed to the n+kth state to the number of bits whose target state is the n+kth state is less than or equal to the second preset value, we can consider that the programming of the n+kth state has not been successful, and after the next application of the programming pulse, the probability of the storage cell whose target state is the n+k+1th state reaching the target state is very low. Therefore, in the next programming verification process, there is no need to verify the n+k+1th state, and the highest state that needs to be verified in the next programming verification operation is still the n+kth state.

[0195] In some embodiments, the method further comprises:

[0196] Obtaining the number of cycles of the memory cell to be programmed;

[0197] According to the number of cycles, a value range of the second preset value or a value range of the second preset ratio is determined.

[0198] Compared with providing a fixed second preset value, in the embodiment of the present disclosure, by obtaining the number of cycles of the storage unit to be programmed and determining the second preset value based on the number of cycles, the programming characteristics that change with the number of cycles can be tracked during the programming verification process, and the range of the second preset value can be flexibly adjusted, thereby reducing the slow programming speed caused by improper setting of the second preset value, which is conducive to improving the programming speed and ensuring better programming quality.

[0199] In some embodiments, the second preset ratio ranges from 2% to 3%. For example, the second preset ratio may be 2.3%.

[0200] In some embodiments, based on the concept of PVS (Program Vt distribution sigma), taking TLC as an example, each programming pulse shifts the threshold voltage distribution by approximately 2 sigma, and the difference between the verify levels of different programming states is approximately 3 sigma. To prevent over-programming of a memory cell with the target programming state (n+k+1) after the next programming pulse is applied, causing its threshold voltage to exceed the target threshold voltage, the second preset value can be set to a value outside the range of 2 sigma (i.e., 2.3%).

[0201] When the ratio of the number of successful bits programmed for the n+k state to the number of bits whose target state is the n+k state is greater than 2.3%, it can be considered that after the next application of the programming pulse, there may be many (for example, 50%) storage cells whose target programming state is the n+k state that will reach the target state, and since the target threshold voltage of the n+k+1 state is distributed at negative 3 times sigma, storage cells whose target state is the n+k+1 state will also begin to reach the target threshold voltage. Therefore, it is necessary to start verification of the n+k+1 state during the next programming verification.

[0202] In some embodiments, the program verification method is applied to an incremental step pulse programming method, and the program verification method further includes:

[0203] Obtaining the step size and / or programming voltage slope of the incremental step pulse programming;

[0204] The value range of the second preset value is determined according to the step size and / or the programming voltage slope; or the value range of the second preset ratio is determined according to the step size and the programming voltage slope.

[0205] For example, the memory can be programmed using Incremental Step Pulse Programming (ISPP). It should be noted that when the step size and / or programming voltage slope changes, the rate of change of the threshold voltage of the memory cell also changes. Therefore, the range of the second preset value and the second preset ratio can be adjusted accordingly.

[0206] Specifically, taking the step size as an example, when the step size is large, the threshold voltage of the memory cell increases significantly after each programming pulse is applied, and therefore, the values ​​of the second preset value and the second preset ratio can be relatively small. When the step size is small, the threshold voltage of the memory cell increases slightly after each programming pulse is applied, and therefore, the values ​​of the second preset value and the second preset ratio can be relatively large.

[0207] For example, taking QLC as an example, coarse programming or fine programming can be used, and the step size of coarse programming is larger than the step size of fine programming. Therefore, the value of the second preset value when coarse programming is used is smaller than the value of the second preset value when fine programming is used; or, the value of the second preset ratio when coarse programming is used is smaller than the value of the second preset ratio when fine programming is used.

[0208] Compared to providing a fixed second preset value and second preset ratio, in the embodiment of the present disclosure, by obtaining the step size and / or programming voltage slope of the incremental step pulse programming, and determining the value range of the second preset value based on the step size and / or programming voltage slope; or, determining the value range of the second preset ratio based on the step size and programming voltage slope, the range of the second preset value and the second preset ratio can be flexibly adjusted, reducing the slow programming speed caused by improper setting of the second preset value and the second preset ratio, which is conducive to improving the programming speed and ensuring better programming quality.

[0209] In some embodiments, S110 includes:

[0210] Sampling the verification sub-result of the n-th state and the verification sub-result of the n+k-th state in the i-th verification result respectively to obtain the i-th sampling statistical data of the n-th state and the i-th sampling statistical data of the n+k-th state;

[0211] Determining a lowest programming state to be verified for an (i+1)th programming-verification operation based on i-th sampling statistical data of the n-th state;

[0212] A highest programmed state that needs to be verified in an (i+1) program-verification operation is determined based on i-th sampling statistical data of the (n+k)-th state.

[0213] During a program-verify operation, verification results generated can be stored in a page buffer. These data can be used to identify memory cells that require application of a program-inhibit voltage during subsequent application of programming pulses. Specifically, the verification results can be stored in a dedicated latch in the page buffer, which is used only to temporarily store the verification results of the program-verify operation. Alternatively, the verification results can be stored in other latches in the page buffer, which can also be used to store programming data or program-inhibit information.

[0214] The i-th sampling statistical data of the n-th state may include statistical data obtained by randomly sampling verification results of all memory cells whose target programming state is the n-th state and performing statistics on the number of failed bits of the sampling results.

[0215] The i-th sampling statistical data of the n+k-th state may include statistical data obtained by randomly sampling verification results of all memory cells whose target programming state is the n+k-th state and performing failure bit statistics on the sampling results.

[0216] For example, when there are 16KB latches in the page buffer for storing the above verification results, the verification results stored in 4KB latches can be randomly selected as sample data to determine the lowest programming state and the highest programming state that need to be verified in the (i+1)th program verification operation.

[0217] It is understandable that in some embodiments, data stored in 2KB or 8KB latches may be randomly selected as sample data to determine the lowest programming state and the highest programming state that need to be verified in the (i+1)th program verification operation.

[0218] It should be emphasized that when sampling the statistics of the number of failed bits to obtain the i-th sampling statistics of the n-th state and the i-th sampling statistics of the n+k-th state, it is not limited to obtaining data in units of an entire latch, and only part of the data in a latch can be obtained as sampling statistics.

[0219] After each program-verify operation, the generated verification result includes a large amount of data, especially when program-verify is performed on every memory cell to be programmed. Therefore, if the verification results of all memory cells are counted, the time required to count the number of failed bits will be extended, resulting in an increase in programming time.

[0220] In the embodiment of the present disclosure, by sampling the verification sub-result of the nth state and the verification sub-result of the n+kth state respectively, the i-th sampling statistical data of the nth state and the i-th sampling statistical data of the n+kth state are obtained, and based on the i-th sampling statistical data of the nth state, the lowest programming state that needs to be verified for the i+1th programming verification operation is determined, and based on the i-th sampling statistical data of the n+kth state, the highest programming state that needs to be verified for the i+1th programming verification operation is determined. This can reduce the total amount of data that needs to be counted for each failed bit count, which is beneficial to shortening the time for failed bit count, and increasing the determination range of the programming state that needs to be verified for the i+1th programming verification operation, thereby increasing the programming speed, shortening the programming time, and improving the memory performance.

[0221] In the related art, memory programming is typically performed using the following iterative process: applying programming pulses to memory cells and verifying whether the memory cells have reached a desired data state (i.e., a target programming state) in response to the programming pulses. This iterative process is repeated until the memory cells pass the programming verification. Once a memory cell passes the verification, further programming is prohibited, but other memory cells that have not reached the target programming state can still be programmed in response to subsequent programming pulses.

[0222] After each verification operation, it is usually necessary to count the number of memory cells that failed verification in this programming operation, that is, to perform Fail Bit Count (FBC). In related art, the operation of counting the number of failed bits is performed between the current programming operation and the next programming operation, which takes additional time and results in longer programming time.

[0223] In view of this, Figure 3 FIG. 1 is a flow chart showing a method for programming a memory according to an exemplary embodiment. Figure 3 As shown, the programming method includes the following steps:

[0224] S200: applying an (i+1)th programming pulse to a memory cell to be programmed;

[0225] S210: During the application of the (i+1)th programming pulse, counting the number of failed bits in programming the nth state and programming the n+kth state in the (i)th programming operation based on the verification sub-result of the nth state and the verification sub-result of the n+kth state in the (i)th verification result of the (i)th programming verification operation, to obtain an (i)th counting result; wherein the programming states verified by the (i)th programming verification operation range from the (n)th state to the (n+k)th state, i and n are positive integers, k is a natural number, and the (n+k)th state is less than or equal to the highest programming state of the memory;

[0226] S220: Determine a programming state range to be verified for the (i+1)th program-verification operation according to the (i)th counting result;

[0227] S230: performing an (i+1)th program-verification operation according to the determined program state range that needs to be verified in the (i+1)th program-verification operation.

[0228] In S200 , a program pulse application operation may be performed on the memory cell array through a program operation circuit in a peripheral circuit of the memory device to control a potential level of a bit line of a selected memory cell array.

[0229] In S210, the process of the (i+1)th programming pulse may include an (i+1)th programming preparation operation phase and an (i+1)th programming stabilization execution phase. The (i+1)th programming preparation operation is a preparation operation for performing states and data related to the (i+1)th programming operation, and corresponds to a phase of applying an (i+1)th pass voltage (Vpass) to the selected word line in terms of voltage timing. The (i+1)th programming stabilization execution phase is a phase of controlling the potential level of the bit line of the memory cell array in response to programming data during the programming pulse application operation, and corresponds to a phase of applying an (i+1)th programming voltage to the selected word line in terms of voltage timing.

[0230] In some embodiments, the i+1th statistical data may be read in the i+1th program stabilization execution phase after the i+1th program preparation operation, that is, after the i+1th pass voltage is applied to the selected word line.

[0231] In S220, the i-th counting result may include the i-th statistical data of the n-th state and the i-th statistical data of the (n+k)-th state in the above-mentioned program-verify method. Alternatively, the i-th counting result may include the i-th sampling statistical data in the above-mentioned program-verify method. In this way, the programming state range to be verified for the (i+1)-th program-verify operation is determined based on the i-th counting result. Reference may be made to the program-verify method provided in the embodiments of the present disclosure, and no further description is given here.

[0232] Compared to counting the number of failed bits between applying the i-th programming pulse and the i+1-th programming pulse to determine the programming state range that needs to be verified for the i+1-th programming verification operation performed after the i+1-th programming pulse, the programming method provided by the embodiment of the present disclosure can, during the process of applying the i+1-th programming pulse, count the number of failed bits for the programming result of the n-th state and the programming result of the n+k-th state according to the verification sub-result of the n-th state and the verification sub-result of the n+k-th state in the i-th verification result of the i-th programming verification operation, so as to determine the programming state range that needs to be verified for the i+1-th programming verification operation. In this way, the operation of counting the number of failed bits in the iterative process of the entire programming operation does not take up additional time, thereby saving the execution time of the iterative process of the entire programming operation and improving the efficiency of programming the memory cells.

[0233] Furthermore, the embodiment of the present disclosure can save logic overhead by hiding the process of counting the number of failed bits in the process of applying a programming pulse.

[0234] For example, in terms of time sequence, S220 may be executed between S210 and S230 .

[0235] Preferably, S220 can overlap with S210 in terms of timing. Specifically, S220 can be executed during the application of the (i+1)th programming pulse and after obtaining the i-th counting result. In this way, the determination of the programming state range that needs to be verified for the (i+1)th programming verification operation can be hidden in the application of the (i+1)th programming pulse. In this way, during the iterative process of the entire programming operation, the operation of determining the programming state range that needs to be verified for the (i+1)th programming verification operation does not take up additional time, thereby further saving the execution time of the iterative process of the entire programming operation and improving the efficiency of programming the memory cells.

[0236] In some embodiments, the i-th counting result includes: the number of failed bits programmed to the n-th state in the i-th programming operation;

[0237] S220 may include:

[0238] When the number of failed bits in programming the nth state is less than a first preset value, determining that the lowest programming state to be verified in the (i+1)th programming verification operation is the (n+1)th state;

[0239] When the number of failed bits programmed for the nth state is greater than or equal to the first preset value, the lowest programmed state to be verified in the (i+1)th program-verification operation is determined to be the nth state.

[0240] In some embodiments, S220 may include:

[0241] When a ratio of the number of failed bits programmed for the nth state to the number of bits whose target state is the nth state is less than a first preset ratio, determining that the lowest programmed state to be verified in the (i+1)th program-verification operation is the (n+1)th state;

[0242] When the ratio of the number of failed bits programmed to the nth state to the number of bits whose target state is the nth state is greater than or equal to a first preset ratio, the lowest programmed state to be verified in the (i+1)th program verification operation is determined to be the nth state.

[0243] In some embodiments, the i-th counting result includes: the number of failed bits programmed to the n+k-th state in the i-th programming operation;

[0244] S220 may include:

[0245] When the number of successful bits programmed for the n+kth state is greater than a second preset value, and the n+kth state is less than the highest programmed state of the memory, determining that the highest programmed state to be verified in the i+1th program-verification operation is the n+k+1th state;

[0246] When the number of successful bits programmed into the (n+k)th state is less than or equal to a second preset value, the highest programmed state to be verified in the (i+1)th program-verification operation is determined to be the (n+k)th state.

[0247] In some embodiments, S220 may include:

[0248] When a ratio of the number of successful bits programmed to the n+kth state to the number of bits whose target state is the n+kth state is greater than a second preset ratio, determining that the highest programmed state to be verified in the (i+1)th program-verification operation is the (n+k+1)th state;

[0249] When the ratio of the number of successful bits programmed to the n+kth state to the number of bits whose target state is the n+kth state is less than or equal to a second preset ratio, the highest programmed state to be verified in the (i+1)th program verification operation is determined to be the n+kth state.

[0250] In some embodiments, S210 may include:

[0251] Sampling the verification sub-result of the n-th state and the verification sub-result of the n+k-th state in the i-th verification result respectively to obtain i-th sample data of the n-th state and i-th sample data of the n+k-th state;

[0252] According to the i-th sampling sample data of the n-th state and the i-th sampling sample data of the n+k-th state, the number of failed bits of programming of the n-th state and programming of the n+k-th state in the i-th programming operation is counted to obtain an i-th counting result.

[0253] The i-th counting result may include the i-th sampling statistical data of the n-th state and the i-th sampling statistical data of the (n+k)-th state.

[0254] Exemplarily, the verification results of all storage cells whose target programming state is the nth state can be randomly sampled to obtain the i-th sampling sample data of the nth state, and then the number of failed bits of the i-th sampling sample data of the nth state can be counted to obtain the i-th sampling statistical data of the nth state.

[0255] Similarly, the verification results of all storage cells whose target programming state is the n+kth state can be randomly sampled to obtain the i-th sampling sample data of the n+kth state, and then the number of failed bits of the i-th sampling sample data of the n+kth state can be counted to obtain the i-th sampling statistical data of the n+kth state.

[0256] In the embodiment of the present disclosure, by sampling the verification sub-result of the nth state and the verification sub-result of the n+kth state respectively, the i-th sampling sample data of the nth state and the i-th sampling sample data of the n+kth state are obtained, and the i-th counting result is obtained based on the i-th sampling sample data of the nth state and the i-th sampling sample data of the n+kth state. This can reduce the total amount of data required for counting the number of failed bits each time, which is beneficial to shortening the time for counting the number of failed bits, and increasing the determination range of the programming state that needs to be verified in the i+1th programming verification operation, thereby increasing the programming speed, shortening the programming time, and improving the memory performance.

[0257] Below, refer to Figure 4 As shown, taking TLC as an example, a partial flow chart of a programming operation of a three-dimensional NAND memory is shown. The programming method includes the following steps:

[0258] S300: performing an i-th program verification to perform program verification (i.e., verification (PVn, ..., PVn+k)) on memory cells whose target states are the n-th state to the n+k-th state; wherein i and n are positive integers, k is a natural number, and the n+k-th state is less than or equal to the highest programmed state of the memory;

[0259] S310: After performing the i-th program verification, applying an i+1-th program pulse; during the application of the i+1-th program pulse, counting the number of failed bits in programming the n-th state and programming the n+k-th state in the i-th program verification operation based on the verification sub-result of the n-th state and the verification sub-result of the n+k-th state in the i-th verification result of the i-th program verification operation, to obtain an i-th counting result;

[0260] S320: Determine, based on the i-th counting result, whether the number of failed bits when performing program verification (i.e., PVn) on the n-th state is less than a first preset value;

[0261] S330: Determine, based on the i-th counting result, whether the number of successful bits when performing program verification on the n+k-th state (i.e., PVn+k) is greater than a second preset value;

[0262] When the number of failed bits during program verification for the nth state (i.e., PVn) is less than a first preset value, and the number of successful bits during program verification for the n+kth state (i.e., PVn+k) is greater than a second preset value, it can be determined that the programming state range to be verified for the i+1th program verification operation is from the n+1th state to the n+k+1th state, and therefore, the process jumps to execution S331.

[0263] When the number of failed bits during program verification for the nth state (i.e., PVn) is less than a first preset value, and the number of successful bits during program verification for the n+kth state (i.e., PVn+k) is less than or equal to a second preset value, it can be determined that the programming state range to be verified for the (i+1)th program verification operation is from the (n+1)th state to the (n+k)th state, and therefore, the process jumps to execution S332.

[0264] When the number of failed bits during program verification for the nth state (i.e., PVn) is greater than or equal to a first preset value, and the number of successful bits during program verification for the n+kth state (i.e., PVn+k) is greater than a second preset value, it can be determined that the programming state range to be verified for the (i+1)th program verification operation is from the nth state to the (n+k+1)th state, and therefore, the process jumps to execution S341.

[0265] When the number of failed bits during program verification for the nth state (i.e., PVn) is greater than or equal to a first preset value, and the number of successful bits during program verification for the n+kth state (i.e., PVn+k) is less than or equal to a second preset value, it can be determined that the programming state range to be verified for the (i+1)th program verification operation is from the nth state to the (n+k)th state, and therefore, the process jumps to execution S342.

[0266] S331: performing the (i+1)th program verification to perform program verification on memory cells whose target states are the (n+1)th state to the (n+k+1)th state (i.e., verification (PVn+1, ..., PVn+k+1)); wherein the (n+k+1)th state is less than or equal to the highest programmed state of the memory;

[0267] S332: performing the (i+1)th program verification to perform program verification on the memory cells whose target states are the (n+1)th state to the (n+k)th state (ie, verify (PVn+1, . . . , PVn+k)).

[0268] S341: performing an i+1th program verification to perform program verification on memory cells whose target states are the nth state to the n+k+1th state (i.e., verify (PVn, ..., PVn+k+1)); wherein the n+k+1th state is less than or equal to the highest programmed state of the memory;

[0269] S342: performing the (i+1)th program verification to perform program verification on the memory cells whose target states are the nth state to the (n+k)th state (ie, verify (PVn, . . . , PVn+k));

[0270] S350: After completing the i+1th programming verification, apply a programming pulse, and in the process of applying the programming pulse, count the number of failed bits of the lowest state programming and the highest state programming in the i+1th programming operation according to the lowest state verification sub-result and the highest state verification sub-result in the i+1th verification result of the i+1th programming verification operation, and obtain the i+1th counting result.

[0271] It should be emphasized that each time program verification is performed, the highest state verified must be less than or equal to the highest state that the memory can be programmed in. If the highest state determined in the next program verification in step S330 is greater than the highest state that the memory can be programmed in, the highest state when the next program verification is performed is still the highest state that the memory can be programmed in.

[0272] Taking TLC as an example, the highest state that can be programmed is L7. When the highest state of the i-th program-verify operation is L7 and the number of successful bits of PV7 is greater than the second preset value, the highest state of the i+1-th program-verify operation is still L7.

[0273] Specifically, taking TLC as an example, when the value of i is 4, the value of n is 1, and the value of k is 1, the method includes the following steps:

[0274] Step 1: Execute the fourth program verification operation (i.e., execute S300). The verification state range of the fourth program verification operation is from the first state to the second state. Figure 1 Threshold voltage distribution curve shown in (d);

[0275] Step 2: After executing the fourth program-verify operation, applying a fifth program pulse. During the application of the fifth program pulse, counting the number of failed bits in programming the first state and programming the second state in the fourth program operation is performed based on the verification sub-result of the lowest state (i.e., the first state) and the verification sub-result of the highest state (i.e., the second state) in the verification result of the fourth program-verify operation, respectively, to obtain a fourth counting result (i.e., performing S310 for the first time).

[0276] Subsequently, based on the fourth counting result, the programming state range that needs to be verified in the fifth program-verify operation is determined. Specifically, step three can be executed: based on the fourth counting result, determining whether the number of failed bits when performing program-verification on the first state in the fourth program-verify operation is less than a first preset value (i.e., executing S320); based on the fourth counting result, determining whether the number of successful bits when performing program-verification on the second state is greater than a second preset value (i.e., executing S330);

[0277] Step 4: When the fourth counting result indicates that in the fourth program-verify operation, the number of failed bits in program-verify operation for the first state is less than the first preset value, and the number of successful bits in program-verify operation for the second state is greater than the second preset value, jump to step 5 (i.e., execute S331);

[0278] When the fourth counting result indicates that in the fourth program-verify operation, the number of failed bits in program-verify operation on the first state is less than the first preset value, and the number of successful bits in program-verify operation on the second state is less than or equal to the second preset value, the process jumps to step six (i.e., executing S332);

[0279] When the fourth counting result indicates that in the fourth program-verify operation, the number of failed bits in program-verify operation on the first state is greater than or equal to the first preset value, and the number of successful bits in program-verify operation on the second state is greater than the second preset value, the process jumps to step seven (i.e., executing S341);

[0280] When the fourth counting result indicates that in the fourth program-verify operation, the number of failed bits in program-verify operation on the first state is greater than or equal to the first preset value, and the number of passed bits in program-verify operation on the second state is less than or equal to the second preset value, the process jumps to step eight (i.e., executing S342);

[0281] Step 5: performing a fifth program-verification operation, wherein the target state range to be verified in the fifth program-verification operation is from the second state to the third state; then performing step 9;

[0282] Step 6: performing a fifth program-verification operation, wherein the target state to be verified in the fifth program-verification operation is the second state; then performing step 9;

[0283] Step 7: performing a fifth program-verification operation, wherein the target state range to be verified in the fifth program-verification operation is from the first state to the third state; then performing step 9;

[0284] Step 8: performing a fifth program-verification operation, wherein the target state range to be verified in the fifth program-verification operation is from the first state to the second state; then performing step 9;

[0285] Step nine: Apply the sixth programming pulse; and, during the application of the sixth programming pulse, count the number of failed bits of the lowest programming state verified in the fifth programming verification operation, and count the number of failed bits of the highest programming state verified in the fifth programming verification operation to obtain the fifth counting result (i.e., execute S350).

[0286] It is understood that, during an actual programming operation, the above programming method may be executed cyclically until programming is completed, or until the number of programming pulses applied reaches a maximum number, or until the number of program verifications performed reaches a maximum number.

[0287] Figure 5 FIG. 1 is a schematic diagram of a memory 100 according to an exemplary embodiment. Figure 5 As shown, the memory 100 includes:

[0288] a memory cell array 110 , the memory cell array 110 including a plurality of memory cell rows;

[0289] a plurality of word lines 120, wherein the plurality of word lines 120 are respectively coupled to the plurality of memory cell rows;

[0290] A peripheral circuit 130 is coupled to the plurality of word lines 120 and is configured to perform a program verification operation on a selected memory cell row among the plurality of memory cell rows, the selected memory cell row being coupled to the selected word line, wherein, to perform the program verification operation, the peripheral circuit 130 is configured to:

[0291] Obtaining an i-th verification result of an i-th program-verification operation; wherein the programming state range verified by the i-th program-verification operation is from the n-th state to the n+k-th state, i and n are positive integers, k is a natural number, and the n+k-th state is less than or equal to the highest programming state of the memory;

[0292] Determining a programming state range to be verified in an (i+1)th program-verification operation based on a verification sub-result of the nth state and a verification sub-result of the (n+k)th state in the (i)th verification result;

[0293] The (i+1)th program-verification operation is performed according to the determined program state range that needs to be verified in the (i+1)th program-verification operation.

[0294] The memory cell array 110 may be a NAND flash memory cell array, wherein the memory cell array 110 is provided in the form of an array of NAND memory strings 111, each NAND memory string 111 extending vertically above a substrate (not shown). In some embodiments, each NAND memory string 111 includes a plurality of memory cells 112 coupled in series and stacked vertically. Each memory cell 112 may hold a continuous analog value, such as a voltage or charge, that depends on the number of electrons trapped within the region of the memory cell 112. Each memory cell 112 may be a floating gate type memory cell including a floating gate transistor, or a charge trapping type memory cell including a charge trapping transistor.

[0295] In some embodiments, each memory cell 112 is a single-level cell having two possible memory states and can therefore store one bit of data. For example, a first memory state "0" can correspond to a first voltage range, and a second memory state "1" can correspond to a second voltage range.

[0296] In some embodiments, each memory cell 112 is a cell capable of storing more than a single bit of data in more than four memory states. For example, two bits can be stored per cell (also known as a multi-level cell), three bits can be stored per cell (also known as a triple-level cell), or four bits can be stored per cell (also known as a quad-level cell). Each MLC can be programmed to assume a range of possible nominal storage values. In one example, if each MLC stores two bits of data, the MLC can be programmed to assume one of three possible programming levels from an erased state by writing one of three possible nominal storage values ​​to the cell. A fourth nominal storage value can be used for the erased state.

[0297] like Figure 5 As shown in , each NAND memory string 111 may include a source select gate (SSG) 113 at its source end and a drain select gate (DSG) 114 at its drain end. The source select gate 113 and the drain select gate 114 may be configured to activate a selected NAND memory string 111 (column of the array) during read and program operations.

[0298] In some embodiments, sources of NAND memory strings 111 in the same block 115 are coupled via the same source line (SL) 116 (eg, common SL). In other words, according to some embodiments, all NAND memory strings 111 in the same block 115 have an array common source (ACS).

[0299] According to some embodiments, the drain select gate 114 of each NAND memory string 111 is coupled to a corresponding bit line 117 , from which data can be read or written via an output bus (not shown).

[0300] In some embodiments, each NAND memory string 111 is configured to be selected or deselected by applying a select voltage (e.g., higher than the threshold voltage of the transistor having the drain select gate 114) or a deselect voltage (e.g., 0V) to the corresponding drain select gate 114 via one or more DSG lines 118. And / or, in some embodiments, each NAND memory string 111 is configured to be selected or deselected by applying a select voltage (e.g., higher than the threshold voltage of the transistor having the source select gate 113) or a deselect voltage (e.g., 0V) to the corresponding source select gate 113 via one or more SSG lines 119.

[0301] like Figure 5 As shown in FIG, a NAND memory string 111 can be organized into a plurality of blocks 115, each of which can have a common source line 116 (e.g., coupled to ground). In some embodiments, each block 115 is a basic data unit for an erase operation, i.e., all memory cells 112 on the same block 115 are erased at the same time. To erase the memory cells 112 in a selected block, the source lines coupled to the selected block and unselected blocks in the same plane as the selected block can be biased with an erase voltage (Vers) (e.g., a high positive voltage (e.g., 20V or higher)).

[0302] It should be understood that in some examples, erase operations can be performed at the half-block level, at the quarter-block level, or at levels having any suitable number or fraction of blocks. The memory cells 112 of adjacent NAND memory strings 111 can be coupled by word lines 120, which select which row of memory cells 112 is affected by read and program operations.

[0303] In some embodiments, each word line 120 is coupled to a page 130 of memory cells 112, which is the basic unit of data for programming operations. The size of a page 130, measured in bits, can be related to the number of NAND memory strings 111 coupled by the word lines 120 in a block 115. Each word line 120 can include multiple control gates (gate electrodes) at each memory cell 112 in the corresponding page 130 and a gate line coupling the control gates. It will be understood that a memory cell row is a plurality of memory cells 112 located in the same page 130.

[0304] Figure 6 1 shows a side view of a cross section of an exemplary memory cell array 110 including NAND memory strings 111 according to some aspects of the present disclosure. Figure 6 As shown in FIG, NAND memory strings 111 can extend vertically through a memory stack layer 102 over a substrate 101. The substrate 101 can include silicon (e.g., single crystal silicon), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon on insulator (SOI), germanium on insulator (GOI), or any other suitable material.

[0305] Memory stack 102 may include alternating gate conductive layers 103 and gate-to-gate dielectric layers 104. The number of pairs of gate conductive layers 103 and gate-to-gate dielectric layers 104 in memory stack 102 may determine the number of memory cells 112 in memory cell array 110.

[0306] The gate conductive layer 103 may include a conductive material, including but not limited to tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, silicide, or any combination thereof. In some embodiments, each gate conductive layer 103 includes a metal layer, such as a tungsten layer. In some embodiments, each gate conductive layer 103 includes a doped polysilicon layer. Each gate conductive layer 103 may include a control gate surrounding the memory cell 112 and may extend laterally at the top of the memory stack 102 as a DSG line 118, at the bottom of the memory stack 102 as an SSG line 119, or between the DSG line 118 and the SSG line 119 as a word line 120.

[0307] like Figure 6 As shown in FIG, NAND memory string 111 includes a channel structure 105 extending vertically through memory stack layer 102. In some embodiments, channel structure 105 includes a channel hole filled with one or more semiconductor materials (e.g., as semiconductor channel 106) and one or more dielectric materials (e.g., as memory film 107). In some embodiments, semiconductor channel 106 includes silicon, such as polysilicon. In some embodiments, memory film 107 is a composite dielectric layer including a tunneling layer 108, a storage layer 109 (also referred to as a "charge trapping / storage layer"), and a barrier layer 1010. Channel structure 105 can have a cylindrical shape (e.g., a pillar). According to some embodiments, semiconductor channel 106, tunneling layer 108, storage layer 109, and barrier layer 1010 are arranged radially in this order from the center of the pillar toward the outer surface of the pillar. Tunneling layer 108 can include silicon oxide, silicon oxynitride, or any combination thereof. Storage layer 109 can include silicon nitride, silicon oxynitride, or any combination thereof. The barrier layer 1010 may include silicon oxide, silicon oxynitride, a high dielectric constant (high-k) dielectric, or any combination thereof. In one example, the memory film 107 may include a composite layer of silicon oxide / silicon oxynitride / silicon oxide (ONO).

[0308] According to some embodiments, Figure 6 As shown in FIG, a well 414 (e.g., a P-well and / or an N-well) is formed in the substrate 101, and the source terminal of the NAND memory string 111 is in contact with the well 414. For example, the source line 116 can be coupled to the well 414 to apply an erase voltage to the well 414 (i.e., the source of the NAND memory string 111) during an erase operation. In some embodiments, the NAND memory string 111 further includes a channel plug 416 at the drain terminal of the NAND memory string 111. It should be understood that although in Figure 6Not shown, but additional features of the memory cell array 110 may be formed, including but not limited to gate line gaps / source contacts, local contacts, interconnect layers, etc.

[0309] Return Reference Figure 5 , peripheral circuitry 130 may be coupled to memory cell array 110 via bit lines 117, word lines 120, source lines 116, SSG lines 119, and DSG lines 118. Peripheral circuitry 130 may include any suitable analog, digital, and mixed-signal circuitry for facilitating operation of memory cell array 110 by applying and sensing voltage and / or current signals to and from each target memory cell 112 via bit lines 117, word lines 120, source lines 116, SSG lines 119, and DSG lines 118.

[0310] The peripheral circuit 130 may include various types of peripheral circuits formed using metal-oxide-semiconductor (MOS) technology. For example, Figure 7 Some exemplary peripheral circuits 130 are shown, including page buffers / sense amplifiers 504, column decoders / bit line (BL) drivers 506, row decoders / word line (WL) drivers 508, voltage generators 510, control logic units 512, registers 514, interfaces 516, and data buses 518. It should be understood that in some examples, peripheral circuits 130 may also include Figure 7 Additional peripheral circuits not shown.

[0311] The page buffer / sense amplifier 504 can be configured to read data from the memory cell array 110 and program (write) data to the memory cell array 110 according to control signals from the control logic unit 512. In one example, the page buffer / sense amplifier 504 can store a page of program data (write data) to be programmed into one page 130 of the memory cell array 110. In another example, the page buffer / sense amplifier 504 can perform a program verification operation to ensure that the data has been correctly programmed into the memory cell 112 coupled to the selected word line 120. In yet another example, the page buffer / sense amplifier 504 can also sense a low-power signal from the bit line 117 representing a data bit stored in the memory cell 112 and amplify the small voltage swing to a recognizable logic level during a read operation. The column decoder / bit line driver 506 can be configured to be controlled by the control logic unit 512 and select one or more NAND memory strings 111 by applying a bit line voltage generated from the voltage generator 510.

[0312] The row decoder / word line driver 508 may be configured to be controlled by the control logic unit 512 and to select / deselect the block 115 of the memory cell array 110 and to select / deselect the word line 120 of the block 115. The row decoder / word line driver 508 may also be configured to use the word line voltage (V WL ) to drive the word lines 120. In some embodiments, the row decoder / word line driver 508 can also select / deselect and drive the SSG lines 119 and the DSG lines 118. As described in detail below, the row decoder / word line driver 508 is configured to perform an erase operation on the memory cells 112 coupled to the selected word line(s) 120. The voltage generator 510 can be configured to be controlled by the control logic unit 512 and generate word line voltages (e.g., read voltage, program voltage, pass voltage, local voltage, verify voltage, etc.), bit line voltages, and source line voltages to be supplied to the memory cell array 110.

[0313] The control logic unit 512 can be coupled to each of the peripheral circuits described above and is configured to control the operation of each peripheral circuit. The register 514 can be coupled to the control logic unit 512 and includes a status register, a command register, and an address register for storing status information, command operation codes (OP codes), and command addresses for controlling the operation of each peripheral circuit. The interface 516 can be coupled to the control logic unit 512 and act as a control buffer to buffer control commands received from a host (not shown) and relay them to the control logic unit 512, as well as buffer status information received from the control logic unit 512 and relay it to the host. The interface 516 can also be coupled to the column decoder / bit line driver 506 via the data bus 518 and act as a data I / O interface and data buffer to buffer data and relay it to the memory cell array 110 or relay or buffer data from the memory cell array 110.

[0314] It should be emphasized that the peripheral circuit 130 is configured to perform the program verification operation provided by the embodiment of the present disclosure on a selected memory cell row among the plurality of memory cell rows.

[0315] Figure 8 FIG. 1 is a schematic diagram of a memory 200 according to an exemplary embodiment. Figure 8 As shown, the memory 200 includes:

[0316] a memory cell array 110 , the memory cell array 110 including a plurality of memory cell rows;

[0317] a plurality of word lines 120, the plurality of word lines 120 being coupled to the plurality of memory cell rows, respectively; and

[0318] A peripheral circuit 230 is coupled to the plurality of word lines 120 and is configured to perform a program operation on a selected memory cell row among the plurality of memory cell rows, the selected memory cell row being coupled to the selected word line, wherein, to perform the program operation, the peripheral circuit 230 is configured to:

[0319] Applying an (i+1)th programming pulse to a memory cell to be programmed in the memory;

[0320] During the application of the (i+1)th programming pulse, counting the number of failed bits in programming the nth state and programming the n+kth state in the i-th programming operation based on the verification sub-result of the nth state and the verification sub-result of the n+kth state in the i-th verification result of the i-th programming verification operation to obtain an i-th counting result; wherein the programming states verified in the i-th programming verification operation range from the n-th state to the n+k-th state, i and n are positive integers, k is a natural number, and the n+k-th state is less than or equal to the highest programming state of the memory;

[0321] Determining a programming state range to be verified for an (i+1)th program-verification operation according to an (i)th counting result;

[0322] The (i+1)th program-verification operation is performed according to the determined program state range that needs to be verified in the (i+1)th program-verification operation.

[0323] It should be emphasized that the peripheral circuit 230 is configured to perform the program operation provided by the embodiment of the present disclosure on a selected memory cell row among the plurality of memory cell rows.

[0324] For example, the structure of the peripheral circuit 230 may be the same as that of the peripheral circuit 130 .

[0325] Figure 9a is a schematic diagram showing a memory system 300 according to an exemplary embodiment. Figure 9b FIG is a schematic diagram of another memory system 300 according to an exemplary embodiment. Figure 9a and Figure 9b As shown, the memory system 300 includes:

[0326] One or more memories 100 or 200;

[0327] The memory controller 321 is coupled to the memory 100 or the memory 200 and is configured to control the memory 100 or the memory 200 .

[0328] System 300 may be a mobile phone, a desktop computer, a laptop computer, a tablet computer, a vehicle computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device having storage therein.

[0329] like Figure 9a As shown in FIG, system 300 may include a host 310 and a storage subsystem 320. The storage subsystem 320 has one or more memories 100 or 200, and the storage subsystem further includes a memory controller 321. The host 310 may be a processor (e.g., a central processing unit (CPU)) or a system on a chip (SoC) (e.g., an application processor (AP)) of an electronic device. The host 310 may be configured to send data to the memory 100 or 200. Alternatively, the host 310 may be configured to receive data from the memory 100 or 200.

[0330] The memory 100 or the memory 200 can be any memory device disclosed in the present disclosure. The memory 100 or the memory 200 (e.g., a NAND flash memory device (e.g., a three-dimensional (3D) NAND flash memory device)) can have reduced leakage current from a driver transistor (e.g., a string driver) coupled to an unselected word line during an erase operation, which allows further size reduction of the driver transistor.

[0331] According to some embodiments, the memory controller 321 is also coupled to the host 310. The memory controller 321 may manage data stored in the memory 100 or the memory 200 and communicate with the host 310.

[0332] In some embodiments, the memory controller 321 is designed to operate in a low duty cycle environment, such as a Secure Digital (SD) card, a Compact Flash (CF) card, a Universal Serial Bus (USB) flash drive, or other media for use in electronic devices such as personal computers, digital cameras, mobile phones, etc.

[0333] In some embodiments, the memory controller 321 is designed to operate in a high duty cycle environment solid state drive (SSD) or embedded multimedia card (eMMC), which is used as data storage for mobile devices such as smartphones, tablets, laptops, etc., as well as enterprise storage arrays.

[0334] The memory controller 321 may be configured to control operations of the memory 100 or the memory 200, such as read, erase, and program operations. The memory controller 321 may also be configured to manage various functions regarding data stored or to be stored in the memory 100 or the memory 200, including but not limited to bad block management, garbage collection, logical to physical address translation, wear leveling, etc. In some embodiments, the memory controller 321 is further configured to process error correction codes (ECC) regarding data read from or written to the memory 100 or the memory 200.

[0335] The memory controller 321 may also perform any other suitable functions, such as formatting the memory 100 or the memory 200. The memory controller 321 may communicate with an external device (e.g., the host 310) according to a specific communication protocol. For example, the memory controller 321 may communicate with the external device through at least one of various interface protocols, such as a USB protocol, an MMC protocol, a peripheral component interconnect (PCI) protocol, a PCI Express (PCI-E) protocol, an Advanced Technology Attachment (ATA) protocol, a serial ATA protocol, a parallel ATA protocol, a small computer mini-interface (SCSI) protocol, an enhanced minidisk interface (ESDI) protocol, an integrated drive electronics (IDE) protocol, a Firewire protocol, etc.

[0336] The memory controller 321 and one or more memories 100 or 200 can be integrated into various types of storage devices, for example, included in the same package (e.g., a universal flash storage (UFS) package or an eMMC package). That is, the memory system 100 can be implemented and packaged into different types of terminal electronic products.

[0337] In such Figure 10a In one example shown in FIG, the memory controller 321 and the single memory 100 may be integrated into a memory card 400. The memory card 400 may include a PC card (PCMCIA, Personal Computer Memory Card International Association), a CF card, a Smart Media (SM) card, a memory stick, a multimedia card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), a UFS, etc. The memory card 400 may also include a computer that connects the memory card 400 to a host (e.g., Figure 9a A memory card connector 410 is coupled to the host 310 in the memory card.

[0338] In such Figure 10bIn another example shown in FIG, the memory controller 321 and the plurality of memories 100 may be integrated into a solid state drive (SSD) 500. The solid state drive 500 may also include a computer that connects the solid state drive 500 to a host (e.g., Figure 9a In some embodiments, the solid-state drive 500 has a storage capacity and / or an operating speed greater than that of the memory card 400.

[0339] It can be understood that the memory controller 321 can execute the program verification method or the programming method provided by any embodiment of the present disclosure.

[0340] The description of the above memory device embodiment is similar to the description of the above method embodiment, and has similar beneficial effects as the method embodiment. For technical details not disclosed in the memory device embodiment of the present disclosure, please refer to the description of the method embodiment of the present disclosure for understanding.

[0341] It should be understood that the “some embodiments” mentioned throughout the specification mean that specific features, structures or characteristics related to the embodiments are included in at least one embodiment of the present disclosure. Therefore, “in some embodiments” or “in other embodiments” appearing throughout the specification do not necessarily refer to the same embodiment. In addition, these specific features, structures or characteristics may be combined in one or more embodiments in any suitable manner. It should be understood that in the various embodiments of the present disclosure, the size of the serial numbers of the above-mentioned processes does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present disclosure. The serial numbers of the embodiments of the present disclosure mentioned above are for description only and do not represent the advantages and disadvantages of the embodiments.

[0342] It should be noted that, in this document, the terms "comprises," "includes," or any other variations thereof are intended to encompass non-exclusive inclusion, such that a process, method, article, or apparatus comprising a series of elements includes not only those elements but also other elements not explicitly listed, or elements inherent to such process, method, article, or apparatus. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of other identical elements in the process, method, article, or apparatus comprising the element.

[0343] In the several embodiments provided in the present disclosure, it should be understood that the disclosed devices and methods can be implemented in other ways. The device embodiments described above are merely schematic. For example, the division of the units is merely a logical function division. In actual implementation, there may be other division methods, such as: multiple units or components can be combined, or can be integrated into another system, or some features can be ignored or not executed. In addition, the coupling, direct coupling, or communication connection between the components shown or discussed can be through some interfaces, and the indirect coupling or communication connection of the devices or units can be electrical, mechanical or other forms.

[0344] The units described above as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units; they may be located in one place or distributed across multiple network units; some or all of the units may be selected according to actual needs to achieve the purpose of the scheme of this embodiment.

[0345] In addition, all functional units in the embodiments of the present disclosure may be integrated into one processing unit, or each unit may be separately used as a unit, or two or more units may be integrated into one unit; the above-mentioned integrated units may be implemented in the form of hardware or in the form of hardware plus software functional units.

[0346] The above description is merely an embodiment of the present disclosure, but the scope of protection of the present disclosure is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this disclosure should be included in the scope of protection of the present disclosure. Therefore, the scope of protection of the present disclosure should be based on the scope of protection of the claims.

Claims

1. A memory programming verification method, characterized in that: include: Obtaining an i-th verification result of an i-th program-verification operation; wherein the programming state range verified by the i-th program-verification operation is from the n-th state to the n+k-th state, i and n are positive integers, k is a natural number, and the n+k-th state is less than the highest programming state of the memory; determining a programming state range to be verified for an (i+1)th program-verification operation according to the number of bits successfully programmed into the (n+k)th state in the (i)th verification result; The (i+1)th program-verification operation is performed according to the determined program state range that needs to be verified in the (i+1)th program-verification operation.

2. The program verification method according to claim 1, wherein: The step of determining the programming state range to be verified for the (i+1)th program-verification operation according to the number of bits successfully programmed in the (n+k)th state in the (i)th verification result includes: In response to the number of bits successfully programmed into the (n+k)th state being greater than a first preset value, it is determined that the highest programmed state to be verified in the (i+1)th program-verification operation is the (n+k+1)th state.

3. The program verification method according to claim 1, wherein: Also includes: A programming state range to be verified in the (i+1)th program-verification operation is determined according to a verification sub-result of the nth state in the (i)th verification result.

4. The program verification method according to claim 3, wherein: The determining, based on the verification sub-result of the n-th state in the i-th verification result, a programming state range to be verified for the (i+1)-th program-verification operation includes: A lowest programming state to be verified in the (i+1)th program-verification operation is determined according to a verification sub-result of the nth state in the (i)th verification result.

5. The program verification method according to claim 4, wherein: The verification sub-result of the nth state in the i-th verification result includes: i-th statistical data of the nth state, used to count the number of failed bits programmed in the n-th state; The determining, based on the verification sub-result of the n-th state in the i-th verification result, a lowest programming state to be verified in the (i+1)-th program-verification operation includes: determining a number of failed bits for programming the nth state based on an i-th statistical data of the nth state; When the number of failed bits programmed for the nth state is less than a second preset value, determining that the lowest programmed state to be verified in the (i+1)th program-verification operation is the (n+1)th state; When the number of failed bits in programming the nth state is greater than or equal to the second preset value, determining that the lowest programming state to be verified in the (i+1)th program-verification operation is the nth state; or, When a ratio of the number of failed bits programmed to the nth state to the number of bits whose target state is the nth state is less than a first preset ratio, determining that the lowest programmed state to be verified in the (i+1)th program-verification operation is the (n+1)th state; When the ratio of the number of failed bits programmed to the nth state to the number of bits whose target state is the nth state is greater than or equal to the first preset ratio, the lowest programmed state to be verified in the (i+1)th program verification operation is determined to be the nth state.

6. The program verification method according to claim 5, wherein: The program verification method further includes: Obtaining the number of cycles of the memory cell to be programmed; According to the number of cycles, a value range of the second preset value or a value range of the first preset ratio is determined.

7. The program verification method according to claim 5, wherein: The value range of the second preset value is within the range allowed by the error correction mechanism of the error correction code performed on the memory.

8. The program verification method according to claim 2, wherein: Also includes: determining the number of bits successfully programmed in the n+k th state according to the i th statistical data of the n+k th state; When the number of successful bits programmed for the n+kth state is less than or equal to the first preset value, determining that the highest programmed state to be verified in the (i+1)th program-verification operation is the (n+k)th state; or, When a ratio of the number of successful bits programmed to the n+kth state to the number of bits whose target state is the n+kth state is greater than a second preset ratio, determining that the highest programmed state to be verified in the (i+1)th program-verification operation is the (n+k+1)th state; When the ratio of the number of successful bits programmed to the n+kth state to the number of bits whose target state is the n+kth state is less than or equal to the second preset ratio, the highest programmed state to be verified in the (i+1)th program verification operation is determined to be the n+kth state.

9. The program verification method according to claim 8, wherein: The program verification method further includes: Obtaining a step size and / or a programming voltage slope of incremental step pulse programming; determining a value range of the first preset value or the second preset ratio based on the step size and / or the programming voltage slope; wherein the programming verification method is applied to an incremental step pulse programming method; or, Obtaining the number of cycles of the memory cell to be programmed; and determining a value range of the first preset value or a value range of the second preset ratio according to the number of cycles.

10. The method according to claim 8, characterized in that The second preset ratio ranges from 2% to 3%.

11. The program verification method according to claim 1, wherein: Also includes: Sampling the verification sub-result of the n-th state and the verification sub-result of the n+k-th state in the i-th verification result respectively to obtain i-th sampling statistical data of the n-th state and i-th sampling statistical data of the n+k-th state; determining, based on i-th sampling statistical data of the n-th state, a lowest programming state to be verified in the (i+1)th programming-verification operation; A highest programmed state that needs to be verified in the (i+1)th program-verification operation is determined based on the i-th sampling statistical data of the (n+k)-th state.

12. The program verification method according to claim 5, wherein: Also includes: Applying an (i+1)th programming pulse to a memory cell to be programmed in the memory; During the application of the i+1th programming pulse, the number of failed bits of the programming of the nth state and the programming of the n+kth state in the i-th programming operation is counted according to the verification sub-result of the n-th state and the verification sub-result of the n+k-th state in the i-th verification result of the i-th programming verification operation to obtain an i-th counting result.

13. The program verification method according to claim 10, wherein: The step of counting the number of failed bits in programming the nth state and programming the n+kth state in the i-th programming operation according to the verification sub-result of the n-th state and the verification sub-result of the n+k-th state in the i-th verification result of the i-th program-verification operation to obtain the i-th counting result includes: Sampling the verification sub-result of the n-th state and the verification sub-result of the n+k-th state in the i-th verification result respectively to obtain i-th sample data of the n-th state and i-th sample data of the n+k-th state; According to the i-th sampling sample data of the n-th state and the i-th sampling sample data of the n+k-th state, the number of failed bits of programming of the n-th state and programming of the n+k-th state in the i-th programming operation is counted to obtain the i-th counting result.

14. A memory, characterized in that: include: a memory cell array comprising a plurality of memory cell rows; a plurality of word lines, the plurality of word lines being coupled to the plurality of memory cell rows, respectively; as well as a peripheral circuit coupled to the plurality of word lines and configured to perform a program verification operation on a selected row of memory cells among the plurality of memory cell rows, the selected row of memory cells being coupled to a selected word line, wherein, to perform the program verification operation, the peripheral circuit is configured to: Obtaining an i-th verification result of an i-th program-verification operation; wherein the programming state range verified by the i-th program-verification operation is from the n-th state to the n+k-th state, i and n are positive integers, k is a natural number, and the n+k-th state is less than the highest programming state of the memory; determining a programming state range to be verified for an (i+1)th program-verification operation according to the number of bits successfully programmed into the (n+k)th state in the (i)th verification result; The (i+1)th program-verification operation is performed according to the determined program state range that needs to be verified in the (i+1)th program-verification operation.

15. The memory according to claim 14, wherein: The step of determining the programming state range to be verified for the (i+1)th program-verification operation according to the number of bits successfully programmed in the (n+k)th state in the (i)th verification result includes: In response to the number of bits successfully programmed into the (n+k)th state being greater than a first preset value, it is determined that the highest programmed state to be verified in the (i+1)th program-verification operation is the (n+k+1)th state.

16. The memory according to claim 14, wherein: The peripheral circuit is further configured to: A programming state range to be verified in the (i+1)th program-verification operation is determined according to a verification sub-result of the nth state in the (i)th verification result.

17. The memory according to claim 16, wherein: The determining, based on the verification sub-result of the n-th state in the i-th verification result, a programming state range to be verified for the (i+1)-th program-verification operation includes: A lowest programming state to be verified in the (i+1)th program-verification operation is determined according to a verification sub-result of the nth state in the (i)th verification result.

18. The memory according to claim 17, wherein: The peripheral circuit is further configured to: determining a number of failed bits for programming the nth state based on an i-th statistical data of the nth state; When the number of failed bits programmed for the nth state is less than a second preset value, determining that the lowest programmed state to be verified in the (i+1)th program-verification operation is the (n+1)th state; When the number of failed bits in programming the nth state is greater than or equal to the second preset value, determining that the lowest programming state to be verified in the (i+1)th program-verification operation is the nth state; or, When a ratio of the number of failed bits programmed to the nth state to the number of bits whose target state is the nth state is less than a first preset ratio, determining that the lowest programmed state to be verified in the (i+1)th program-verification operation is the (n+1)th state; When the ratio of the number of failed bits programmed to the nth state to the number of bits whose target state is the nth state is greater than or equal to the first preset ratio, the lowest programmed state to be verified in the (i+1)th program verification operation is determined to be the nth state.

19. The memory according to claim 14, wherein: The peripheral circuit is further configured to: Sampling the verification sub-result of the n-th state and the verification sub-result of the n+k-th state in the i-th verification result respectively to obtain i-th sampling statistical data of the n-th state and i-th sampling statistical data of the n+k-th state; determining, based on i-th sampling statistical data of the n-th state, a lowest programming state to be verified in the (i+1)th programming-verification operation; A highest programmed state that needs to be verified in the (i+1)th program-verification operation is determined based on the i-th sampling statistical data of the (n+k)-th state.

20. A memory system, characterized in that: include: One or more memories according to claims 14 to 19; A memory controller is coupled to the memory and configured to control the memory.

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