Memory controller, error address positioning method and computing system

Abstract

The embodiment of the invention provides a memory controller, an error address positioning method and a computing system. The memory controller comprises an algorithm control circuit, a data generation circuit, a data comparison circuit and a monitoring circuit, and the algorithm control circuit is configured to generate control information for memory testing based on preset steps of a test algorithm; the data generation circuit is configured to generate test data used for being written into the memory to be tested and expected data obtained after the test data is read; the data comparison circuit is configured to detect whether target data read from the to-be-detected memory is consistent with expected data or not; and the monitoring circuit is configured to respond to the inconsistency of the read target data and the expected data, send a mark for stopping the memory test to the algorithm control circuit so as to stop the memory test and record a test address corresponding to an error and corresponding command data, so that stop and quick positioning are realized when the error occurs, and the repair efficiency is improved.

Description

Technical Field

[0001] The present disclosure relates to a memory controller, an error address locating method, and a computing system. Background Art

[0002] With technological advancements and shrinking process geometries, the distances between memory array cells are becoming increasingly closer, increasing the probability of failure and proving the diversity of these failure types. Memory Built-In Self-Test (MBIST), a testing technology that automatically generates a series of test processes within the chip and verifies the accuracy of the data results, has gained widespread adoption. The March C algorithm can cover a wider range of fault types and reduce testing time, significantly improving testing efficiency. Memory manufacturers also offer a feature that can repair some addresses that still have errors after shipment. This feature primarily uses spare cells to remap the erroneous addresses. Summary of the Invention

[0003] At least one embodiment of the present disclosure provides a memory controller, comprising: an algorithm control circuit, a data generation circuit, a data comparison circuit, and a monitoring circuit, wherein the algorithm control circuit is configured to generate control information for memory testing based on preset steps of a test algorithm, wherein the control information includes a test address and corresponding command data in the memory to be tested; the data generation circuit is configured to generate test data for writing to the memory to be tested and expected data after the test data is read; the data comparison circuit is configured to detect whether the target data read from the memory to be tested is consistent with the expected data; and the monitoring circuit is configured to send a flag for terminating the memory test to the algorithm control circuit in response to the read target data being inconsistent with the expected data, so as to terminate the memory test and record the test address and corresponding command data corresponding to the error, wherein the inconsistency between the read target data and the expected data indicates an error.

[0004] For example, at least one embodiment of the present disclosure provides a memory controller, wherein the algorithm control circuit includes an algorithm state machine, an address generating circuit and a command generating circuit, wherein the algorithm state machine is configured to send spatial range information to the address generating circuit according to the execution state of the test algorithm, send command control signal sequence information to the command generating circuit, and send data type information to the data generating circuit so that the data generating circuit generates test data and expected data; the address generating circuit is configured to generate a test address in the memory to be tested by ascending or descending addressing based on the spatial range information; and the command generating circuit is configured to encode the command control signal sequence information and output command data.

[0005] For example, at least one embodiment of the present disclosure provides a memory controller, wherein the command control signal sequence information includes a read command signal sequence, a write command signal sequence, or a read-write command signal sequence, and the command generation circuit encodes the command control signal sequence information and outputs command data, including: encoding the read command signal sequence, the write command signal sequence, or the read-write command signal sequence, respectively, and outputting read command data, write command data, or read-write command data, wherein the number of command control signals in the command control signal sequence is equal to the sum of the number of read command data, write command data, and read-write command data.

[0006] For example, at least one embodiment of the present disclosure provides a memory controller, wherein the address of a dynamic random access memory includes a bank address, a row address, and a column address, wherein, when the memory to be tested is a dynamic random access memory, the command generation circuit is further configured to send a refresh command to the dynamic random access memory at a preset time interval to prevent data loss, and to control the opening and closing of the row address to read and write the address of each row in the test address of the dynamic random access memory.

[0007] For example, at least one embodiment of the present disclosure provides a memory controller, wherein the data type information includes a pseudo-random number sequence, and the memory controller further includes: a test vector sending circuit, configured to receive a test address, write command data and a pseudo-random number sequence in the memory to be tested in response to the command data being write command data, and to form a test vector and send it to the dynamic random access memory.

[0008] For example, the memory controller provided by at least one embodiment of the present disclosure further includes: a data return receiving circuit, configured to perform bit width conversion on the received test data read from the test address of the dynamic random access memory to obtain converted test data, generate a valid flag bit for the converted test data, and send the converted test data containing the valid flag bit to the data comparison circuit, wherein the converted test data is data that can be processed by the data comparison circuit, and the bit width of the converted test data is greater than the bit width of the read test data. The data comparison circuit detects whether the target data read from the memory to be tested is consistent with the expected data, including: extracting the target data read from the test address of the dynamic random access memory from the converted test data containing the valid flag bit sent by the data return receiving circuit, and detecting whether the read target data is consistent with the expected data.

[0009] For example, in the memory controller provided by any of the above embodiments of the present disclosure, the test algorithm includes a March algorithm.

[0010] For example, the memory controller provided by any of the above embodiments of the present disclosure further includes: a register configuration word module, which is configured to manage and configure system test parameters of the memory to be tested, receive a test address corresponding to an error sent by a monitoring module, and send a start control signal to the algorithm state machine to control the start of the memory test, wherein the system test parameters include spatial range information, an initial value of a pseudo-random number sequence, and timing parameters.

[0011] At least one embodiment of the present disclosure further provides a computing system comprising a processor, a memory to be tested, and a memory controller, wherein the memory controller comprises an algorithm control circuit, a data generation circuit, a data comparison circuit, and a monitoring circuit, and the memory to be tested comprises a fuse circuit and a redundant storage unit, wherein the algorithm control circuit is configured to generate control information for memory testing based on preset steps of a test algorithm, wherein the control information comprises a test address and corresponding command data in the memory to be tested; the data generation circuit is configured to generate test data for writing to the memory to be tested, and expected data after the test data is read; the data comparison circuit is configured to detect whether the data read from the memory to be tested is consistent with the expected data; the monitoring circuit is configured to send a flag for terminating the memory test to the algorithm control circuit in response to the read target data being inconsistent with the expected data, so as to terminate the memory test and record the test address and corresponding command data corresponding to the error, wherein the read target data being inconsistent with the expected data indicates an error; and the fuse circuit is configured to remap the row where the test address corresponding to the error is located to a row in the redundant storage unit to repair the row where the test address corresponding to the error is located.

[0012] At least one embodiment of the present disclosure also provides an error address locating method based on a memory controller, wherein the memory controller includes an algorithm control circuit, a data generating circuit, a data comparing circuit and a monitoring circuit, and the error address locating method includes: generating control information for memory testing based on preset steps of a test algorithm through the algorithm control circuit, wherein the control information includes a test address and corresponding command data in the memory to be tested; generating test data for writing to the memory to be tested and expected data after the test data is read through the data generating circuit; detecting whether the target data read from the memory to be tested is consistent with the expected data through the data comparing circuit; and sending a flag for terminating the memory test through the monitoring circuit in response to detecting that the read target data is inconsistent with the expected data to terminate the memory test and record the test address and corresponding command data corresponding to the error, wherein inconsistency between the read target data and the expected data indicates an error.

[0013] For example, at least one embodiment of the present disclosure provides an error address locating method, in which control information for memory testing is generated based on preset steps of a test algorithm, including: generating spatial range information and command control signal sequence information according to the execution status of the test algorithm; generating a test address in the memory to be tested by addressing in ascending or descending order based on the spatial range information; and encoding the command control signal sequence information to output command data.

[0014] For example, at least one embodiment of the present disclosure provides an error address locating method, wherein the command control signal sequence information includes a read command signal sequence, a write command signal sequence, or a read-write command signal sequence, and the command control signal sequence information is encoded to output command data, including: respectively encoding the read command signal sequence, the write command signal sequence, or the read-write command signal sequence to output read command data, write command data, or read-write command data, wherein the number of command control signals in the command control signal sequence is equal to the sum of the number of read command data, write command data, and read-write command data.

[0015] For example, at least one embodiment of the present disclosure provides an error address locating method, wherein the address of a dynamic random access memory includes a bank address, a row address, and a column address. Wherein, when the memory to be tested is a dynamic random access memory, the error address locating method further includes: sending a refresh command to the dynamic random access memory at a preset time interval to prevent data loss, and controlling the opening and closing of the row address to read and write the address of each row in the test address of the dynamic random access memory.

[0016] For example, at least one embodiment of the present disclosure provides an error address locating method, wherein the data type information includes a pseudo-random number sequence. After generating test data for writing to the memory to be tested and expected data after the test data is read, the error address locating method further includes: in response to the command data being write command data, receiving the test address, write command data and pseudo-random number sequence in the memory to be tested and forming a test vector to send to the dynamic random access memory.

[0017] For example, at least one embodiment of the present disclosure provides an error address locating method, wherein, after a test vector is composed and sent to a dynamic random access memory, the error address locating method further includes: performing bit width conversion on the received test data read from the test address of the dynamic random access memory to obtain converted test data, generating a valid flag bit for the converted test data, and sending the converted test data containing the valid flag bit to a data comparison circuit, wherein the converted test data is data that can be processed by the data comparison circuit, and the bit width of the converted test data is greater than the bit width of the read test data, wherein detecting whether the target data read from the memory to be tested is consistent with the expected data includes: extracting the target data read from the test address of the dynamic random access memory from the converted test data containing the valid flag bit sent by the data return receiving circuit, and detecting whether the read target data is consistent with the expected data.

[0018] For example, the error address locating method provided in any of the above-mentioned embodiments of the present disclosure further includes: managing and configuring the system test parameters of the memory to be tested through the register configuration word module, receiving the test address corresponding to the error sent by the monitoring module, and sending a start control signal to the algorithm state machine to control the start of the memory test, wherein the system test parameters include spatial range information, the initial value of the pseudo-random number sequence, and timing parameters.

[0019] For example, in any of the above-mentioned embodiments of the present disclosure, the error address locating method provided, wherein the memory to be tested includes a fuse circuit and a redundant memory unit, after sending a flag for terminating the memory test to terminate the memory test and record the test address corresponding to the error, the error address locating method further includes: remapping the row where the test address corresponding to the error is located to a row in the redundant memory unit through the fuse circuit to repair the row where the test address corresponding to the error is located. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly introduced below. Obviously, the drawings in the following description only relate to some embodiments of the present disclosure, rather than limiting the present disclosure.

[0021] Figure 1 A schematic diagram of the overall structure of a memory built-in self-test is shown;

[0022] Figure 2 A schematic structural diagram of a memory controller according to at least one embodiment of the present disclosure is shown;

[0023] Figure 3 A schematic structural diagram of an algorithm control circuit in a memory controller according to at least one embodiment of the present disclosure is shown;

[0024] Figure 4A schematic diagram of the overall structure of a memory built-in self-test according to at least one embodiment of the present disclosure is shown;

[0025] Figure 5 An example of processing an error address in a memory built-in self-test by a memory controller according to at least one embodiment of the present disclosure is shown;

[0026] Figure 6 Shown for Figure 5 Schematic diagram for repairing the error address in ;

[0027] Figure 7 A schematic flow chart illustrating a method for locating an error address based on a memory controller according to at least one embodiment of the present disclosure is shown; and

[0028] Figure 8 A schematic diagram of a computing system according to at least one embodiment of the present disclosure is shown. DETAILED DESCRIPTION

[0029] To make the purpose, technical solutions, and advantages of the embodiments of the present disclosure more clear, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the accompanying drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0030] Unless otherwise defined, the technical or scientific terms used herein shall have the ordinary meaning understood by persons of ordinary skill in the field to which the present disclosure pertains. The terms "first", "second" and similar words used in the present disclosure do not indicate any order, quantity or importance, but are merely used to distinguish between different components. Similarly, terms such as "include" or "comprise" and the like mean that the elements or objects preceding the term encompass the elements or objects listed following the term and their equivalents, without excluding other elements or objects. Terms such as "connect" or "connected" and the like are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. Terms such as "upper", "lower", "left", and "right" are only used to indicate relative positional relationships. When the absolute position of the object being described changes, the relative positional relationship may also change accordingly.

[0031] Memory Built-In Self-Test (MBIST) is a technology used to detect and diagnose embedded memory failures. It automatically performs memory testing by integrating specialized test circuitry within the chip, eliminating the need for external test equipment. MBIST, as part of integrated circuit design, is specifically used to test the functional correctness of embedded memory modules (such as static random access memory (SRAM) and dynamic random access memory (DRAM)). This ensures that the memory is free of defects during manufacturing and maintains reliability during use, which is crucial for improving yield and reducing field failures.

[0032] MBIST performs testing by writing specific data patterns to the memory and reading back the data. If the read data does not match the expected data, it indicates a fault. Currently, MBIST includes the following key components:

[0033] (1) The BIST controller is the core of the entire test system and is responsible for coordinating the entire test process, including initialization, test execution, result collection, and error reporting. It supports multiple test algorithms and is programmable to adapt to different memory types and requirements. For example, commonly used test algorithms include the March algorithm, the Checkerboard algorithm, and the Walking Ones / Zeroes algorithm.

[0034] (2) Test vector generator, which is used to generate a series of input data patterns or sequences for testing the memory. Effective test vectors can cover a wide range of potential fault types, thereby improving test coverage.

[0035] (3) Response analyzer, which is used to receive the data read back from the memory and compare it with the expected value to determine whether there is an error.

[0036] (4) Interface circuit, which is used to provide a communication interface between MBIST and other system components to ensure signal integrity and synchronization during the test process.

[0037] Figure 1 FIG. 1 shows a schematic diagram of the overall structure of a memory built-in self-test. Figure 1 As shown, the overall structure includes a memory controller 100 and a memory 107 .

[0038] The memory controller 100 includes a March C algorithm module 101, a data generation circuit 102, a test vector sending circuit 103, a data return receiving circuit 104, a data comparison circuit 105, and a register configuration word module 106. The March C algorithm module 101 is an example of the aforementioned BIST controller, the test vector sending circuit 103 is an example of the aforementioned test vector generator, and the data return circuit 104 and the data comparison circuit 105 together constitute an example of the aforementioned response analyzer. First, the tester configures the register configuration word module 106 through the host computer to manage macro-level parameter settings such as the startup of the entire test, the test range, the test vector, and the data type. After receiving the configuration startup signal, the March algorithm module 101 generates read and write commands and the specific test address in the corresponding memory according to the predetermined read and write process and sends them to the test vector sending circuit 103. At the same time, after receiving the data type signal, data generation circuit 102 also generates corresponding test data and the expected data after reading. The test data is sent to test vector transmission circuit 103 and, together with the command address information, forms a test vector. The expected data after reading is sent to data comparison circuit 105 for data comparison. For example, because memory 107 is a dynamic random access memory (DRAM), test vector transmission circuit 103 sends the previously generated test vector in the data format of the dynamic random access memory interface protocol (i.e., the DFI protocol) to the physical layer interface (PHY) of memory 107. The PHY then processes the test vector and sends it to memory 107. As a result, the test data is sequentially written into memory 107 according to the MarchC algorithm. After the test data is written, the test data is read and sent to the PHY in sequence. The PHY then sends the read data in the DFI protocol data format to the data return receiving circuit 104. The data return receiving circuit 104 reprocesses the read data and sends it to the data comparison circuit 105 for data comparison. The comparison result is finally sent to the register configuration word module 106 for recording.

[0039] The applicant's research revealed that during the self-test process, if a data comparison error occurs, the test will continue to execute until completion, and only the number of erroneous commands and some statistical error information will be recorded. In actual operation, if an error occurs, a post-package repair (PPR) process is required to repair it, and the specific address of the error must be known. However, because the specific process of this test is not transparent to the public, testers can only determine whether an error has occurred, but not the specific address of the error. They can only narrow down the error through software iterations in the system before determining the specific location. This consumes a significant amount of time and technical resources to use PPR to repair the error during actual operation.

[0040] An embodiment of the present disclosure provides a memory controller, comprising: an algorithm control circuit, a data generation circuit, a data comparison circuit, and a monitoring circuit, wherein the algorithm control circuit is configured to generate control information for memory testing based on preset steps of a test algorithm, wherein the control information includes a test address and corresponding command data in the memory to be tested; the data generation circuit is configured to generate test data for writing to the memory to be tested and expected data after the test data is read; the data comparison circuit is configured to detect whether the target data read from the memory to be tested is consistent with the expected data; and the monitoring circuit is configured to send a flag for terminating the memory test to the algorithm control module in response to the read target data being inconsistent with the expected data to terminate the memory test and record the test address and corresponding command data corresponding to the error, wherein the inconsistency between the read target data and the expected data indicates an error.

[0041] Based on the same inventive concept, an embodiment of the present disclosure further provides an error address location method and a computing system based on a memory controller.

[0042] The memory controller provided by the disclosed embodiments offers excellent flexibility and scalability by decoupling the algorithm control module. Furthermore, by introducing a monitoring circuit to monitor data comparisons in real time, testing can be interrupted when errors occur, maximizing field protection. Furthermore, the memory controller provides rapid location accuracy and clarity, facilitating testing and repairs. Furthermore, the entire test circuit is simple, high-performance, manageable in area, and cost-effective.

[0043] The embodiments of the present disclosure are described in detail below with reference to the accompanying drawings.

[0044] Figure 2 A schematic diagram showing the structure of a memory controller according to at least one embodiment of the present disclosure is shown. Figure 3 FIG. 1 shows a schematic diagram of the structure of the algorithm control circuit in the memory controller of at least one embodiment of the present disclosure. Figure 2 As shown, the memory controller 200 includes an algorithm control circuit 201 , a data generation circuit 202 , a data comparison circuit 203 and a monitoring circuit 204 .

[0045] The algorithm control circuit 201 is configured to generate control information for memory testing based on preset steps of the test algorithm, wherein the control information includes a test address in the memory to be tested and corresponding command data.

[0046] For example, the test algorithm can be any one of the March algorithm, the Checkerboard algorithm, the Walking Ones / Zeroes algorithm, and the general test algorithm. For example, unless otherwise specified, the memory to be tested described below in the present disclosure is a dynamic random access memory DRAM, but it should be understood that the embodiments of the present disclosure do not limit the type of the memory. The address of a DRAM memory generally includes a bank address, a row address, and a column address. For example, the test address of a DRAM memory can include all addresses between (bank0, row0, col0) and (bank1, row10, col10). For example, the above-mentioned test algorithm is the March C algorithm in the March algorithm. Since the March C algorithm has a fixed test process, each step of the process corresponds to a corresponding command control signal (for example, a read command signal, a write command signal, or a read-write command signal), and the read-write command signal becomes the corresponding command data after being encoded.

[0047] For example, in one possible implementation, Figure 3 As shown, the algorithm control circuit 300 (ie Figure 2 The algorithm control circuit 201 in FIG. 1 includes an algorithm state machine 301 , an address generation circuit 302 , and a command generation circuit 303 .

[0048] For example, in one possible implementation, the algorithm state machine 301 is configured to send spatial range information to the address generation circuit 302, send command control signal sequence information to the command generation circuit 303, and send data type information to the command generation circuit 304 according to the execution state of the test algorithm. Figure 2 The data generation circuit 202 in the memory is configured to enable the data generation circuit 202 to generate test data and expected data for memory testing.

[0049] The spatial range can be understood as the test address range of the above-mentioned DRAM memory. The spatial range can be configured through the host computer (i.e., the register configuration word module described later) to flexibly adjust the range of the test address in the DRAM memory. The algorithm state machine 301 forwards the configured spatial range information to the address generation circuit 302 so that it can generate the test addresses (including specific library, row, and column addresses) in the DRAM memory one by one within the spatial range.

[0050] The command control signal sequence information is based on the command control signal corresponding to each step of the test algorithm. For example, in one possible implementation, if the test algorithm is the March C algorithm, the command control signal sequence information corresponding to the March C algorithm includes a read command signal sequence, a write command signal sequence, or a read-write command signal sequence. Specifically, the March C algorithm state machine includes the following steps (1)-(7):

[0051] (1) W0 (↑)

[0052] (2) R0 W1 (↑)

[0053] (3) R1 W0 (↑)

[0054] (4) R0 (↑)

[0055] (5) R0 W1 (↓)

[0056] (6) R1 W0 (↓)

[0057] (7) R0 (↓)

[0058] In the above steps (1) to (7), W0 represents the control signal for writing 0, W1 represents the control signal for writing 1, R0 represents the control signal for reading 0, and R1 represents the control signal for reading 1.

[0059] Since the test address includes multiple addresses, each address in the test address corresponds to a command control signal, that is, the command control signal corresponding to each step belongs to a command control signal sequence. For example, step (1) is a write command control signal sequence, and step (2) is a read-first-then-write command control signal sequence. The remaining steps are similar to steps (1) and (2) and will not be repeated here. Among them, when the test algorithm is the March C algorithm, the data type information is the "0" or "1" involved in the above steps (1)-(7). By adopting the March C algorithm, more error types in DRAM memory testing can be covered, and the comprehensiveness of detection coverage can be improved.

[0060] For example, in another possible implementation, the test algorithm can also be an ordinary random number test algorithm. In this random number test algorithm, the above data type information is generally based on a pseudo-random number sequence. Pseudo-random numbers refer to a series of numbers generated by a deterministic mathematical algorithm. These numbers appear to be generated from a true random process in statistics, but are actually determined by an initial value (called a seed) and a specific algorithm. If the algorithm and seed are known, the generated sequence can be accurately predicted (for example, the initial value of the pseudo-random number sequence can be configured through the register configuration word module described later). Since the order and data of the pseudo-random number sequence are controllable and the generation method is relatively simple, it is very suitable for use as test data for DRAM memory. It should be noted that when the test algorithm is a random number test algorithm, unlike steps (1)-(7) in the March C algorithm, the random number test algorithm only includes sending a write command control signal sequence and then sending a read command signal sequence. Unlike the test data in the March C algorithm, which are "0" and "1", the use of random number testing can increase the randomness of the test data to improve the accuracy of detection.

[0061] For example, in one possible implementation, the address generation circuit 302 is configured to generate test addresses in the DRAM memory using ascending or descending addressing based on the spatial range information. For example, ascending addressing can be represented by "↑" in the March C algorithm above, and descending addressing can be represented by "↓". In ascending addressing, the address starts with all 0s and gradually increases upward. In descending addressing, the address starts with the highest address and gradually decreases downward.

[0062] For example, in one possible implementation, the command generation circuit 303 is configured to encode the command control signal sequence information and output command data. Since the data that can be processed by the subsequent processing circuit has a certain data format, it is necessary to encode the command control signal into command data to convert it into a data format that can be processed by the subsequent circuit.

[0063] For example, in one possible implementation, the command generation circuit 303 encodes the command control signal sequence information and outputs command data, including encoding a read command signal sequence, a write command signal sequence, or a read-write command signal sequence, and outputting read command data, write command data, or read-write command data, where the number of command control signals in the command control signal sequence is equal to the total number of read command data, write command data, and read-write command data. Specifically, each command control signal (e.g., a read command signal) is encoded into a corresponding command data (e.g., read command data).

[0064] For example, in one possible embodiment, the command generation circuit 303 is also configured to send a refresh command to the DRAM memory at a preset time interval to prevent the loss of written data, and to control the opening and closing of the row address to read and write the address of each row in the test address of the DRAM memory.

[0065] Specifically, each storage cell in the DRAM memory is composed of a transistor and a capacitor. The capacitor is used to store charge and represent data (for example, charging represents "1" and discharging represents "0"). However, since the capacitor will gradually leak electricity over time (that is, the charge will slowly drain away), the stored data will gradually be lost. In order to maintain the integrity of the data, the command generating circuit 303 of the present disclosure sends a refresh command to the DRAM memory at regular intervals so that the DRAM memory regularly refreshes the storage cell. The refresh operation ensures that the charge in the capacitor is not completely exhausted by rereading the data in the storage cell and writing it back. And for the DRAM memory, since the same bank address (for example, bank0) can only read and write one row during the reading and writing process (that is, the row that needs to be read and written is in the open state, and the other rows are in the closed state and cannot be read or written), the command generating circuit 303 also needs to control the opening and closing of each row address to read and write data for each row of the test address in the DRAM memory.

[0066] For example, if you want to read or write to the address (bank2, row1, col20), the command generation circuit 303 first needs to open the first row (row1) in the second bank (bank2), and then send the column address (col20) to determine the specific location of the address, so that the address can be read or written. If you want to read or write to another row (row2, col0) in bank2, you need to close the first row and then open the second row (row2), and then send the column address (col0) to determine the next address to be read or written for data reading or writing.

[0067] The algorithm control circuit of the embodiment of the present disclosure is divided into an algorithm state machine, an address generation circuit and a command generation circuit. Figure 1The algorithm implementation and command address generation are decoupled by design, and the three can work together under the premise of being relatively independent, each doing its own job and not interfering with each other. On the one hand, when facing algorithm evolution, the decoupling design only needs to make corresponding changes to the algorithm state machine without changing the entire algorithm control circuit. The other parts can still be used normally, which greatly increases flexibility and scalability; on the other hand, the generation of the above-mentioned test data is also uniformly coordinated by the control signal generated by the algorithm state machine. Data generation needs to be sent out rhythmically in conjunction with the command control signal. Data can be generated and output at the appropriate time to avoid invalid jumps and outputs. The embodiment of the present disclosure is conducive to the centralized and efficient control of coordinated resources through unified management of the algorithm state machine, thereby achieving the purpose of saving power consumption and resources.

[0068] like Figure 2 As shown, the data generating circuit 202 is configured to generate test data for writing into the memory to be tested and expected data after the test data is read;

[0069] For example, when the test algorithm is the March C algorithm, the test data is "0" or "1" in the algorithm (see above for details), and the expected data after reading is also "0" or "1"; when the test algorithm is an ordinary random number algorithm, the test data is the pseudo-random number sequence described above, and each test address corresponds to a pseudo-random number. As for the expected data after reading, since the characteristic of the pseudo-random number is that after the initial value (i.e., the seed above) is determined, the order of subsequent values ​​is determined. Therefore, when the initial value of the pseudo-random number is configured, the data generation circuit 202 can generate the expected data after reading corresponding to each address in the test address.

[0070] For example, in one possible embodiment, the memory controller 200 further includes a test vector sending circuit configured to receive a test address, write command data, and a pseudo-random number sequence from the DRAM memory in response to the command data being write command data, and to compose a test vector and send it to the DRAM memory. It should be noted that the test vector sending circuit sends the test vector to the DRAM memory in a DFI (DDR PHY Interface) protocol format. The DFI protocol is a standard interface protocol between the physical layer (DDR PHY, also referred to as "PHY") connecting the memory controller and the DRAM memory. The following description will be based on the DFI protocol.

[0071] Specifically, the DFI protocol is designed to improve the flexibility and efficiency of the DDR memory subsystem, making the communication between the controller and PHY more standardized and efficient. It mainly includes the following features:

[0072] (1) Timing control: Provides precise timing control mechanism to ensure synchronous operation between the memory controller and PHY.

[0073] (2) Command and data transmission: defines how to pass command, address and data information between the controller and PHY.

[0074] (3) Training sequence: Contains specific training sequences to optimize signal integrity and increase data transmission rate.

[0075] (4) Low power management: supports multiple power states, allowing the system to adjust power consumption as needed.

[0076] Since DRAM memory can only process data in DFI (DDR PHY Interface) protocol format, when test data needs to be written into DRAM memory, the test vector sending circuit ( Figure 2 (not shown) It is necessary to package the write command data, the test address of the data to be written, and the corresponding test data to be written (for example, the random number test algorithm corresponds to a pseudo-random number, and the March C algorithm corresponds to the "0" or "1" required by the execution step) into a test vector and encode it into DFI protocol data and send it to the PHY of the DRAM memory. After receiving the test vector, the PHY processes it and sends it to the corresponding address of the DRAM memory to write the test data.

[0077] The data comparison circuit 203 is configured to detect whether the target data read from the DRAM memory is consistent with the expected data, for example, the expected data comes from the data generation circuit 202 .

[0078] For example, in one possible embodiment, the memory controller 200 also includes: a data return receiving circuit, configured to perform bit width conversion on the received test data read from the test address of the DRAM memory to obtain converted test data, generate a valid flag bit for the converted test data, and send the converted test data containing the valid flag bit to the data comparison circuit, wherein the converted test data is data that can be processed by the data comparison circuit, and the bit width of the converted test data is greater than the bit width of the read test data. The data comparison circuit detects whether the target data read from the DRAM memory is consistent with the expected data, including: extracting the target data read from the test address of the DRAM memory from the converted test data containing the valid flag bit sent by the data return receiving circuit, and detecting whether the read target data is consistent with the expected data sent by the data generation circuit.

[0079] Specifically, the read data is sent to the PHY in the DFI protocol format in the DRAM memory, and then the PHY sends the DFI data to the data return receiving circuit ( Figure 2 (Not shown in the figure), since the data comparison circuit 203 in the memory controller 200 cannot directly process data in the DFI protocol format, the data return receiving circuit performs bit width conversion on the test data read in the DFI protocol format to obtain converted test data. This converted test data is data that the data comparison circuit 203 can process, and a valid flag bit is generated for the converted test data (for example, a binary "0" or "1" can be used to represent "invalid" and "valid" in a certain idle bit of the converted test data packet). This flag is then sent to the data comparison circuit 203 for post-processing. The purpose of generating the valid flag bit is to perform preliminary data screening and eliminate invalid data to improve data comparison processing efficiency. For example, the data bit width of the DFI protocol is 128 bits, while the data comparison circuit processes data with a bit width of 256 bits. The data bit width conversion is performed to facilitate the data comparison circuit to clock-sample the converted test data sent from the data return receiving circuit, which contains the valid flag bit, to extract the target data read from the test address of the DRAM memory, thereby improving data extraction efficiency.

[0080] like Figure 2 As shown, the monitoring circuit 204 is configured to send a flag for terminating the memory test to the algorithm control circuit in response to the data comparison circuit 203 detecting that the target data read from the DRAM memory is inconsistent with the expected data to terminate the memory test and record the test address and corresponding command data corresponding to the error, wherein the inconsistency between the read target data and the expected data indicates an error.

[0081] For example, when the monitoring circuit 204 detects that the read target data is inconsistent with the expected data, it will send a flag for terminating the memory test (for example, a termination signal) to the algorithm state machine. At this time, the algorithm state machine will terminate the control input of the spatial range, command control signal, and test data generation signal. The monitoring circuit 204 then records the specific address corresponding to the error at this time (for example, including the library address, row address, and column address).

[0082] For example, in one possible embodiment, the memory controller 200 also includes: a register configuration word module, which is configured to manage the test parameters of the configuration DRAM memory, receive the test address corresponding to the error sent by the monitoring circuit, and send a start control signal to the algorithm state machine to control the start of the memory test, wherein the test parameters include spatial range information, the initial value of the pseudo-random number sequence, and timing parameters.

[0083] Before the test begins, the tester can configure the word module through the register ( Figure 2(not shown) to set the system parameters for the entire test. For example, the tester can use software to specify the test address range to be tested in the DRAM memory, the initial value of the input pseudo-random number sequence, and the timing of the entire system. For example, the register configuration word module can also receive the specific test address corresponding to the error sent by the monitoring circuit, allowing the subsequent repair module to efficiently repair the address. For example, the register configuration word module can also send a start instruction to the algorithm state machine through the host computer software to control the start of the entire memory test.

[0084] The memory controller provided by the disclosed embodiments achieves excellent flexibility and scalability by decoupling the algorithm control circuit. By introducing a monitoring circuit to monitor data comparison in real time, testing can be interrupted when errors occur, maximizing field protection. Furthermore, the memory controller provides rapid and precise location tracking, directly outputting bank, row, and column addresses, facilitating testing and repair. Furthermore, the entire test circuit is simple, flexible, and offers excellent performance.

[0085] Figure 4 FIG. 1 shows a schematic diagram of the overall structure of a memory built-in self-test according to at least one embodiment of the present disclosure. Figure 4 As shown, the memory controller 400 includes a March C algorithm state machine 401, an address generation circuit 402, a command generation circuit 403, a data generation circuit 404, a test vector sending circuit 405, a data return receiving circuit 406, a data comparison circuit 407, a monitoring circuit 408 and a register configuration word module 409.

[0086] First, the tester configures the system parameters for the entire memory test in the register configuration word module 409 by writing registers. For example, these parameters include the test address range, the initial value of the pseudo-random number, and the system timing parameters. The entire system test process is then initiated through software configuration. After the test begins, the March C algorithm state machine 401 forwards the spatial range information (i.e., the test address range) to the address generation circuit 402 for generating each specific test address. It also sends the command control signal sequence to the command generation circuit 403 for generating corresponding command data (e.g., read and write commands) based on the specific command control signals. It also sends data type information to the data generation circuit 404. It should be noted that the data generation circuit 404 can support a variety of data types, including fixed numbers, random numbers, or user-defined numbers. If the test algorithm is the March C algorithm, the data type is a fixed number, i.e., the "0" or "1" described above. If the test algorithm is a standard random number algorithm, the data type is a pseudo-random number sequence. Driven by the control signals of the March C algorithm state machine, the address generation circuit 402, the command generation circuit 403, and the data generation circuit 404 rhythmically generate row and column addresses, perform command encoding to generate command data, and generate test data to be written. The test vector sending circuit 405 converts the data into the data format of the DFI protocol and sends it to the PHY of the DRAM memory (not shown in the figure), and then sends it to the corresponding test address by the PHY.

[0087] Secondly, the target data read from the DRAM memory is sent to the data return receiving circuit 406 in the data format of the DFI protocol. The data return receiving circuit 406 converts the 128-bit data of the DFI protocol into 256-bit data for subsequent processing by the data comparison circuit 407. The data comparison circuit 407 clock samples the received 256-bit data on the premise of receiving the expected data sent by the data generation circuit 404 to extract the target data read from the DRAM memory test address, and then compares the extracted target data with the expected data.

[0088] Finally, monitoring circuit 408 monitors the comparison results of data comparison circuit 407 in real time. If the data matches, the test address is tested successfully; if the data differs, the test address fails. If the data comparison is inconsistent, monitoring circuit 408 immediately sends a stop signal to March C algorithm state machine 401 to terminate the current memory test. After the test is terminated, monitoring circuit 408 also captures the current command and address signals and stores them in register configuration word module 409. Testers can read the contents of the register configuration word module to obtain the specific address of the error, thus achieving the purpose of stopping the error immediately and quickly locating the error.

[0089] Figure 4The embodiment shown has added a monitoring circuit, which gives the entire circuit two functions: stopping immediately when there is an error and rapid positioning. Figure 1 The solution shown will still execute the test until it is completed if an error occurs after data comparison, and can only record the number of error commands and some statistical error information. In the actual operation process, if an error occurs, PPR needs to be repaired, and the specific error address needs to be known. Therefore, Figure 4 The monitoring circuit in the system can use the stop-on-error and address recording functions to provide the tester with the error site situation, directly and quickly locate the error address, and then start PPR repair to improve repair efficiency.

[0090] For example, in one possible embodiment, when a specific error address is located and PPR repair of the error address is required, the DRAM memory also includes a fuse circuit and a redundant storage unit, wherein the fuse circuit is configured to remap the row where the test address corresponding to the error is located to a row in the redundant storage unit to repair the row where the test address corresponding to the error is located.

[0091] Figure 5 An example of processing an error address in a memory built-in self-test (BIST) by a memory controller according to at least one embodiment of the present disclosure is shown.

[0092] like Figure 5 As shown, a cell at (bank0, ROW6, COL15) of the memory is faulty. When the startup test circuit scans this address, the data read back will not match the expected data, causing an error in data comparison circuit 502. At this point, the real-time information monitoring logic in monitoring circuit 503 detects the error, increments the error counter by 1, and the abort test logic issues an abort signal. The address capture logic captures the current address signal and stores it in a register. The tester then knows the faulty address and can initiate PPR repair work.

[0093] Figure 6 Shown for Figure 5 Schematic diagram for repairing the wrong address.

[0094] like Figure 6 As shown, DRAM manufacturers put some redundant spare memory cells in the production process. These cells will not be used under normal circumstances, but if an address fails, the PPR function can be used to replace the broken row with these spare cells. Figure 6The spare row marked with a black box in the redundant memory cell replaces the row where the error address just occurred (i.e., row 6, filled with a "slash pattern" in the figure), thus achieving the repair effect. It should be noted that the remapped row in the redundant memory cell (for example, the spare row marked with a black box) will be in a blown state after being remapped. This means that the redundant memory cell is only usable once, and each row of the redundant memory cell can only be mapped once.

[0095] Therefore, a necessary condition for replacement is that the tester needs to know the specific address of the fault. The rapid positioning function provided by the embodiment of the present disclosure combined with PPR repair can quickly and accurately find and repair the faulty DRAM particles, which has important economic significance in engineering.

[0096] Figure 7 FIG1 shows a schematic flow chart of a method for locating an error address based on a memory controller according to at least one embodiment of the present disclosure. Figure 7 As shown, the positioning method includes steps S710 to S740.

[0097] Step S710: Generate control information for memory testing based on preset steps of the test algorithm, wherein the control information includes a test address in the memory to be tested and corresponding command data;

[0098] Step S720: Generate test data for writing into the memory under test, and generate and send expected data after reading the test data to the data comparison circuit.

[0099] Step S730: Detecting whether the target data read from the memory to be tested is consistent with the expected data; and

[0100] Step S740: In response to detecting that the target data read from the memory to be tested is inconsistent with the expected data, a flag for terminating the memory test is sent to terminate the memory test and record the test address corresponding to the error, wherein the inconsistency between the read target data and the expected data indicates an error.

[0101] For example, step S710 may be executed by the algorithm control circuit, step S720 may be executed by the data generation circuit, step S730 may be executed by the data comparison circuit, and step S740 may be executed by the monitoring circuit.

[0102] For example, in one possible implementation, generating control information for memory testing based on preset steps of a test algorithm includes: generating spatial range information and command control signal sequence information according to the execution state of the test algorithm; generating test addresses in the memory under test in ascending or descending addressing order based on the spatial range information; and encoding the command control signal sequence information to output command data. For example, these steps can be performed separately by the aforementioned algorithm state machine, address generation circuit, and command generation circuit, and the specific operation methods are not further described here.

[0103] For example, in one possible implementation, the command control signal sequence information includes a read command signal sequence, a write command signal sequence, or a read-write command signal sequence; encoding the command control signal sequence information to output command data includes: encoding the read command signal sequence, the write command signal sequence, or the read-write command signal sequence to output read command data, write command data, or read-write command data, respectively, wherein the number of command control signals in the command control signal sequence is equal to the total number of read command data, write command data, and read-write command data. For example, this step can be performed by the command generation circuit described above, and the specific operation method is not further described herein.

[0104] For example, in one possible embodiment, the data type information includes a pseudo-random number sequence. After generating test data for writing to the memory under test and expected data after reading the test data, the error address location method further includes: in response to the command data being write command data, receiving the test address, write command data, and pseudo-random number sequence in the memory under test, forming a test vector, and transmitting the result to the dynamic random access memory. For example, this step can be performed by the test vector transmitting circuit described above, and the specific operation method is not further described here.

[0105] For example, in one possible embodiment, after the test vector is composed and sent to the dynamic random access memory, the error address location method further includes: performing bit width conversion on the received test data read from the test address of the dynamic random access memory to obtain converted test data, generating a valid flag bit for the converted test data, and sending the converted test data containing the valid flag bit to the data comparison circuit, wherein the converted test data is data that can be processed by the data comparison circuit, and the bit width of the converted test data is greater than the bit width of the read test data, wherein detecting whether the target data read from the memory to be tested is consistent with the expected data includes: extracting the target data read from the test address of the dynamic random access memory from the converted test data containing the valid flag bit sent by the data return receiving circuit, and detecting whether the read target data is consistent with the expected data sent by the data generation circuit. For example, this step can be performed by the above-mentioned data return receiving circuit and the data comparison circuit respectively, and the specific operation method is not repeated here.

[0106] For example, in one possible implementation, the error address location method further includes: managing and configuring system test parameters for the memory under test, receiving a test address corresponding to the error sent by a monitoring circuit, and sending a start control signal to an algorithm state machine to control the start of the memory test. The system test parameters include spatial range information, an initial value of a pseudo-random number sequence, and timing parameters. For example, this step can be performed by the register configuration word module described above, and the specific operation method is not further described here.

[0107] For example, in one possible embodiment, the memory under test includes a fuse circuit and redundant memory cells. After sending a flag to terminate the memory test and recording the test address corresponding to the error, the error address location method further includes remapping the row containing the test address corresponding to the error to a row in the redundant memory cells to repair the row containing the test address corresponding to the error. For example, this step can be performed by the aforementioned fuse circuit, and the specific operation method is not further described here.

[0108] The error address location method based on the memory controller provided by the embodiment of the present disclosure has good flexibility and scalability by decoupling and separating the algorithm control circuit. By introducing a monitoring circuit to monitor the data comparison situation in real time, the test can be interrupted when an error occurs, thereby achieving the purpose of protecting the site to the greatest extent. It also has the ability to quickly locate, accurately and clearly locate, and can directly output the library, row, and column addresses, providing convenience for testers to test and repair.

[0109] At least one embodiment of the present disclosure further provides a computing system. Figure 8 A schematic block diagram of a computing system according to at least one embodiment of the present disclosure is shown.

[0110] For example, Figure 8 As shown, the computing system 800 includes a processor 810, a memory 820, and a memory controller 830. The memory 820 may be the memory provided by any of the aforementioned embodiments of the present disclosure, and the memory controller 830 may be the memory controller provided by any of the aforementioned embodiments of the present disclosure. The memory 820 is also used to store non-transitory computer-readable instructions (e.g., one or more computer program modules). The processor 810 is used to execute the computer program instructions, which, when executed by the processor 810, execute the error address location method based on the memory controller provided by any of the aforementioned embodiments of the present disclosure. The memory 820 and the processor 810 may be interconnected via a bus system and / or other forms of connection mechanisms (not shown).

[0111] Processor 810 may be a device with data processing and / or program execution capabilities, such as a central processing unit (CPU), a tensor processing unit (TPU), a network processor (NP), or a graphics processing unit (GPU). It may also be a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), or other programmable logic device, a discrete gate or transistor logic device, or a discrete hardware component. For example, the central processing unit (CPU) may be an X86 or ARM architecture. Processor 810 may be a general-purpose processor or a special-purpose processor, and may control other components in computing system 800 to perform desired functions.

[0112] For example, memory 820 may include any combination of one or more computer program products, which may include various forms of computer-readable storage media, such as volatile memory and / or non-volatile memory. Volatile memory may include, for example, random access memory (RAM) and / or cache memory. Non-volatile memory may include, for example, read-only memory (ROM), a hard disk, an erasable programmable read-only memory (EPROM), a portable compact disk read-only memory (CD-ROM), a USB memory, a flash memory, and the like. One or more computer program modules may be stored on the computer-readable storage medium, and the processor 810 may execute one or more computer program modules to implement the various functions of the computing system 800. The computer-readable storage medium may also store various applications and data, as well as data used and / or generated by the applications.

[0113] Regarding this disclosure, the following points need to be explained:

[0114] (1) The drawings of the embodiments of the present disclosure only involve structures related to the embodiments of the present disclosure. Other structures can refer to the general design.

[0115] (2) Unless there is any conflict, the features of the same embodiment and different embodiments of the present disclosure may be combined with each other.

[0116] The above are only specific embodiments of the present disclosure, but the scope of protection of the present disclosure is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this disclosure should be included in the scope of protection of the present disclosure. Therefore, the scope of protection of the present disclosure should be based on the scope of protection of the claims.

Claims

1. A memory controller comprising: Algorithm control circuit, data generation circuit, data comparison circuit and monitoring circuit, wherein, The algorithm control circuit is configured to generate control information for memory testing based on preset steps of a test algorithm, wherein the control information includes a test address in the memory to be tested and corresponding command data; The data generating circuit is configured to generate test data for writing into the memory under test and expected data after the test data is read; The data comparison circuit is configured to detect whether the target data read from the memory to be tested is consistent with the expected data; and The monitoring circuit is configured to send a flag for terminating the memory test to the algorithm control circuit in response to the read target data being inconsistent with the expected data to terminate the memory test and record the test address and corresponding command data corresponding to the error, wherein the inconsistency between the read target data and the expected data indicates an error.

2. The memory controller according to claim 1, wherein: The algorithm control circuit includes an algorithm state machine, an address generation circuit and a command generation circuit, wherein: The algorithm state machine is configured to send spatial range information to the address generation circuit, send command control signal sequence information to the command generation circuit, and send data type information to the data generation circuit according to the execution state of the test algorithm so that the data generation circuit generates the test data and the expected data; The address generating circuit is configured to generate a test address in the memory to be tested by addressing in ascending order or descending order based on the spatial range information; and The command generating circuit is configured to encode the command control signal sequence information and output command data.

3. The memory controller according to claim 2, wherein: The command control signal sequence information includes a read command signal sequence, a write command signal sequence, or a read-write command signal sequence. The command generating circuit encodes the command control signal sequence information and outputs command data, including: respectively encoding the read command signal sequence, the write command signal sequence, or the read-write command signal sequence, and outputting read command data, write command data, or read-write command data, wherein the number of command control signals in the command control signal sequence is equal to the sum of the number of the read command data, the write command data, and the read-write command data.

4. The memory controller according to claim 3, wherein: The address of a dynamic random access memory includes a bank address, a row address, and a column address. Wherein, when the memory to be tested is the dynamic random access memory, the command generation circuit is further configured to: A refresh command is sent to the dynamic random access memory at a preset time interval to prevent loss of written data, and the row address is controlled to be opened and closed to read and write the address of each row in the test address of the dynamic random access memory.

5. The memory controller according to claim 4, wherein: The data type information includes a pseudo-random sequence, and the memory controller further includes: The test vector sending circuit is configured to receive the test address, the write command data and the pseudo-random number sequence in the memory to be tested in response to the command data being the write command data, and to compose a test vector and send it to the dynamic random access memory.

6. The memory controller according to claim 5, further comprising: The data return receiving circuit is configured to perform bit width conversion on the test data received and read from the test address of the dynamic random access memory to obtain converted test data, generate a valid flag bit of the converted test data, and send the converted test data containing the valid flag bit to the data comparison circuit, wherein: The converted test data is data that can be processed by the data comparison circuit, and the bit width of the converted test data is greater than the bit width of the read test data. The data comparison circuit detects whether the target data read from the memory to be tested is consistent with the expected data, including: extracting the target data read from the test address of the dynamic random access memory from the converted test data containing the valid flag sent by the data return receiving circuit, and detecting whether the read target data is consistent with the expected data.

7. The memory controller according to any one of claims 1 to 6, wherein: The test algorithm includes the March algorithm.

8. The memory controller according to claim 5, further comprising: The register configuration word module is configured to manage and configure the system test parameters of the memory to be tested, receive the test address corresponding to the error sent by the monitoring circuit, and send a start control signal to the algorithm state machine to control the start of the memory test, wherein the system test parameters include the spatial range information, the initial value of the pseudo-random number sequence and the timing parameters.

9. A computing system comprising a processor, a memory to be tested, and a memory controller, wherein: The memory controller includes an algorithm control circuit, a data generation circuit, a data comparison circuit and a monitoring circuit, and the memory to be tested includes a fuse circuit and a redundant storage unit, wherein: The algorithm control circuit is configured to generate control information for memory testing based on preset steps of a test algorithm, wherein the control information includes a test address in the memory to be tested and corresponding command data; The data generating circuit is configured to generate test data for writing into the memory under test and expected data after the test data is read; The data comparison circuit is configured to detect whether the target data read from the memory to be tested is consistent with the expected data; The monitoring circuit is configured to, in response to the read target data being inconsistent with the expected data, send a flag for terminating the memory test to the algorithm control circuit to terminate the memory test and record a test address and command data corresponding to the error, wherein the inconsistency between the read target data and the expected data indicates an error; and The fuse circuit is configured to remap the row where the test address corresponding to the error is located to a row of the redundant memory cells to repair the row where the test address corresponding to the error is located.

10. A method for locating an error address based on a memory controller, wherein: The memory controller includes an algorithm control circuit, a data generation circuit, a data comparison circuit, and a monitoring circuit. The error address locating method includes: Generate control information for memory testing based on preset steps of a test algorithm through the algorithm control circuit, wherein the control information includes a test address in the memory to be tested and corresponding command data; Generate, by the data generating circuit, test data for writing into the memory to be tested and expected data after reading the test data; detecting, by the data comparison circuit, whether the target data read from the memory to be tested is consistent with the expected data; Through the monitoring circuit, in response to detecting that the read target data is inconsistent with the expected data, a flag for terminating the memory test is sent to terminate the memory test and record the test address and corresponding command data corresponding to the error, wherein the inconsistency between the read target data and the expected data indicates an error.

11. The error address locating method according to claim 10, wherein: The control information for memory testing is generated based on the preset steps of the test algorithm, including: generating spatial range information and command control signal sequence information according to the execution status of the test algorithm; Generate a test address in the memory to be tested by addressing in ascending order or descending order based on the spatial range information; and The command control signal sequence information is encoded to output command data.

12. The error address locating method according to claim 11, wherein: The command control signal sequence information includes a read command signal sequence, a write command signal sequence, or a read-write command signal sequence. The step of encoding the command control signal sequence information and outputting command data includes: The read command signal sequence, write command signal sequence or read-write command signal sequence are respectively encoded to output read command data, write command data or read-write command data, wherein the number of command control signals in the command control signal sequence is equal to the sum of the number of read command data, write command data and read-write command data.

13. The error address locating method according to claim 12, wherein: The address of a dynamic random access memory includes a bank address, a row address, and a column address. Wherein, when the memory to be tested is the dynamic random access memory, the error address locating method further includes: A refresh command is sent to the dynamic random access memory at a preset time interval to prevent data loss, and the row address is controlled to be opened and closed to read and write the address of each row in the test address of the dynamic random access memory.

14. The error address locating method according to claim 13, wherein: The data type information includes a pseudo-random number sequence. After generating test data for writing into the memory to be tested and expected data after reading the test data, the error address locating method further includes: In response to the command data being the write command data, a test address in the memory to be tested, the write command data and the pseudo-random number sequence are received and formed into a test vector which is sent to the dynamic random access memory.

15. The error address locating method according to claim 14, wherein: After the composed test vector is sent to the dynamic random access memory, the error address locating method further includes: The received test data read from the test address of the dynamic random access memory is subjected to bit width conversion to obtain converted test data, a valid flag bit of the converted test data is generated, and the converted test data containing the valid flag bit is sent to the data comparison circuit, wherein, The converted test data is data that can be processed by the data comparison circuit, and the bit width of the converted test data is greater than the bit width of the read test data. Among them, the detection of whether the target data read from the memory to be tested is consistent with the expected data includes: extracting the target data read from the test address of the dynamic random access memory from the converted test data containing the valid flag sent by the data return receiving circuit, and detecting whether the read target data is consistent with the expected data.

16. The method for locating an error address according to any one of claims 10 to 15, further comprising: Through the register configuration word module, the system test parameters of the memory to be tested are managed and configured, the test address corresponding to the error sent by the monitoring circuit is received, and a start control signal is sent to the algorithm state machine to control the start of the memory test, wherein the system test parameters include the spatial range information, the initial value of the pseudo-random number sequence and the timing parameters.

17. The error address locating method according to claim 10, wherein: The memory to be tested includes a fuse circuit and a redundant memory unit. After sending a flag for terminating the memory test to terminate the memory test and recording a test address corresponding to an error, the error address locating method further includes: The row where the test address corresponding to the error is located is remapped to a row in the redundant memory unit through the fuse circuit to repair the row where the test address corresponding to the error is located.

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