Packaging structure and packaging method
Through the vertical stacking packaging structure and DRAM chip heterogeneous storage architecture, combined with a flexible silicon connection layer and heat sink, the high cost and thermal management problems in semiconductor packaging are solved, and high-performance chip integration and low-cost packaging are achieved.
Patent Information
- Application Number
- CN202510745505.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-06-05
- Publication Date
- 2025-09-12
AI Technical Summary
Existing technologies in semiconductor packaging have high manufacturing costs, high process complexity and thermal management challenges, especially traditional silicon interposer packaging and EMIB technology have bottlenecks in high-density integration and heat dissipation.
It adopts a vertically stacked packaging structure and uses DRAM chips to build a heterogeneous storage architecture. Multiple DRAM chips work together, combined with a flexible silicon connection layer to achieve efficient electrical connection and thermal management, and a heat sink is set between the substrates to optimize mechanical support and fixation.
It achieves high-performance chip integration while reducing packaging costs, improving process feasibility, optimizing thermal management and mechanical stability, and solving the problem of excessive packaging volume.
Smart Images
Figure CN120637333A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of semiconductor packaging, and in particular to a packaging structure and a packaging method. Background Art
[0002] The mainstream solutions in the advanced packaging field currently focus on 2.5D / 3D integration technologies. Silicon interposer packaging, represented by CoWoS, utilizes through-silicon via (TSV) interconnects and redistribution layer (RDL) technology to enable vertical stacking of high-bandwidth memory (HBM) and three-dimensional interconnection of heterogeneous chips. While this solution achieves high-density integration within a limited packaging space, it faces significant technical bottlenecks: the TSV interposer process is highly complex, requiring ultra-precision equipment and specialized materials, resulting in exponentially increasing manufacturing costs. Furthermore, the material utilization rate of large silicon interposers is low.
[0003] As an alternative, EMIB embedded interconnect technology replaces traditional through-silicon vias with micro-silicon bridge structures, embedding high-precision interconnect bridges within the substrate to enable inter-chip signal transmission. This technology avoids the high cost of all-silicon interposers and eliminates the wafer-level packaging process, thereby improving production yield. However, its two-dimensional planar interconnect architecture limits further increases in interconnect density. While both solutions increase system bandwidth through HBM stacking, they face high manufacturing costs, increased process complexity, and heat dissipation challenges. Traditional air cooling can no longer meet the required thermal density, making liquid cooling a necessary solution.
[0004] In response to the limitations of existing technologies in cost control, process complexity and thermal management, this solution proposes an innovative packaging architecture design, aiming to achieve high-performance chip integration while optimizing manufacturing economics and improving process feasibility. Summary of the Invention
[0005] The present invention provides a packaging structure and a packaging method, the purpose of which is to solve the problem of high packaging difficulty in the existing AI chip packaging process.
[0006] In order to achieve the above object, an embodiment of the present invention provides a packaging structure, including:
[0007] a first substrate, a first SoC chip and a first DRAM chip being electrically connected to a front surface of the first substrate, wherein at least one of the first SoC chip and the first DRAM chip is provided;
[0008] a heat sink disposed above the front surface of the first substrate and covering the first SoC chip and the first DRAM chip, wherein the heat sink is in surface contact with the first SoC chip and the first DRAM chip;
[0009] A second substrate is provided above the heat sink, wherein a second SoC chip and a second DRAM chip are electrically connected to the front surface of the second substrate, and at least one second SoC chip and at least one second DRAM chip are provided respectively, and a capacitor is provided on the back surface of the second substrate;
[0010] The front surface of the first substrate is arranged opposite to the front surface of the second substrate, and the second SoC chip and the second DRAM chip are attached to the heat sink surface;
[0011] Several first LGA pads and several second LGA pads are respectively provided on the edges of the back side of the first substrate and the back side of the second substrate. Four flexible silicon connection layers are provided between the first substrate and the second substrate. One end of each flexible silicon connection layer is welded to the first LGA pad, and the other end is welded to the second LGA pad. The four flexible silicon connection layers are orthogonally distributed.
[0012] Preferably, the first SoC chip and the first DRAM chip are flip-chip mounted on the front surface of the first substrate via first bumps.
[0013] Preferably, the second SoC chip and the second DRAM chip are flip-chip mounted on the front surface of the second substrate via second bumps.
[0014] Preferably, a first thermal interface layer is provided between the first SoC chip and the first DRAM chip and the heat sink respectively, and a second thermal interface layer is provided between the second SoC chip and the second DRAM chip and the heat sink respectively.
[0015] Preferably, a first underfill layer is provided between the first SoC chip, the first DRAM chip and the first substrate respectively, and the first underfill layer is used to protect the first bumps;
[0016] A second underfill layer is provided between the second SoC chip, the second DRAM chip and the second substrate respectively, and the second underfill layer is used to protect the second bumps.
[0017] The present application also provides a method for manufacturing a packaging structure, which is used to manufacture the aforementioned packaging structure, comprising:
[0018] S10. The first SoC chip and the first DRAM chip are electrically connected to the front side of the first substrate using flip-chip technology;
[0019] S20. The second SoC chip and the second DRAM chip are electrically connected to the front of the second substrate using flip-chip technology;
[0020] S30. Fix a heat sink above the first substrate and attach the back of the first SoC chip and the first DRAM chip to the heat sink. Reverse the second substrate and attach the second SoC chip and the second DRAM chip to the heat sink.
[0021] S40. Soldering capacitors on the back of the second substrate;
[0022] S50. Welding the four flexible silicon connection layers onto the first LGA pad and the second LGA pad, respectively;
[0023] S60. Perform ball planting on the back side of the first substrate.
[0024] Preferably, the step S10 includes S11 and S12, and the step S11 includes: electrically connecting the first SoC chip, the first DRAM chip and the front surface of the first substrate through first bumps;
[0025] The step S12 includes: filling an underfill in a gap formed by the first SoC chip, the first DRAM chip and the first substrate;
[0026] The step S20 includes S21 and S22, wherein the step S21 includes electrically connecting the second SoC chip and the second DRAM chip to the front surface of the second substrate through the second bump, and the step S22 includes filling the gap formed by the second SoC chip, the second DRAM chip and the second substrate with underfill.
[0027] Preferably, the backsides of the first SoC chip and the first DRAM chip are coated with a thermal interface material for connecting to a heat sink;
[0028] The back surfaces of the second SoC chip and the second DRAM chip are coated with a thermal interface material for connecting to a heat sink.
[0029] Preferably, one end point of the flexible silicon connection layer is welded to the second LGA pad on the back side of the second substrate, and the weld point is sealed with glue;
[0030] The packaging structure is turned over, and the other end of the flexible silicon connection layer is welded to the first LGA pad and the welding point is sealed with glue.
[0031] The above solution of the present invention has the following beneficial effects:
[0032] This technical solution innovatively uses DRAM chips to build a heterogeneous storage architecture, and achieves equivalent bandwidth performance to traditional HBM chips through the collaborative work of multiple DRAM chips.
[0033] In terms of packaging architecture, this solution adopts a vertical stacking design, effectively solving the problem of excessive package size caused by horizontally arranging multiple SoC chips and DRAM chips. Furthermore, the clever placement of a heat sink between the substrates not only optimizes system thermal conductivity and alleviates heat accumulation during chip operation, but also provides reliable mechanical support and fixation for the first and second substrates.
[0034] In addition, the flexible silicon connection layer realizes multiple functional integration, providing an efficient electrical connection path for the SoC chip and DRAM chip in the upper and lower substrates, building a thermal management channel throughout the system, and providing the necessary mechanical stability support for the overall packaging structure.
[0035] Other features and advantages of the present invention will be described in detail in the following detailed description. BRIEF DESCRIPTION OF THE DRAWINGS
[0036] Figure 1 It is a perspective view of the present invention;
[0037] Figure 2 It is a longitudinal sectional view of the present invention;
[0038] Figure 3 is a schematic diagram of a first substrate;
[0039] Figure 4 is a schematic diagram of the second substrate.
[0040] [Description of Reference Numerals]
[0041] 10-first substrate, 11-first SoC chip, 12-first DRAM chip, 13-first LGA pad, 14-first bump, 15-first thermal interface layer, 16-capacitor;
[0042] 20- heat sink, 21- support leg;
[0043] 30 - second substrate, 31 - second SoC chip, 32 - second DRAM chip, 33 - second LGA pad, 34 - second bump, 35 - second thermal interface layer,
[0044] 40-Flexible silicon connecting layer. DETAILED DESCRIPTION
[0045] In order to make the technical problems, technical solutions and advantages to be solved by the present invention clearer, a detailed description will be given below with reference to the accompanying drawings and specific embodiments.
[0046] SoC chip: System on Chip chip;
[0047] DRAM chip: Dynamic Random Access Memory chip;
[0048] LGA pad: Land Grid Array, also known as pad grid array;
[0049] Flexible silicon connection layer: Flexible Silicon.
[0050] like Figures 1-4 As shown, an embodiment of the present invention provides a packaging structure, which includes a first substrate 10, a heat sink 20, and a second substrate 30. The front surface of the first substrate 10 is electrically connected to a first SoC chip 11 and a first DRAM chip 12, and at least one first SoC chip 11 and first DRAM chip 12 are respectively provided. The first SoC chip 11 and the first DRAM chip 12 are electrically connected to the front surface of the first substrate 10, and the heat sink 20 is provided above the front surface of the first substrate 10 and covers the first SoC chip 11 and the first DRAM chip 12. The heat sink 20 is in contact with the first SoC chip 11 and the first DRAM chip 12.
[0051] The second substrate 30 is disposed above the heat sink 20. A second SoC chip 31 and a second DRAM chip 32 are electrically connected to the front surface of the second substrate 30. At least one of the second SoC chip 31 and the second DRAM chip 32 is provided. The back surface of the second substrate 30 is also electrically connected to the capacitor 16. The front surface of the first substrate 10 is disposed opposite the front surface of the second substrate 30, so that the second SoC chip 31 and the second DRAM chip 32 are in contact with the heat sink 20.
[0052] There are several first LGA pads 13 on the back edge of the first substrate 10, and the same number of second LGA pads 33 as the first LGA pads 13 are provided on the back edge of the second substrate 30. Four flexible silicon connection layers 40 are arranged between the first substrates 10, and one end of each flexible silicon connection layer 40 is welded to the first LGA pad 13, and the other end is welded to the second LGA pad 33, and the four flexible silicon connection layers 40 are distributed orthogonally.
[0053] The first SoC chip 11 and the first DRAM chip 12 are flip-chip mounted on the front surface of the first substrate 10 through the first bumps 14 , thereby achieving electrical connection between the first SoC chip 11 and the first DRAM chip 12 and the first substrate 10 .
[0054] Similarly, the second SoC chip 31 and the second DRAM chip 32 are flip-chip mounted on the front surface of the second substrate 30 through the second bumps 34 , thereby achieving electrical connection between the second SoC chip 31 and the second DRAM chip 32 and the second substrate 30 .
[0055] Preferably, since the first SoC chip 11 and the first substrate 10 are connected via the first bumps 14, resulting in a gap between the first SoC chip 11 and the first substrate 10, an underfill is filled between the first SoC chip 11 and the first substrate 10 to form a first underfill layer between the first SoC chip 11 and the first substrate 10. This serves to strengthen the connection between the first SoC chip 11 and the first substrate 10 and to protect the first bumps 14. Similarly, a gap also exists between the first DRAM chip 12 and the first substrate 10, and therefore a first underfill layer is provided between the first DRAM chip 12 and the first substrate 10.
[0056] It can be understood that a second underfill layer is provided between the second SoC chip 31 and the second substrate 30 , and a second underfill layer is also provided between the second DRAM chip 32 and the second substrate 30 .
[0057] In some embodiments of the present application, a first thermal interface layer 15 is disposed between the first SoC chip 11 and the heat sink 20. The first thermal interface layer 15 is bonded between the first SoC chip 11 and the heat sink 20, thereby both connecting the first SoC chip 11 and the heat sink 20 and enhancing the heat dissipation capability of the first SoC chip 11. Similarly, a first thermal interface layer 15 is also disposed between the first DRAM chip 12 and the heat sink 20.
[0058] A second thermal interface layer 35 is provided between the second SoC chip 31 and the heat sink 20 . The second thermal interface layer 35 is bonded between the second SoC chip 31 and the heat sink 20 . Similarly, a second thermal interface layer 35 is provided between the second DRAM chip 32 and the heat sink 20 .
[0059] In some embodiments of the present application, the center of the bottom of the heat sink 20 is recessed upward to form a leg 21. A first thermal interface layer 15 is disposed between the leg 21 and the first substrate 10 to secure the leg 21 to the first substrate 10. Furthermore, the space formed by the upward recess of the heat sink 20 accommodates the aforementioned first SoC chip 11 and first DRAM chip 12. The aforementioned first thermal interface layer 15 is disposed on the backside of the first SoC chip 11 and the first DRAM chip 12, and the first thermal interface layer 15 is bonded to the upwardly recessed surface of the heat sink 20. The heat sink 20 provides mechanical support, thereby protecting the first SoC chip 11 and the first DRAM chip 12. Furthermore, the heat sink 20 can also dissipate heat from the first SoC chip 11 and the first DRAM chip 12.
[0060] The packaging cost of this application is low and the packaging technology threshold is low, which can alleviate the high cost and difficult process technology faced by most small and medium-sized enterprises in developing high-end packaging technology, and provide them with transitional products in the high-end packaging technology business segment.
[0061] The present application also provides a method for manufacturing a packaging structure, which is used to manufacture the aforementioned packaging structure, comprising the following steps:
[0062] S10. The first SoC chip 11 and the first DRAM chip 12 are electrically connected to the front side of the first substrate 10 using flip-chip technology;
[0063] Specifically, step S10 includes step S11 and step S12, wherein step S11 includes: flip-mounting the first SoC chip 11 on the first substrate 10 through the first bumps 14, and flip-mounting the first DRAM chip 12 on the first substrate 10 through the first bumps 14;
[0064] S12 : filling an underfill between the first SoC chip 11 and the first substrate 10 to form the aforementioned first underfill layer, and filling an underfill between the first DRAM chip 12 and the first substrate 10 to form the aforementioned first underfill layer.
[0065] S20. The second SoC chip 31 and the second DRAM chip 32 are electrically connected to the front of the second substrate 30 using flip-chip technology;
[0066] Specifically, step S20 includes step S21 and step S22, wherein step S21 includes: flip-chipping the second SoC chip 31 on the second substrate 30 through the second bumps 34, and flip-chipping the second DRAM chip 32 on the first substrate 10 through the second bumps 34;
[0067] S22 : filling the space between the second SoC chip 31 and the second substrate 30 with underfill to form the aforementioned second underfill layer, and filling the space between the second DRAM chip 32 and the second substrate 30 with underfill to form the aforementioned second underfill layer.
[0068] In this embodiment, the SoC chip and the DRAM chip are mounted on the substrate in a flip-chip manner, which can shorten the interconnection path and improve the density of the signal.
[0069] S30. A heat sink 20 is fixed above the first substrate 10, and the back surfaces of the first SoC chip 11 and the first DRAM chip 12 are respectively attached to the heat sink 20. After attaching the heat sink 20, the second substrate 30 is turned over so that the front surface of the second substrate 30 faces downward, and the second SoC chip 31 and the second DRAM chip 32 are attached to the heat sink 20.
[0070] In this process, a thermal interface material is coated on the lower surface of the heat sink 20, and the heat sink 20 is bonded to the front surface of the first substrate 10, thereby forming a first thermal interface material layer between the first substrate 10 and the heat sink 20, between the first SoC chip 11 and the heat sink 20, and between the first DRAM chip 12 and the heat sink 20. It will be understood that the lower surface of the heat sink 20 includes the lower surface of the legs 21 and the upwardly concave surface in the middle of the heat sink 20.
[0071] After the heat sink 20 is attached, the second substrate 30 is processed. After the thermal interface material is applied to the backsides of the second SoC chip 31 and the second DRAM chip 32, the second substrate 30 is turned over so that the front side of the second substrate 30 faces downward. The second SoC chip 31 and the second DRAM chip 32 are attached to the heat sink 20 via the thermal interface material, thereby forming a second thermal interface layer 35 between the second SoC chip 31 and the second substrate 30, and between the second DRAM chip 32 and the second substrate 30.
[0072] S40 . Solder the capacitor 16 on the back surface of the second substrate 30 .
[0073] The back of the second substrate 30 also has capacitor pads. The capacitor 16 is soldered using SMT (Surface Mount Technology), and glue is applied at the solder joints to solidify them. The capacitor 16 can stabilize the power supply voltage of the package structure. Using glue to solidify the solder joints can reduce the stress caused by thermal expansion of the material, mechanically protect the solder joints, and extend their service life. At the same time, solidifying the solder joints prevents the solder joints from melting during reflow soldering when the package structure is installed on the PCB, resulting in interconnect failure.
[0074] S50 . Solder four flexible silicon connection layers 40 onto the first LGA pad 13 and the second LGA pad 33 , respectively.
[0075] A first LGA pad 13 is provided on the back surface of the first substrate 10 . The first LGA pad 13 is provided at four edges of the first substrate 10 .
[0076] Second LGA pads 33 are further provided on the back surface of the second substrate 30 . The second LGA pads 33 are provided at four edges of the second substrate 30 .
[0077] Apply solder paste to the second LGA pad 33, then solder one end of the flexible silicon connection layer 40 to the second LGA pad 33. Secure the solder joints between the flexible silicon connection layer 40 and the second LGA pad 33 with glue. After glue application, invert the entire package structure. Apply solder paste to the first LGA pad 13, and use a fixture to gently press the other end of the flexible silicon connection layer 40 onto the first LGA pad 13. Solder the flexible connection layer to the first LGA pad 13 and secure it with glue.
[0078] The flexible silicon connection layer 40 is bendable, thin, and can achieve electrical connection between the first substrate 10 and the second substrate 30 .
[0079] S60 . Perform ball planting on the back side of the first substrate 10 for connecting to the PCB.
[0080] Solder balls are planted on the back side of the first substrate 10 , and the solder balls are electrically connected to the first substrate 10 , so that the package structure can be electrically connected to other PCBs.
[0081] The above is a preferred embodiment of the present invention. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principles of the present invention. These improvements and modifications should also be regarded as within the scope of protection of the present invention.
Claims
1. A packaging structure, characterized in that: include: A first substrate (10), wherein a first SoC chip (11) and a first DRAM chip (12) are electrically connected to the front surface of the first substrate (10), and at least one of the first SoC chip (11) and the first DRAM chip (12) is provided; A heat sink (20) is provided above the front surface of the first substrate (10) and covers the first SoC chip (11) and the first DRAM chip (12), wherein the heat sink (20) is in surface contact with the first SoC chip (11) and the first DRAM chip (12); A second substrate (30) is arranged above the heat sink (20); a second SoC chip (31) and a second DRAM chip (32) are electrically connected to the front surface of the second substrate (30); at least one second SoC chip (31) and at least one second DRAM chip (32) are respectively provided; and a capacitor (16) is provided on the back surface of the second substrate (30); The front surface of the first substrate (10) is arranged opposite to the front surface of the second substrate (30), and the second SoC chip (31) and the second DRAM chip (32) are surface-attached to the heat sink (20); A plurality of first LGA pads (13) and a plurality of second LGA pads (33) are respectively provided on the back side of the first substrate (10) and the edge of the back side of the second substrate (30); four flexible silicon connection layers (40) are provided between the first substrate (10) and the second substrate (30); one end of each flexible silicon connection layer (40) is welded to the first LGA pad (13), and the other end is welded to the second LGA pad (33); the four flexible silicon connection layers (40) are orthogonally distributed.
2. The packaging structure according to claim 1, wherein: The first SoC chip (11) and the first DRAM chip (12) are respectively flip-mounted on the front surface of the first substrate (10) via first bumps (14).
3. The packaging structure according to claim 2, wherein: The second SoC chip (31) and the second DRAM chip (32) are respectively flip-mounted on the front surface of the second substrate (30) via second bumps (34).
4. The packaging structure according to claim 1, wherein: A first thermal interface layer (15) is provided between the first SoC chip (11) and the first DRAM chip (12) and the heat sink (20), and a second thermal interface layer (35) is provided between the second SoC chip (31) and the second DRAM chip (32) and the heat sink (20).
5. The packaging structure according to claim 3, wherein: A first underfill layer is provided between the first SoC chip (11), the first DRAM chip (12) and the first substrate (10), respectively, and the first underfill layer is used to protect the first bump (14); A second bottom filling layer is provided between the second SoC chip (31), the second DRAM chip (32) and the second substrate (30), respectively, and the second bottom filling layer is used to protect the second bumps (34).
6. A method for manufacturing a packaging structure, used to manufacture the packaging structure according to any one of claims 1 to 5, characterized in that: include: S10. The first SoC chip (11) and the first DRAM chip (12) are electrically connected to the front surface of the first substrate (10) using a flip-chip technology; S20. The second SoC chip (31) and the second DRAM chip (32) are electrically connected to the front side of the second substrate (30) using flip-chip technology; S30. Fixing a heat sink (20) above the first substrate (10), and attaching the back surfaces of the first SoC chip (11) and the first DRAM chip (12) to the heat sink (20), turning the second substrate (30) over, and attaching the second SoC chip (31) and the second DRAM chip (32) to the heat sink (20); S40. Soldering a capacitor (16) on the back side of the second substrate (30); S50. Soldering four flexible silicon connection layers (40) respectively onto the first LGA pad (13) and the second LGA pad (33); S60. Perform ball planting on the back side of the first substrate (10).
7. The method for manufacturing a packaging structure according to claim 6, wherein: The step S10 includes steps S11 and S12, wherein the step S11 includes: electrically connecting the first SoC chip (11), the first DRAM chip (12) and the front surface of the first substrate (10) via a first bump (14); The step S12 comprises: filling an underfill into a gap formed by the first SoC chip (11), the first DRAM chip (12) and the first substrate (10); The step S20 includes steps S21 and S22, wherein the step S21 includes electrically connecting the second SoC chip (31) and the second DRAM chip (32) to the front surface of the second substrate (30) via a second bump (34), and the step S22 includes filling a gap formed between the second SoC chip (31), the second DRAM chip (32) and the second substrate (30) with an underfill.
8. The method for manufacturing a packaging structure according to claim 7, wherein: The back surfaces of the first SoC chip (11) and the first DRAM chip (12) are coated with a thermal interface material for connecting to a heat sink (20); The back surfaces of the second SoC chip (31) and the second DRAM chip (32) are coated with a thermal interface material for connecting to a heat sink (20).
9. The method for manufacturing a packaging structure according to claim 8, wherein: Welding one end of the flexible silicon connection layer (40) to the second LGA pad (33) on the back side of the second substrate (30), and sealing the welding point with glue; The packaging structure is turned over, the other end of the flexible silicon connection layer (40) is welded to the first LGA welding pad (13), and the welding point is sealed with glue.